CN216216815U - Time delay circuit - Google Patents
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- CN216216815U CN216216815U CN202122422290.7U CN202122422290U CN216216815U CN 216216815 U CN216216815 U CN 216216815U CN 202122422290 U CN202122422290 U CN 202122422290U CN 216216815 U CN216216815 U CN 216216815U
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Abstract
A time delay circuit comprises a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the first current loop of the current mirror module is from a voltage end Vcp to a voltage end Vss, and the second current loop of the current mirror module is from a voltage end Vcn to a voltage end Vss; when the input voltage IN of the input and initialization module is at a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m: 1; once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the determination output module outputs a second control level, the second control level has the same phase as the first control level, and the delay time Tdelay is a time difference between a starting point of the first control level and a starting point of the second control level. Therefore, the utility model reduces the actual charging current to the capacitor C0 by adding the current mirror module, thereby increasing the delay time Tdelay and making the chip area of the formed circuit much smaller than that of the traditional circuit.
Description
Technical Field
The utility model belongs to the technical field of circuit design, and relates to a delay circuit.
Background
The delay circuit is a circuit which can output the enabling function after a period of time passes after the enabling signal is input, the motor is started or closed immediately by pressing the switch at ordinary times, but the delay circuit can be started or closed again at equal time (the time can be adjusted). For example, the sound control LED lamp is turned off after the sound control lamp is turned on, which is to provide convenience for passers-by to walk later.
In the design of an integrated circuit, in order to design a larger delay time Tdelay and ensure accuracy, the same current source is used, and most of the current sources are adopted to charge a capacitor C0 to a certain threshold value so as to serve as a signal delay circuit. Referring to fig. 1, fig. 1 is a functional block diagram of a delay circuit in the prior art, and as shown in fig. 1, the delay circuit includes a current source, an input module, a capacitor C0 and a comparator. The capacitor C0 and the input module are connected in parallel between the positive input end Vc and the voltage end Vss of the comparator, the negative input end of the comparator is connected with the reference voltage Vref, and the current source is connected between the voltage end Vcc and the voltage end Vc. Once the input module inputs the on-off control signal IN, the voltage difference across the capacitor C0 changes from 0V IN the initial state to Vref, and the change value is Vref, at this time, the comparator outputs the on-off control signal, that is, the control signal is delayed by the time Tdelay.
Referring to fig. 2, fig. 2 is a waveform diagram of each node of the delay circuit of fig. 1. As shown IN fig. 2, when the input voltage IN is inputted to the high level, the voltage terminal Vc starts to increase from 0, and when the voltage value thereof increases to the reference voltage Vref, the comparator outputs the high level after the delay time Tdelay.
Assuming that the current source is I0 and the reference voltage Vref is usually fixed in the circuit, there are:
I0*Tdelay＝C0*Vref
however, many application circuits require a relatively large delay time Tdelay, and after selecting a suitable current source I0, a large capacitor C0 is required to obtain a relatively ideal state based on the above formula, but a larger layout area is required when the size of the capacitor C0 is increased in the integrated circuit design, which means more cost.
SUMMERY OF THE UTILITY MODEL
To solve the above technical problem, the present invention provides a delay circuit, which has the following technical scheme:
a time delay circuit comprises a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input end of the determination output module and an input end of the current mirror module, the positive input end of the determination output module is connected to the voltage terminal Vcp, and the other input end of the current mirror module is connected to the voltage terminal Vcn; the negative input end of the judgment output module is connected with a reference voltage Vref; the current source is connected between a voltage end Vcc and a voltage end Vcp; one end of the input and initialization module is connected with a voltage terminal Vss, the input end of the input and initialization module is connected with an IN, the first output end of the input and initialization module is connected with a voltage terminal Vcp, the second output end of the input and initialization module is connected with a voltage terminal Vcn, the first current loop of the current mirror module is connected from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is connected from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is at a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m: 1; the determination output module outputs a second control level once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, and the delay time Tdelay is a time difference between an activation point of the first control level and an activation point of a second control level when the second control level reaches the first control level.
Further, the current mirror module includes a first N-type transistor NFET1 and a second N-type transistor NFET 2; the ratio of the channel width to length ratio of the first N-type transistor NFET1 to the channel width to length ratio of the second N-type transistor NFET2 is 1: m; the gates of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vcn; the sources of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to a voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to a voltage terminal Vcp.
Further, the delay time is as follows: tdelay ═ m +1) C0 (Vref-Vth)/I1 where Vth is the turn-on threshold of NFET1, i.e., the final voltage of voltage terminal Vcn.
Further, the current source comprises a current mirror and a bias current module, the current mirror comprises a first P-type transistor PFET1 and a second P-type transistor PFET2, and the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module are configured to form a current constant source for charging a voltage terminal Vcp connected to the capacitor C0.
Further, the input and initialization block includes an inverter INV, a third N-type transistor NFET3, and a fourth N-type transistor NFET 4; the inverter INV is connected between an input IN and the gates of the third N-type transistor NFET3 and fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the sources of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are connected to the voltage terminal Vss.
Further, the judgment output module is a comparison module.
From the above technical solutions, in the embodiment of the delay circuit of the present invention, when a requirement of designing a larger delay time Tdelay is met, the capacitance of the capacitor C0 can be reduced under the same current source condition. If Vcc is 5V, Vss is 0V, Vref is 2.5V, Vth is 0.7V, and m is 8, the capacitance of the circuit of the present invention is only about 15.4% of the capacitance of the conventional circuit. That is, in the circuit layout (layout), the capacitor C0 usually occupies a major area, and therefore, the chip area of the circuit formed by the present invention is much smaller than that of the conventional circuit, and the manufacturing cost is much smaller than that of the conventional circuit.
Drawings
FIG. 1 is a functional block diagram of a prior art delay circuit
FIG. 2 is a waveform diagram of each node of the delay circuit shown in FIG. 1
FIG. 3 is a functional block diagram of a delay circuit according to an embodiment of the present invention
FIG. 4 is a diagram of a delay circuit according to a preferred embodiment of the present invention
Detailed Description
The following describes the embodiments of the present invention in further detail with reference to fig. 3-4.
Referring to fig. 3, fig. 3 is a functional block diagram of a delay circuit according to an embodiment of the utility model. As shown in fig. 3, the delay circuit includes a current source, an input and initialization module, a capacitor C0, a current mirror module, and a determination output module.
The capacitor C0 is connected between the positive input end of the determination output module and an input end of the current mirror module, the positive input end of the determination output module is connected to the voltage terminal Vcp, and the other input end of the current mirror module is connected to a connection point between the voltage terminal Vcn and the positive input end of the determination output module; the negative input end of the judgment output module is connected with a reference voltage Vref; the current source is connected between a voltage end Vcc and a voltage end Vcp; one end of the input and initialization module is connected with a voltage terminal Vss, the input end of the input and initialization module is connected with an IN, the first output end of the input and initialization module is connected with a voltage terminal Vcp, the second output end of the input and initialization module is connected with a voltage terminal Vcn, the first current loop of the current mirror module is connected from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is connected from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is at the first control level, the ratio of the current I2 of the first current loop and the current I4 of the second current loop is m: 1.
Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the determination output module outputs a second control level, and the delay time Tdelay is a time difference between an activation point of the first control level and an activation point of a second control level when the second control level reaches the first control level.
That is, the current mirror module reduces the actual charging current and increases the delay time Tdelay, so that the delay circuit of the present invention can increase the delay time Tdelay without increasing the capacitance of the capacitor C0 and maintaining the current constant current source.
Referring to fig. 4, fig. 4 is a schematic diagram of a delay circuit according to a preferred embodiment of the utility model. In the embodiment of the present invention, the judgment output module is a comparison module, which may be a comparator. The supply voltage Vcc of the current source and the comparator may be, for example, 5 volts.
Specifically, the capacitor C0 is connected between the positive input end of the determination output module and an input end of the current mirror module, and as can be seen from the circuit diagram, the positive input end of the determination output module is connected to the voltage terminal Vcp, and the other input end of the current mirror module is connected to the voltage terminal Vcn; and the negative input end of the judgment output module is connected with the reference voltage Vref.
The current source is connected between a voltage end Vcc and a voltage end Vcp; the first initialization loop of the input and initialization module is from voltage terminal Vcp to voltage terminal Vss.
The first current loop of the current mirror module is connected from a voltage end Vcp to a voltage end Vss, the input end of the input and initialization module is connected with IN, the second initialization loop of the input and initialization module is connected from a voltage end Vcn to a voltage end Vss, and the second current loop of the current mirror module is connected from a voltage end Vcn to a voltage end Vss.
In an embodiment of the present invention, the current mirror block may include a first N-type transistor NFET1 and a second N-type transistor NFET 2; the ratio of the channel width to length ratio of the first N-type transistor NFET1 to the channel width to length ratio of the second N-type transistor NFET2 is 1: m; the gates of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vcn; the sources of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to a voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to a voltage terminal Vcp.
When the input voltage IN of the input and initialization module is at the first control level, the ratio of the current I2 of the first current loop and the current I4 of the second current loop is m: 1. Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the determination output module outputs a second control level, and the delay time Tdelay is a time difference between an activation point of the first control level and an activation point of a second control level when the second control level reaches the first control level.
Typically, the delay time is: tdelay ═ m +1) C0 (Vref-Vth)/I1
Where Vth is the turn-on threshold of the first N-type transistor NFET1, i.e., the final voltage of the voltage terminal Vcn. That is, the delay time Tdelay is determined by m, the capacitance value of the capacitor C0, Vth, and the reference voltage. The larger m is, the larger the delay time Tdelay is if the capacitance value of the capacitor C0, Vth, and reference voltage are constant.
The current source may include a current mirror including a first P-type transistor PFET1 and a second P-type transistor PFET2, the first P-type transistor PFET1, the second P-type transistor PFET2, and a bias current module to form a current constant current source to charge the Vcp terminal of the capacitor C0.
The input and initialization module includes an inverter INV, a third N-type transistor NFET3, and a fourth N-type transistor NFET 4; the inverter INV is connected between an input IN and the gates of the third N-type transistor NFET3 and fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the sources of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are connected to the voltage terminal Vss.
In the embodiment of the present invention, VSS may be 0V for convenience of description, and the parameters may be 2.5V for reference voltage Vref, 0.7V for Vth, and 8 for m.
When the delay circuit is IN the operation initialization state, the input voltage IN of the input and initialization module is 0V, the inverter INV outputs a high level, the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are turned on, Vcn is Vcp is 0V, and the U1 of the comparator outputs OUT is 0V; at this time, the delay circuit is in an initial state and is in a standby state.
When the delay circuit starts to work, the input voltage IN of the input and initialization module goes high to Vcc, the inverter INV outputs low level, and the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are closed; at this time, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module constitute a current constant current source for charging the voltage terminal Vcp of the capacitor C0; at this point, the first N-type transistor NFET1 and the second N-type transistor NFET2 form a current mirror pair that operates, and NFET2 discharges the I2 to the Vcp terminal, where:
I1-I2 ═ I3, I2 ═ m ═ I4, I3 ═ I4, so I3 ═ I4 ═ I1/(m +1)
Further, since Tdelay is CV/I, (m +1) C0 (Vref-Vth)/I1
Where Vref-Vth is the voltage drop variation across capacitor C0, and Vth is the turn-on threshold of NFET1, i.e., the final Vcn voltage.
When Vcp > Vref, the U1 output of the comparator block is high, i.e., the output OUT is VCC. That is, the delay time Tdelay is a rising edge time from when the input voltage IN becomes high to when the output OUT becomes high. When the input voltage IN goes low, the whole circuit enters the initial state again.
In summary, the present invention reduces the actual charging current to the capacitor C0 by adding the current mirror module, so as to increase the delay time Tdelay, that is, the same current source can achieve the purpose of reducing the capacitance value of the capacitor C0, and the chip area of the formed circuit is much smaller than that of the conventional circuit, so that the manufacturing cost is much smaller than that of the conventional circuit.
The above description is only for the preferred embodiment of the present invention, and the embodiment is not intended to limit the scope of the present invention, so that all the equivalent structural changes made by using the contents of the description and the drawings of the present invention should be included in the scope of the present invention.
Claims (6)
1. A time delay circuit is characterized by comprising a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input end of the determination output module and an input end of the current mirror module, the positive input end of the determination output module is connected to the voltage terminal Vcp, and the other input end of the current mirror module is connected to the voltage terminal Vcn; the negative input end of the judgment output module is connected with a reference voltage Vref; the current source is connected between a voltage end Vcc and a voltage end Vcp; one end of the input and initialization module is connected with a voltage terminal Vss, the input end of the input and initialization module is connected with an IN, the first output end of the input and initialization module is connected with a voltage terminal Vcp, the second output end of the input and initialization module is connected with a voltage terminal Vcn, the first current loop of the current mirror module is connected from the voltage terminal Vcp to the voltage terminal Vss, and the second current loop of the current mirror module is connected from the voltage terminal Vcn to the voltage terminal Vss; when the input voltage IN of the input and initialization module is at a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m: 1; the determination output module outputs a second control level once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, and the delay time Tdelay is a time difference between an activation point of the first control level and an activation point of a second control level when the second control level reaches the first control level.
2. The delay circuit of claim 1, wherein the current mirror block comprises a first N-type transistor NFET1 and a second N-type transistor NFET 2; the ratio of the channel width to length ratio of the first N-type transistor NFET1 to the channel width to length ratio of the second N-type transistor NFET2 is 1: m; the gates of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vcn; the sources of the first N-type transistor NFET1 and second N-type transistor NFET2 are commonly connected at a voltage terminal Vss; the drain of the first N-type transistor NFET1 is connected to a voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to a voltage terminal Vcp.
3. The delay circuit of claim 2, wherein the delay time is:
Tdelay＝(m+1)C0*(Vref-Vth)/I1
where Vth is the turn-on threshold of NFET1, the last voltage of voltage terminal Vcn.
4. The delay circuit of claim 1, wherein the current source comprises a current mirror and a bias current block, the current mirror comprising a first P-type transistor PFET1 and a second P-type transistor PFET2, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current block configured to form a current constant source for charging a voltage terminal Vcp connected to the capacitor C0.
5. The delay circuit of claim 1, wherein the input and initialization block comprises an inverter INV, a third N-type transistor NFET3, and a fourth N-type transistor NFET 4; the inverter INV is connected between an input IN and the gates of the third N-type transistor NFET3 and fourth N-type transistor NFET4, the drain of the third N-type transistor NFET3 is connected to the voltage terminal Vcn, the drain of the fourth N-type transistor NFET4 is connected to the voltage terminal Vcp, and the sources of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are connected to the voltage terminal Vss.
6. The delay circuit of claim 1, wherein the decision output module is a comparison module.
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|---|---|---|---|
| CN202122422290.7U CN216216815U (en) | 2021-10-09 | 2021-10-09 | Time delay circuit |
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| CN202122422290.7U CN216216815U (en) | 2021-10-09 | 2021-10-09 | Time delay circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113904664A (en) * | 2021-10-09 | 2022-01-07 | 无锡裕芯电子科技有限公司 | a delay circuit |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113904664A (en) * | 2021-10-09 | 2022-01-07 | 无锡裕芯电子科技有限公司 | a delay circuit |
| CN113904664B (en) * | 2021-10-09 | 2025-01-28 | 无锡裕芯电子科技有限公司 | A delay circuit |
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