CN113904664B - A delay circuit - Google Patents
A delay circuit Download PDFInfo
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- CN113904664B CN113904664B CN202111173923.3A CN202111173923A CN113904664B CN 113904664 B CN113904664 B CN 113904664B CN 202111173923 A CN202111173923 A CN 202111173923A CN 113904664 B CN113904664 B CN 113904664B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
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Abstract
一种延时电路，包括电流源、输入与初始化模块、电容C0、电流镜模块和判断输出模块；电流镜模块的第一电流回路从电压端Vcp到电压端Vss，电流镜模块的第二电流回路从电压端Vcn到电压端Vss；当输入与初始化模块的输入电压IN为第一控制电平时，第一电流回路的电流I2和第二电流回路的电流I4之比为m:1；一旦电压端Vcp的电压大于参考电压Vref时，判断输出模块输出第二控制电平，第二控制电平与第一控制电平相同的相位，延迟时间Tdelay为第一控制电平的启动点和第二控制电平的启动点之间的时间差。因此，本发明通过增加电流镜模块，减小了实际对电容C0的充电电流，从而增大延时Tdelay，且使形成电路的芯片面积比传统电路芯片面积小很多。
A delay circuit includes a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the first current loop of the current mirror module is from a voltage terminal Vcp to a voltage terminal Vss, and the second current loop of the current mirror module is from a voltage terminal Vcn to a voltage terminal Vss; when the input voltage IN of the input and initialization module is a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1; once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judgment output module outputs a second control level, the second control level has the same phase as the first control level, and the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level. Therefore, the present invention reduces the actual charging current of the capacitor C0 by adding a current mirror module, thereby increasing the delay Tdelay, and makes the chip area of the circuit much smaller than the chip area of the traditional circuit.
Description
Technical Field
The invention belongs to the technical field of circuit design, and relates to a delay circuit.
Background
The delay circuit is a circuit which can realize that the enabling function can be output after a period of time is passed after the enabling signal is input, the motor is started or closed immediately by pressing the switch at ordinary times, but the delay circuit can be started or closed again after a period of time (time can be adjusted). For example, the voice-controlled LED lamp is turned off after a certain period of time has elapsed after the voice-controlled lamp is turned on, in order to provide convenience for passers-by to walk later.
In the design of integrated circuits, in order to design a larger delay and guarantee precision, the same current source is used, and most of current sources are used for charging a capacitor C0 to a certain threshold value to make a delay circuit of signals. Referring to fig. 1, fig. 1 is a functional block diagram of a prior art delay circuit, which includes a current source, an input module, a capacitor C0, and a comparator, as shown in fig. 1. The capacitor C0 and the input module are connected in parallel between the positive input end Vc and the voltage end Vss of the comparator, the negative input end of the comparator is connected with the reference voltage Vref, and the current source is connected between the voltage end Vcc and the voltage end Vc. Once the input module inputs the on-off control signal IN, the voltage difference on the capacitor C0 is changed from 0V IN the initial state to Vref, and the change value is Vref, and at this time, the comparator outputs the on-off control signal, i.e. the control signal is delayed by the time Tdelay.
Referring to fig. 2, fig. 2 is a schematic waveform diagram of each node of the delay circuit in fig. 1. As shown IN fig. 2, when the input voltage IN is inputted to a high level, the voltage terminal Vc starts to increase from 0, and when its voltage value increases to the reference voltage Vref, the comparator outputs a high level after the delay time Tdelay.
Assuming that the current source is I0 and the reference voltage Vref is typically fixed in the circuit, then there are:
I0*Tdelay=C0*Vref
However, many application circuits require a relatively large delay time Tdelay, and after selecting a suitable current source I0, a large capacitor C0 is required to obtain a relatively ideal state from the above formula, but a larger layout area is required to increase the volume of the capacitor C0 in the integrated circuit design, which means more cost.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a delay circuit, which has the following technical scheme:
the delay circuit comprises a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input end of the judging output module and one input end of the current mirror module, the positive input end of the judging output module is connected with the voltage end Vcp, the other input end of the current mirror module is connected with the voltage end Vcn, the negative input end of the judging output module is connected with the reference voltage Vref, the current source is connected between the voltage end Vcc and the voltage end Vcp, one end of the input and initialization module is connected with the voltage end Vss, the input end of the input and initialization module is connected with the input end IN, the first output end of the input and initialization module is connected with the voltage end Vcp, the second output end of the input and initialization module is connected with the voltage end Vcn, the first current loop of the current mirror module is connected with the voltage end Vcn from the voltage end Vcp to the voltage end Vss, when the input voltage IN of the input and initialization module is at a first control level, the current I2 of the first current loop and the current I4 of the second current loop is at a ratio of m & lt1 & gt, and when the input voltage IN of the input and the initialization module is at a first control level, the voltage I and the second current loop of the current loop is at a second control level of the voltage end Vss is greater than the reference level, and the second control level of the input voltage of the input and the current of the current mirror module reaches a second control level of the first control level is at the second control level, and the first delay time is equal to the first delay time and the control level of the first delay time is reached.
Further, the current mirror module comprises a first N-type transistor NFET1 and a second N-type transistor NFET2, wherein the ratio of the channel width-to-length ratio of the first N-type transistor NFET1 to the channel width-to-length ratio of the second N-type transistor NFET2 is 1:m, the grid electrodes of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected to a voltage end Vcn, the source electrodes of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected to a voltage end Vss, the drain electrode of the first N-type transistor NFET1 is connected to a voltage end Vcn, and the drain electrode of the second N-type transistor NFET2 is connected to a voltage end Vcp.
Further, the delay time is tdelay= (m+1) c0×0 (Vref-Vth)/I1, where Vth is the on threshold of NFET1, i.e. the last voltage of the voltage terminal Vcn.
Further, the current source includes a current mirror and a bias current module, the current mirror includes a first P-type transistor PFET1 and a second P-type transistor PFET2, and the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module are configured to form a current constant current source for charging the voltage terminal Vcp connected to the capacitor C0.
Further, the input and initialization module comprises an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4, wherein the inverter INV is connected between an input end IN and gates of the third N-type transistor NFET3 and the fourth N-type transistor NFET4, a drain electrode of the third N-type transistor NFET3 is connected with a voltage end Vcn, a drain electrode of the fourth N-type transistor NFET4 is connected with a voltage end Vcp, and a source electrode of the third N-type transistor NFET3 and a source electrode of the fourth N-type transistor NFET4 are connected with a voltage end Vss.
Further, the judging output module is a comparison module.
According to the technical scheme, in the embodiment of the delay circuit, when the larger delay time Tdelay is designed, the purpose of reducing the capacitance value of the capacitor C0 can be achieved under the same current source condition. If vcc=5v, vss=0v, vref=2.5v, vth=0.7v, and m=8, the capacitance value in the circuit of the present invention is only about 15.4% of the capacitance value in the conventional circuit. That is, in circuit layout (layout), the capacitor C0 occupies a main area, so the chip area of the circuit formed by the present invention is much smaller than that of the conventional circuit, and thus the manufacturing cost is much lower than that of the conventional circuit.
Drawings
FIG. 1 is a functional block diagram of a prior art delay circuit
FIG. 2 is a schematic waveform diagram of each node of the delay circuit of FIG. 1
FIG. 3 is a functional block diagram of a delay circuit according to an embodiment of the invention
FIG. 4 is a schematic diagram of a preferred embodiment of a delay circuit according to an embodiment of the invention
Detailed Description
The following describes embodiments of the present invention in further detail with reference to fig. 3-4.
Referring to fig. 3, fig. 3 is a functional block diagram of a delay circuit according to an embodiment of the invention. As shown in fig. 3, the delay circuit includes a current source, an input and initialization module, a capacitor C0, a current mirror module, and a judgment output module.
The capacitor C0 is connected between a positive input end of the judging output module and an input end of the current mirror module, the positive input end of the judging output module is connected with a voltage end Vcp, the other input end of the current mirror module is connected with a connection point between the voltage end Vcn and the positive input end of the judging output module, the negative input end of the judging output module is connected with a reference voltage Vref, the current source is connected between the voltage end Vcc and the voltage end Vcp, one end of the input and initialization module is connected with a voltage end Vss, the input end of the input and initialization module is connected with an IN, the first output end of the input and initialization module is connected with the voltage end Vcp, the second output end of the input and initialization module is connected with a voltage end Vcn, the first current loop of the current mirror module is connected with the voltage end Vcp to the voltage end Vss, the second current loop of the current mirror module is connected with the voltage end Vcn to the voltage end Vss, and when the input voltage IN of the input and initialization module is at a first control level, and the current I2 of the first current loop and the current I4 of the first current loop is 1 to the second current loop I4.
Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judging output module outputs a second control level, and when the second control level reaches the first control level to be the same, the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level.
That is, the delay circuit reduces the actual charging current and increases the delay time Tdelay through the current mirror module, so that the delay circuit can increase the delay time Tdelay under the condition of not increasing the capacitance value of the capacitor C0 and keeping the current constant current source.
Referring to fig. 4, fig. 4 is a schematic diagram of a delay circuit according to a preferred embodiment of the invention. In the embodiment of the present invention, the judging output module is a comparing module and may be a comparator. The supply voltage Vcc of the current source and the comparator may be, for example, 5 volts.
Specifically, the capacitor C0 is connected between the positive input end of the judging output module and one input end of the current mirror module, and as can be seen from the circuit diagram, the positive input end of the judging output module is connected with the voltage end Vcp, the other input end of the current mirror module is connected with the voltage end Vcn, and the negative input end of the judging output module is connected with the reference voltage Vref.
The first initialization loop of the input and initialization module is connected from the voltage terminal Vcp to the voltage terminal Vss.
The first current loop of the current mirror module is from the voltage terminal Vcp to the voltage terminal Vss, the input terminal IN of the input and initialization module, the second initialization loop of the input and initialization module is from the voltage terminal Vcn to the voltage terminal Vss, and the second current loop of the current mirror module is from the voltage terminal Vcn to the voltage terminal Vss.
In an embodiment of the invention, the current mirror module may comprise a first N-type transistor NFET1 and a second N-type transistor NFET2, wherein the ratio of the channel width-length ratio of the first N-type transistor NFET1 to the channel width-length ratio of the second N-type transistor NFET2 is 1:m, the gates of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected to a voltage terminal Vcn, the sources of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected to a voltage terminal Vss, the drain of the first N-type transistor NFET1 is connected to a voltage terminal Vcn, and the drain of the second N-type transistor NFET2 is connected to a voltage terminal Vcp.
When the input voltage IN of the input and initialization module is at a first control level, the ratio of the current I2 of the first current loop to the current I4 of the second current loop is m:1. Once the voltage of the voltage terminal Vcp is greater than the reference voltage Vref, the judging output module outputs a second control level, and when the second control level reaches the first control level to be the same, the delay time Tdelay is the time difference between the start point of the first control level and the start point of the second control level.
Typically, the delay time is Tdelay= (m+1) C0 (Vref-Vth)/I1
Where Vth is the on threshold of the first N-type transistor NFET1, i.e., the last voltage of the voltage terminal Vcn. That is, the delay time Tdelay is determined by m, the capacitance of the capacitor C0, vth, and the reference voltage. The larger m is, the larger the delay time Tdelay is, if the capacitance value, vth, and reference voltage of the capacitor C0 are unchanged.
The current source may include a current mirror including a first P-type transistor PFET1 and a second P-type transistor PFET2, and a bias current module to form a current constant source to charge the Vcp terminal of the capacitor C0.
The input and initialization module comprises an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4, wherein the inverter INV is connected between an input end IN and gates of the third N-type transistor NFET3 and the fourth N-type transistor NFET4, a drain electrode of the third N-type transistor NFET3 is connected with a voltage end Vcn, a drain electrode of the fourth N-type transistor NFET4 is connected with a voltage end Vcp, and source electrodes of the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are connected with a voltage end Vss.
In the embodiment of the present invention, for convenience of description, it may be assumed that vss=0v, and the above parameters may be set to the reference voltage vref=2.5v, vth=0.7v, m=8, and so on.
When the delay circuit is IN an operation initialization state, the input voltage in=0v of the input and initialization module, the inverter INV outputs a high level, the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are turned on, vcn=vcp=0v, and the U1 of the comparator outputs out=0v, and at this time, the delay circuit is IN an initial state and is IN a standby state.
When the delay circuit starts to work, the input voltage IN of the input and initialization module becomes Vcc, the inverter INV outputs a low level, the third N-type transistor NFET3 and the fourth N-type transistor NFET4 are turned off, at the moment, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module form a current constant source to charge a voltage end Vcp of the capacitor C0, at the moment, the first N-type transistor NFET1 and the second N-type transistor NFET2 form a current mirror pair to work, the NFET2 carries out I2 discharge on a Vcp end, and at the moment, the following steps are:
I1-I2 the number of times of the number =i 3, the number of the components is 3, i3=i4= I1/(m+1)
Also because tdelay=cv/I, tdelay= (m+1) c0 (Vref-Vth)/I1
Wherein Vref-Vth is the voltage drop variation across capacitor C0, and Vth is the on-threshold of NFET1, the last Vcn voltage.
When Vcp > Vref, the U1 output of the comparator block is high, i.e., output out=vcc. That is, the delay time Tdelay is a rising edge time from when the input voltage IN becomes high to when the output OUT becomes high. When the input voltage IN goes low, i.e. the entire circuit is again from the reentry initial state.
In summary, by adding the current mirror module, the invention reduces the actual charging current to the capacitor C0, thereby increasing the delay Tdelay, that is, the same current source can achieve the purpose of reducing the capacitance value of the capacitor C0, and the chip area of the formed circuit is much smaller than that of the traditional circuit, so that the manufacturing cost is much lower than that of the traditional circuit.
The foregoing description is only of the preferred embodiments of the present invention, and the embodiments are not intended to limit the scope of the invention, so that all changes made in the equivalent structures of the present invention described in the specification and the drawings are included in the scope of the invention.
Claims (4)
1. The delay circuit is characterized by comprising a current source, an input and initialization module, a capacitor C0, a current mirror module and a judgment output module; the capacitor C0 is connected between the positive input end of the judging output module and one input end of the current mirror module, the positive input end of the judging output module is connected with the voltage end Vcp, the other input end of the current mirror module is connected with the voltage end Vcn, the negative input end of the judging output module is connected with the reference voltage Vref, the current source is connected between the voltage end Vcc and the voltage end Vcp, one end of the input and initialization module is connected with the voltage end Vss, the input end of the input and initialization module is connected with the input end IN, the first output end of the input and initialization module is connected with the voltage end Vcp, the second output end of the input and initialization module is connected with the voltage end Vcn, the first current loop of the current mirror module is connected with the voltage end Vcp from the voltage end Vcn to the voltage end Vss, and the second current loop of the current mirror module is connected with the voltage end Vcn from the voltage end V.P, when the input voltage IN of the input and initialization module is at a first control level, the current I2 of the first current loop and the current I4 of the second current loop is 1:1, and when the input voltage IN of the input and initialization module is at a first control level, and the voltage I of the second current loop reaches a second control level of the voltage level of the second control point is greater than the reference level, and the first control level of the voltage of the first control point is at the same time;
The current mirror module comprises a first N-type transistor NFET1 and a second N-type transistor NFET2, wherein the channel width-to-length ratio of the first N-type transistor NFET1 and the channel width-to-length ratio of the second N-type transistor NFET2 are 1:m, the grid electrodes of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected with a voltage end Vcn, the source electrodes of the first N-type transistor NFET1 and the second N-type transistor NFET2 are commonly connected with a voltage end Vss, the drain electrode of the first N-type transistor NFET1 is connected with a voltage end Vcn, and the drain electrode of the second N-type transistor NFET2 is connected with a voltage end Vcp;
the judging output module is a comparison module.
2. The delay circuit of claim 1, wherein the delay time is:
Tdelay=(m+1)C0*(Vref-Vth)/I1
Where Vth is the on threshold of NFET1, the last voltage of voltage terminal Vcn.
3. The delay circuit of claim 1 wherein the current source comprises a current mirror and a bias current module, the current mirror comprising a first P-type transistor PFET1 and a second P-type transistor PFET2, the first P-type transistor PFET1, the second P-type transistor PFET2 and the bias current module being configured to form a current constant current source for charging the voltage terminal Vcp to which the capacitor C0 is connected.
4. The delay circuit of claim 1 wherein said input and initialization module comprises an inverter INV, a third N-type transistor NFET3 and a fourth N-type transistor NFET4, said inverter INV being connected between an input terminal IN and the gates of said third N-type transistor NFET3 and fourth N-type transistor NFET4, the drain of said third N-type transistor NFET3 being connected to a voltage terminal Vcn, the drain of said fourth N-type transistor NFET4 being connected to a voltage terminal Vcp, the sources of said third N-type transistor NFET3 and said fourth N-type transistor NFET4 being connected to a voltage terminal Vss.
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| CN107332541B (en) * | 2017-06-20 | 2019-09-24 | 西北工业大学 | The RC relaxor that comparator imbalance is offset |
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