CN2038669U - Mos element with double-grid - Google Patents

Abstract

The utility model discloses an MOS element with double-grid comprising two oxides grid zones with different thickness and respectively separated metallic layer grids, and a source electrode and a drain electrode can keep single. The thick-grid grid-voltage-channel conductance linear characteristic of the MOS element with double-grid can be adjusted the thin-grid grid-voltage, so the MOS element with double-grid can satisfy the application demand of voltage-conductance linear transform in extensive range.

Description

The utility model relates to a structure of a metal-oxide-semiconductor (MOS) device. It particularly relates to a metal-oxide-semiconductor device structure with two oxide gate regions with different thicknesses.

Existing metal-oxide-semiconductor devices have only a single uniform oxide layer gate region and a single metal layer gate. Once the device is manufactured, the linear characteristics of gate voltage to channel conductance are fixed and cannot be adjusted. This situation is not suitable for some application requirements, especially for the application requirements of realizing the voltage-conductance conversion function in a wide range.

In order to overcome the above-mentioned defects of the prior art, the utility model sets two oxide gate regions with different thicknesses in the same metal-oxide-semiconductor device, and sets metal layer gates respectively on the two gate regions, and The source region and the drain region on both sides of the double-gate MOS structure are connected, and a single source and drain are maintained. Thus, the channel conductance formed between the source and drain is the parallel conductance of the semiconductor surface channel under the two gate regions, which makes one of the gate voltage-channel conductance linear characteristics adjustable by the other gate voltage. Figure 1 shows the gate voltage-channel conductance characteristic curve of the existing MOS device, where the ordinate G is the channel conductance, and the abscissa V _g is the gate voltage. The V _g -G characteristic curve of each MOS device is unique and cannot adjust. Fig. 2 is the gate voltage-channel conductance characteristic curve of the double-gate MOS device of the present invention, wherein the ordinate G is still the channel conductance, and the abscissa V _g1 is the gate voltage of the thick gate, and the V _g1 -G characteristic curve at this moment can be obtained by Another adjustment of the thin gate voltage V _g2 , especially when the characteristic curve of V _g1 ~G needs to pass through the origin in applications, this kind of double-gate MOS device can always be realized by adjusting V _g2 .

The double-gate MOS device of the utility model can be realized no matter whether the structure of the P channel or the structure of the N channel is used. Fig. 3 shows the schematic diagram of the structure of a P-channel double-gate MOS device according to an embodiment of the present invention, wherein 1 is an n-type Si substrate, 2 is a thin gate oxide layer, 3 is a thin gate metal layer gate, and 4 is a thick Gate oxide layer, 5 is the thick metal layer gate, 6 is the P ⁺ source region, 7 is the metal layer source, 8 is the P ⁺ drain region, and 9 is the metal layer drain. In this embodiment, the thick gate oxide layer (4) is controlled within the range of 0.5 to 2.5 microns, and the thin gate oxide layer (2) is controlled within the range of 0.05 to 0.15 microns. The linear conversion of high voltage to channel conductance can make the characteristic curve of thick grid voltage to channel conductance pass through the origin by adjusting the DC low voltage applied to such a thin grid. Such a dual-gate MOS device has four terminals, as shown in FIG. 4 , there are thick-gate terminal g ₁ , thin-gate terminal g ₂ , source terminal S, and drain terminal D.

In some application fields, such as in electric power measurement, it is often necessary to perform linear transformation from voltage to conductance in a relatively wide range of values, and the dual-gate MOS device of the utility model is an extremely simple and effective means to realize such functions .

Description of drawings

Fig. 1 is a gate voltage-channel conductance characteristic curve of an existing MOS device, wherein the abscissa V _g is the gate voltage, and the ordinate G is the channel conductance.

Fig. 2 is the family of characteristic curves from thick gate voltage to channel conductance of the dual-gate MOS device of the present invention, wherein the abscissa V _g1 is the thick gate voltage, and the ordinate G is the channel conductance, and each V _g1 to G characteristic The curve corresponds to a thin grid voltage value V _g2 .

Figure 3 is a schematic diagram of the structure of a P-channel double-gate MOS device according to an embodiment of the present invention, wherein 1 is an n-type Si substrate, 2 is a thin gate oxide layer, 3 is a thin gate metal layer gate, and 4 is a thick gate oxide layer, 5 is the thick gate metal layer gate, 6 is the P ⁺ source region, 7 is the metal layer source, 8 is the P ⁺ drain region, and 9 is the metal layer drain.

Figure 4 is a schematic diagram of the external terminals of the dual-gate MOS device of the present invention, wherein _g1 is the terminal of the thick gate, _g2 is the terminal of the thin gate, S is the terminal of the source, and D is the terminal of the drain.

Claims (2)

1. A metal-oxide-semiconductor device, characterized in that it has two oxide gate regions with different thicknesses, and metal layer gates are respectively arranged on the two gate regions, and the gates on both sides of the two gate regions Both the source and the drain are connected to each other as a single source and drain. 2. The metal-oxide-semiconductor device according to claim 1 is characterized in that, among the two oxide gate regions with different thicknesses, the oxide thickness of the thick gate region is within the range of 0.5 to 2.5 microns, and the thickness of the oxide gate region of the thin gate region is The oxide thickness is in the range of 0.05 to 0.15 microns.

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