CN203179865U - Quad flat no-lead package unit and lead frame - Google Patents

Abstract

The utility model relates to a flat no pin's in four directions encapsulation unit includes a chip, a chip bearing, a plurality of pins and a encapsulation colloid. Wherein the chip bearing has one and accepts the face, accepts the face and can supply the usefulness that the chip set up, and the terminal outer fringe of each pin has an opening to the ring locates the chip bearing and just electric connection respectively in the chip, and the encapsulation colloid forms in chip, chip bearing and each pin with the mode of mould pressing, and the opening of each pin exposes in the outside of encapsulation colloid, therefore, the utility model discloses the open structure of pin not only can provide more and climb tin region in order to promote welding quality and yield, more can reduce the required cost of production preparation and do benefit to the detection behind the soldering tin. The utility model also provides a lead frame that is used for the flat no pin encapsulation of four directions.

Description

Quad flat no-lead package unit and lead frame

technical field

The utility model relates to a packaging unit; in particular, it refers to a quad flat non-lead (QFN) packaging unit, which can provide more soldering areas to improve soldering quality and yield, and can Reduce the cost required for production and facilitate the inspection after soldering.

Background technique

In the packaging industry of integrated circuits, bare chips are completed in advance through the steps of wafer manufacturing, circuit design, mask making, and wafer dicing. The bonding pad is electrically connected to the packaging substrate, and then the bare chip is covered with a molding compound to form a chip package structure. The purpose of packaging is to prevent the bare chip from being affected by the external environment and contamination by dust, and to improve the medium of electrical connection between the bare chip and the external circuit.

Please refer to Fig. 1 and shown in Fig. 2, it is the package unit of a kind of existing quadrilateral flat leadless, and this package unit 1 comprises a chip 2, a chip holder 3, a plurality of pins 4, a plurality of lead wires 5 and a packaging colloid 6 . The chip is arranged on the top of the chip holder, and each pin 4 is arranged around the chip holder, and the chip can be electrically connected to each pin through a wire bonding process, and finally the chip, the chip holder and each The pins are covered and protected. In addition, the lower surface of the pins of the existing quadrilateral flat no-lead package unit is not covered by the encapsulant, and the edges of the pins are aligned with the four sides of the encapsulant, so as to serve as the contact of the encapsulation unit to the outside. .

However, the pins of this package unit are aligned with the four sides of the packaging compound. Therefore, during the SMD assembly process, the solder is located on the bottom surface of the package unit, which makes it difficult to detect the packaged chip after the SMD assembly process. The tin area is only on the lower surface area of each pin, so that the soldering quality of the package unit is limited by the insufficient soldering area and cannot be improved.

In view of this, as shown in Figure 3 and Figure 4, LEADFRAME WITH PLATED END LEADS of US Patent No. US6,608,366 proposes an improvement plan for the above-mentioned problems. The structure of the packaging unit 1' is roughly the same as that of the existing ones. This patent uses a half-etching process to form a recess 7 on the lower surface of each pin 4', and the structure of the recess increases the solder 9 and the solder creeping area of each lead to improve the reliability of solder joints.

However, although the above-mentioned patent case can increase the tin-climbing area through the structure of the concave part, because of its structure, the solder is still located on the bottom surface of the packaging unit, so the problem of difficult detection after the SMD upper part manufacturing process of the packaged chip cannot be overcome. Because the concave portion of the lead of this patent is completed by a half-etching process, compared with the existing quad flat no-lead package unit, the complexity of production will undoubtedly be increased, and the cost will also be relatively increased.

In summary, the existing structures have the above-mentioned deficiencies and need to be improved.

Utility model content

The main purpose of the utility model is to provide a quadrilateral flat leadless package unit and a lead frame for a quadrilateral flat leadless package, which can provide more solder-climbing areas to improve soldering quality and yield, and can also Reduce the cost required for production and facilitate the inspection after soldering.

In order to achieve the above object, the utility model provides a square flat leadless packaging unit, which includes a chip, a chip holder, a plurality of pins and a packaging colloid, wherein the chip holder has a receiving surface, and the receiving surface It can be used for chip setting; each pin is arranged around the chip holder and is electrically connected to the chip respectively, and the outer edge of each pin end has an opening; and the encapsulant is formed on the chip, On the chip seat and each lead, and the opening of each lead is exposed on the outside of the encapsulation compound.

Wherein, the opening of the pin is a through hole, and is formed by stamping.

Wherein, the opening of the pin is arc-shaped.

Wherein, the packaging colloid is formed by single molding.

Wherein, each of the pins is electrically connected to the chip by wire bonding.

In order to achieve the above purpose, the utility model provides a lead frame for square flat no-lead packaging, including: a chip; a chip socket with a receiving surface, the receiving surface is used for setting the chip; A plurality of pins are arranged around the chip holder and are respectively electrically connected to the chip, and each of the pins has an opening at the end outer edge; a plurality of dicing lines are respectively provided at the opening of each of the pins; and An encapsulation compound is formed on the chip, the chip seat and each lead by molding, and the opening of each lead is exposed on the outside of the encapsulation compound.

Wherein, the opening of the pin is a through hole, and is formed by stamping.

Wherein, the lead frames are arranged in multiple groups.

Wherein, the encapsulation compound is formed on each of the encapsulation units by single molding.

Wherein, each of the pins is electrically connected to the chip by wire bonding.

Beneficial effects of the utility model: the utility model utilizes the opening structure of the pins and single molding to form the encapsulating colloid, which not only provides more soldering areas to improve the welding quality and yield, but also reduces the cost required for production And it is beneficial to the detection after soldering.

In order to further understand the structure, features and purpose of the present utility model, some embodiments of the present utility model are cited below, and are described in detail in conjunction with the drawings, and at the same time, those who are familiar with the technical field can implement it in detail, but the following , is only an embodiment provided to illustrate the technical content and characteristics of the present utility model, and those who have general knowledge in the field of the present utility model, after understanding the technical content and characteristics of the present utility model, do not violate the present utility model Under the spirit of the new model, all kinds of simple modification, replacement or reduction of components should belong to the intended protection category of the utility model.

Description of drawings

The technical contents and features of the present utility model will be described in detail below through the enumerated embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic cross-sectional view of a conventional quad flat no-lead package unit.

FIG. 2 is a bottom view of a conventional quad flat no-lead package unit.

FIG. 3 is a perspective view of a conventional quad flat no-lead package unit.

FIG. 4 is a schematic partial cross-sectional view of an existing quadflat no-lead package unit, mainly showing the solder-climbing area of the leads.

Fig. 5 is a schematic cross-sectional view provided by the first preferred embodiment of the present invention.

Fig. 6 is a top view provided by the preferred embodiment of the present invention.

FIG. 7 is a partial cross-sectional schematic diagram provided by the preferred embodiment of the present invention, mainly showing the tin-climbing area of the pins.

FIG. 8 is a schematic cross-sectional view provided by the preferred embodiment of the present invention, which mainly shows the arrangement of quadrilateral flat no-lead package units in multiple groups.

FIG. 9 is a top view provided by the preferred embodiment of the present invention, mainly showing the relative positions of the cutting line, the lead frame and the pins.

【Symbol Description】

10 package units

20 chips

30 chip holder 32 receiving surface

40 pins 42 openings

50 Encapsulation colloid

60 lead frame

70 cutting lane

1 package unit 1’ package unit

2 chips

3 chip socket

4 pins 4’ pins

5 leads

6 Encapsulation Colloid 6’ Encapsulation Colloid

7 concave

8 Substrate

9 Solder

L1 Climbing tin height L2 Climbing tin height

D Pin Thickness

Detailed ways

Please refer to Fig. 5 to Fig. 7, which is the first preferred embodiment of the present utility model, a square flat package unit 10 without leads, including a chip 20, a chip holder 30, and a plurality of pins 40 and an encapsulation compound 50 .

The chip holder 30 has a receiving surface 32 , and the receiving surface 32 can be used for disposing the chip 20 .

Each of the pins 40 is arranged on the chip holder 30 and is electrically connected to the chip 20 by wire bonding. The outer edge of each of the pins 40 has an opening 42, wherein the opening 42 is An arc-shaped through hole is formed by stamping, thereby increasing the soldering and soldering area of each pin, and reducing the cost of production; and

The encapsulant 50 is formed on the chip 20 , the chip holder 30 and each of the leads 40 by single molding, and the opening 42 of each of the leads 40 is exposed on the outside of the encapsulant 50 .

Therefore, as shown in Fig. 4 and Fig. 7, compared with the existing quadrilateral flat no-lead package unit in the SMD upper part manufacturing process of the present utility model, the solder 9 and the tin-climbing area of each pin 40 are removed from each pin 40. In addition to the lower surface of the pin 40, it also includes the opening 42 area of each pin 40 at the outer edge of the end. In other words, the solder 9 will climb to the side of each pin 40 due to the siphon phenomenon during the above-mentioned SMD upper part manufacturing process. , and fill each of the openings 42, thereby improving soldering quality and yield; and if under the same conditions of the thickness D of the pins 4' and 40, because the existing quadrilateral flat no-lead package unit 1' is in The concave part 7 of the pin 4' is arranged flush on the inner side of the encapsulant 6', so the concave part 4' cannot be a through hole, and the pin 4' can provide the height L1 of the solder 9 to climb the tin (the concave part 7 The distance from the top edge to the substrate 8) can only be roughly half of the thickness D of the pin 4', and the area where the solder 9 climbs tin is located under the pin 4'; compared with the structure of the utility model, the lead The pin 40 extends out of the outer edge of the encapsulant 50, so the concave portion 42 of the pin 40 can form a through hole. Correspondingly, the height L2 of the concave portion 42 for the solder 9 to climb tin is the height of the pin 40. Thickness D, so compared with the existing package unit 1 ′, the present invention can provide more soldering areas to improve soldering quality and yield.

In addition, the pins 40 of the packaging unit 10 of the present invention and the openings 42 of the pins 40 are exposed on the outside of the packaging colloid 50, so the quality of the solder 9 can be determined in the detection after the SMD upper part manufacturing process. It can be identified through simple optical instruments, without the need to use expensive X-Ray or destructive tests such as Micro-section and Red Dye Penetration Test, which is not only beneficial to soldering Post-9 detection can also reduce its required cost.

Please refer to Fig. 8 and Fig. 9 again, which is a lead frame 60 for square flat no-lead package of the present invention, wherein each lead frame 60 is arranged in multiple groups, and each package unit 10 contains There are the chip 20 , the chip holder 30 , each of the leads 40 , a plurality of dicing lines 70 and the encapsulant 50 . The chip holder 30 has a receiving surface 32, and the receiving surface 32 can be used for setting the chip 20; each of the pins 40 is arranged on the chip holder 30 and is electrically connected by wire bonding. On the chip 20, an opening 42 is formed at the end outer edge of each lead 40; each dicing line 70 is respectively arranged at the opening 42 of each lead 40; and the encapsulation compound 50 is formed by single molding On the chip 20 , the chip holder 30 and each of the leads 40 , and the openings 42 of each of the leads 40 are exposed outside the packaging compound 50 .

To describe in detail, the lead frames 60 arranged in multiple groups form a through hole 42 at the relative connection of each of the pins 40 and on each of the dicing lines 70 by punching, and then the chips 20 are adhered to the corresponding chips. On the socket 30, the chip 20 is electrically connected to each of the pins 40 by a wire-bonding process. Afterwards, in order to avoid dust and moisture in the external environment from affecting the performance of the chip 20, a single molded Form the encapsulant 50 on the chip 20, the chip holder 30 and the lead frame 60 one by one, and finally form a single square flat leadless lead-free chip by cutting or stamping along each of the dicing lines 70. Packaging unit 10. In other words, compared with the existing multi-group molding method, the single-chip molding method of the present invention can better meet the needs of different packages. For example, a set of multi-group molding molds can only be used for one arrangement of packages structure, if there are multiple arrangements of packaging structures, multiple sets of molds must be opened to meet the demand at this time; in contrast, the utility model is not only suitable for various multi-group arrangements, but also because of the formation of single molded The encapsulation compound 50 is less complex in encapsulation, and the manufacturing cost is relatively lower.

In summary, the quadrilateral flat leadless package unit of the present invention has the following advantages:

With the opening 42 structure at the outer edge of the end of each pin 40 , more areas of solder creeping can be provided to improve soldering quality and yield.

The openings 42 of the pins 40 are exposed on the outside of the encapsulant 50 , and this structure facilitates the inspection after soldering 9 .

The opening 42 is formed by punching, and the encapsulant 50 is formed on the multi-group lead frame 60 by single-piece molding, which can reduce the cost required for production and meet the needs of different multi-group arrangements. packaging requirements.

The components disclosed in the above-disclosed embodiments of the present invention are only for illustration and are not intended to limit the scope of the present application. The replacement or change of other equivalent components should also be covered by the scope of the patent application of the present application.

Claims (10)

1. the encapsulation unit of a square flat non-pin is characterized in that including:

One chip;

One chip bearing has a continuing surface, and this continuing surface is for the usefulness of this chip setting;

A plurality of pins are located on this chip bearing and are electrically connected at this chip respectively, and respectively the terminal outer rim of this pin has an opening; And

One packing colloid is formed at this chip, this chip bearing and respectively on this pin with press moulding mode, and respectively the opening of this pin is exposed to the outside of this packing colloid.

2. according to the encapsulation unit of the square flat non-pin of claim 1, it is characterized in that the opening of this pin is a perforation, and formed with impact style.

3. according to the encapsulation unit of the square flat non-pin of claim 2, it is characterized in that the opening of this pin is circular-arc.

4. according to the encapsulation unit of the square flat non-pin of claim 1, it is characterized in that this packing colloid is formed with single press moulding mode.

5. according to the encapsulation unit of the square flat non-pin of claim 1, it is characterized in that respectively this pin is to be electrically connected on this chip in the routing mode.

6. a lead frame that is used for the square flat non-pin encapsulation is characterized in that, includes:

One chip;

One chip bearing has a continuing surface, and this continuing surface is for the usefulness of this chip setting;

A plurality of pins are located on this chip bearing and are electrically connected at this chip respectively, and respectively the terminal outer rim of this pin has an opening;

A plurality of Cutting Roads are located at the respectively opening part of this pin respectively; And

One packing colloid, with press moulding mode be formed at this chip, this chip bearing and respectively this pin on, and respectively the opening of this pin is exposed to the outside of this packing colloid.

7. according to the lead frame that is used for the square flat non-pin encapsulation of claim 6, it is characterized in that the opening of this pin is a perforation, and formed with impact style.

8. according to the lead frame that is used for the square flat non-pin encapsulation of claim 6, it is characterized in that respectively this lead frame is the arrangement of many group shapes.

9. the lead frame that is used for the square flat non-pin encapsulation according to Claim 8 is characterized in that this packing colloid is to be formed at respectively this encapsulation unit with single press moulding mode.

10. according to the lead frame that is used for the square flat non-pin encapsulation of claim 6, it is characterized in that respectively this pin is to be electrically connected on this chip in the routing mode.

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