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CN203179011U - Reconfigurable high-speed memory chip module and electronic system device - Google Patents

Reconfigurable high-speed memory chip module and electronic system device Download PDF

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Publication number
CN203179011U
CN203179011U CN2012205770786U CN201220577078U CN203179011U CN 203179011 U CN203179011 U CN 203179011U CN 2012205770786 U CN2012205770786 U CN 2012205770786U CN 201220577078 U CN201220577078 U CN 201220577078U CN 203179011 U CN203179011 U CN 203179011U
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memory cell
integrated circuit
chip module
programmable
cell arrays
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甘万达
卢超群
宋建迈
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Etron Technology Inc
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Etron Technology Inc
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model discloses a but high-speed memory chip module and electronic system device of reconfiguration. The high-speed memory chip module comprises a type of memory cell array, a first transmission bus and a logic unit. The memory cell array of this type includes a plurality of memory cell array integrated circuits; the first transmission bus is coupled to the memory cell array of the type, and has a first programmable transmit or receive data rate, a first programmable transmit or receive data signal amplitude, and part or all of a first programmable bus width; the logic unit is coupled to the first transmission bus and used for accessing the memory cell array of the type through the first transmission bus. Therefore, the utility model discloses power consumptive less and have higher transmission efficiency, lower cost, higher efficiency, electromagnetic interference's shielding effect, the heat-sinking capability of preferred and keep apart the function of external noise.

Description

But the high speed storing chip module of reconfiguration and electronic system device
Technical field
The utility model relates to a kind of high speed storing chip module and has the electronic system device of high speed storing chip module, refer to that especially a kind of power consumption is less, have higher transfer efficiency, have electromagnetic interference (EMI) shield effectiveness, have preferable radiating effect and have the high speed storing chip module of the function of isolating outside noise and have the electronic system device of high speed storing chip module.
Background technology
In general, storer usually can be based on particular industry standard (jedec (Joint Electronic Device Engineering Council, JEDEC)) and be designed to be independent of the standard memory of logical block for example.That is based on the particular industry standard, storer is the standard memory that is designed to be applicable to various Different Logic unit, rather than is designed to be applicable to specific logical unit.These common standards (for example known highway width of industry, signal amplitude and operating frequency etc.) have determined memory bus width, given signal amplitude and given transmit data rate, make memory module have lower manufacturability, lower elasticity, and different process technique from generation to generation with different application in higher moving costs.
In the prior art, the manufacture of semiconductor of storer is from generation to generation different with the manufacture of semiconductor of logical block usually from generation to generation, that is integrate than sophisticated semiconductor processing procedure storage chip module from generation to generation may run into that heat radiation is difficult for, higher power dissipation and noise, so prior art is in the difficulty that still faces on the storage chip module in many manufacturings.
The utility model content
But an embodiment of the present utility model provides a kind of high speed storing chip module of reconfiguration.This high speed storing chip module comprises a kind of memory cell arrays, one first transfer bus and logical block of pattern.The memory cell arrays of this kind pattern comprises a plurality of memory cell arrays integrated circuit; This first transfer bus is the memory cell arrays that is coupled to this kind pattern, has one first programmable transmission or rate of received data, one first programmable transmission or receives data signal amplitude; This logical block is to be coupled to this first transfer bus, in order to the memory cell arrays by this this kind of first transfer bus access pattern.
Another embodiment of the present utility model provides a kind of electronic system device with high speed storing chip module.This electronic system device comprises memory cell arrays, one first transfer bus and a logical block of an integrated circuit processor, a kind of pattern.The memory cell arrays of this kind pattern comprises a plurality of memory cell arrays integrated circuit; First transfer bus is the memory cell arrays that is coupled to this kind pattern, has the one first programmable transmission relevant with the included firmware of this integrated circuit processor or a software or rate of received data, one first programmable transmission or receives data signal amplitude; This logical block is to be coupled to this first transfer bus, in order to the memory cell arrays by this this kind of first transfer bus access pattern.
The utility model provides a kind of high speed storing chip module and has the electronic system device of high speed storing chip module.This high speed storing chip module and this electronic system device have following advantage: first, because one first transfer bus has one first programmable transmission or rate of received data, one first programmable transmission or reception data signal amplitude, one first programmable highway width, the part of one first programmable data width and one first programmable position width or whole, and one second transfer bus have one second programmable transmission or rate of received data, one second programmable transmission or reception data signal amplitude, one second programmable highway width, the part of one second programmable data width and one second programmable position width or whole, so the utility model is when operation, power consumption is less, has higher transfer efficiency, be applicable to various integrated circuit processor (or chip system processor), have lower cost and have higher usefulness; The second, because the utility model can utilize a plurality of direct silicon wafer perforation formation one wire netting in the non-active circuits district of a plurality of direct silicon wafer perforation in the non-active circuits district of each memory cell arrays or a logical block, so the utlity model has the shield effectiveness of preferable electromagnetic interference (EMI), the function that has preferable heat-sinking capability and have the isolation outside noise of the electromagnetics principle of using always based on today.Therefore, compared to prior art, the utility model power consumption is less, have higher transfer efficiency, be applicable to various integrated circuit processor (or chip system processor), have lower cost, have higher usefulness, have electromagnetic interference (EMI) shield effectiveness, have preferable heat-sinking capability and have the function of isolating outside noise, and can be used in the portable electric system device that comprises various application integrated circuit processor (or various chip system processor), logical block or storage chip module.
Description of drawings
Fig. 1 is the synoptic diagram that a kind of high speed storing chip module is described for an embodiment of the present utility model.
Fig. 2 is the cross section synoptic diagram for explanation high speed storing chip module.
Fig. 3 is the cross section synoptic diagram that the high speed storing chip module is described for another embodiment of the present utility model.
Fig. 4 is the cross section synoptic diagram that the high speed storing chip module is described for another embodiment of the present utility model.
Fig. 5 is the cross section synoptic diagram that the high speed storing chip module is described for another embodiment of the present utility model.
Fig. 6 is the cross section synoptic diagram that the high speed storing chip module is described for another embodiment of the present utility model.
Fig. 7 is the synoptic diagram for corresponding second sealing ring with logical block of corresponding first sealing ring of each memory cell arrays integrated circuit in explanation memory cell arrays integrated circuit and the memory cell arrays integrated circuit.
Fig. 8 is the exploded perspective view that has a plurality of direct silicon wafer perforation for first sealing ring of each the memory cell arrays integrated circuit in explanation memory cell arrays integrated circuit and the memory cell arrays integrated circuit outward.
Fig. 9 be for be for explanation when the high speed storing chip module be during for the 3D framework, the high speed storing chip module also comprises the exploded perspective view of metal level and insulation course.
Figure 10 is the square section synoptic diagram for the heat dissipation path of the high speed storing chip module of key diagram 9.
Figure 11 is the square section synoptic diagram that the heat dissipation path of high speed storing chip module is described for another embodiment of the present utility model.
Figure 12 be for explanation in the manufacture process of the assembling of the high speed storing chip module of Fig. 8 or encapsulation, the edge of memory cell arrays integrated circuit occur slight crack on look synoptic diagram.
Figure 13 has the electronic system schematic representation of apparatus of high speed storing chip module for another embodiment explanation of the present utility model.
Figure 14 is for having the exploded perspective view of a plurality of direct silicon wafers perforation in the non-active circuits district that the active circuits district that centers on or partly center on each the memory cell arrays integrated circuit in memory cell arrays integrated circuit and the memory cell arrays integrated circuit in another embodiment of the present utility model is described.
Figure 15 illustrates one jiao of memory cell arrays integrated circuit or the logical block synoptic diagram with calibration or direction identification sign for another embodiment of the present utility model.
Figure 16 illustrates one jiao of memory cell arrays integrated circuit or the logical block synoptic diagram with calibration or direction identification sign for another embodiment of the present utility model.
Wherein, description of reference numerals is as follows:
100,900 high speed storing chip modules
101 memory cell arrays
102,104 memory cell arrays integrated circuit
106 logical blocks
108 first transfer bus
110 second transfer bus
112 integrated circuit processors
114 substrates
116,118,119,120 intermediary layers
121,123 wire nettings
122 metal levels
124 insulation courses
128 motherboards
105,130,132,134,136 direct silicon wafer perforation
103 Flip Chips
107 routing technology
126 first sealing rings
129 second sealing rings
125 heat dissipation path
127 heat radiator
133 slight cracks
137 active circuits districts
139 non-active circuits districts
140 driving components
The line of 141 laser graphic
The line of 142 2 laser graphic
The direction identification of 143 lasers cutting indicates
144 calibrations or direction identification indicate
The direction identification of 145 holes indicates
200 encapsulation
1022,1042 I/O data buss
1062 parallel commentaries on classics serialization controllers
1200 electronic system devices
Embodiment
Please refer to Fig. 1, Fig. 1 is the synoptic diagram that a kind of high speed storing chip module 100 is described for an embodiment of the present utility model.High speed storing chip module 100 comprises a kind of memory cell arrays 101 of pattern, one first transfer bus 108 and a logical block 106, wherein memory cell arrays 101 comprises it being to be dynamic RAM (Dynamic Random Access Memory, DRAM) a memory cell arrays integrated circuit 102 of integrated circuit, and be to be flash memory (flash) integrated circuit or nonvolatile memory (non-volatile memory, NVM) integrated circuit (phase change random access memory devices (Phase Change RAM for example, PCRAM), resistive random access memory (resistive random access memories, RRAM), the electronics formula of erasing can be made carbon copies ROM (read-only memory) (Electrically-Erasable Programmable Read-Only Memory, EEPROM), but the planning type ROM (read-only memory) of can erasing (Erasable Programmable Read Only Memory, EPROM) or a memory cell arrays integrated circuit 104 of magnetoresistive random access memory (Magnetoresistive Random Access Memory, MRAM) etc.).But the utility model is not limited to the memory cell arrays 101 that high speed storing chip module 100 comprises a kind of pattern, it comprises memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104, and also not to be subject to memory cell arrays integrated circuit 102 be for dynamic RAM integrated circuit and memory cell arrays integrated circuit 104 are to be quick flash storage integrated circuit or nonvolatile memory integrated circuit, that is memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 also can be the memory integrated circuit of other pattern.In addition, each the memory cell arrays integrated circuit in the memory cell arrays integrated circuit 102,104 has an I/O data bus and at least one memory cell arrays.For example memory cell arrays integrated circuit 102 has an I/O data bus 1022, and have 2 memory cell arrays, and memory cell arrays integrated circuit 104 has an I/O data bus 1042, and have 2 memory cell arrays, wherein I/O data bus 1022 and I/O data bus 1042 have the ability of the wired or wireless transmission of the logical block of being accompanied by 106 changes.Memory cell arrays integrated circuit 102 has 2 memory cell arrays and memory cell arrays integrated circuit 104 has 2 memory cell arrays but the utility model is not limited to.
As shown in Figure 1, first transfer bus 108 is to be coupled to memory cell arrays 101, and it has one first programmable transmission or rate of received data, one first programmable transmission or receives the part of data signal amplitude, one first programmable highway width, one first programmable data width and one first programmable position width or whole.In addition, but the programmable functions of first transfer bus 108 relates to one-time programming (one-time programming, OTP), can repeatedly programme (multi-time programming, MTP), a flash memory (Flash Memory), an in-line memory (embedded memory), an anti-fuse (anti-fuse), a buffer, an included firmware or a software or an included firmware or the software of a memory chip module of an electronic system device.In addition, the utility model can utilize polysilicon fuse (poly fuse), metal fuse (metal fuse), anti-fuse or electrical fuse (e-fuse) to realize the one-time programming of first transfer bus 108 or the function that can repeatedly programme.In an embodiment of the present utility model, the first programmable transmission of first transfer bus 108 or rate of received data can be corresponding to a haploidy number according to speed (single data rate, SDR), a pair of haplotype data speed (Double Data Rate, DDR), a quad data rate (Quadruple Data Rate) or similar data speed.In another embodiment of the present utility model, the first programmable transmission of first transfer bus 108 or rate of received data can be linked to maximum operating frequency and the minimum operation frequency relevant for first transfer bus 108 provided by the utility model.In another embodiment of the present utility model, the first programmable transmission of first transfer bus 108 or reception data signal amplitude can be corresponding to one low-voltag transistor/transistor logic (Low Voltage Transistor – transistor logic, LVTTL) amplitude, one complementary metal oxide semiconductor (CMOS) low-voltag transistor/transistor logic (complementary metal oxide semiconductor LVTTL, CMOS LVTTL) amplitude, one Low Voltage Differential Signal (Low-voltage differential signal, LVDS) amplitude, one high-speed transceiver logic (High-speed transceiver logic, HSTL) amplitude, one series connection termination logic (stub series terminated logic, SSTL) amplitude or similarly amplitude.Therefore, electronic system device (comprising integrated circuit processor 112 and high speed storing chip module 100) and high speed storing chip module 100 can be according to first default values or relevant for other value of the utility model program capability, adjust the first programmable transmission of first transfer bus 108 or receive data signal amplitude, so, first transfer bus 108 can reach higher usefulness, lower operation power consumption, lower stand-by power consumption, the battery life of growing or the enhancement of other function.
Logical block 106 is in order to pass through one first transfer bus, 108 access memory cell array integrated circuit 102 and memory cell arrays integrated circuit 104, wherein first transfer bus 108 is in order to transmitting one first group of panel data, and the highway width of first transfer bus 108 (for example 128 or 256 or more multidigit) is the highway width (for example 8 or 16 or more multidigit) greater than I/O data bus 1022 and I/O data bus 1042; When logical block 106 is arranged first group of panel data of accesses by first transfer bus 108, logical block 106 utilizes its included first group of panel data of parallel commentaries on classics serialization controller 1062 conversions to become one second group of panel data, and one second transfer bus 110 that the I/O data bus by high speed storing chip module 100 is also comprised (for example 32 serial or and column bus) transfers to an Application Specific Integrated Circuit (Application-specific Integrated Circuit, ASIC) processor 112 (or a chip system processor), wherein second transfer bus 110 has one second programmable transmission or rate of received data, one second programmable transmission or reception data signal amplitude, one second programmable highway width, the part of one second programmable data width and one second programmable position width or whole, and second transfer bus 110 be to can be 2.0 editions (USB2.0) buses of a universal serial bus, 3.0 editions (USB3.0) buses of one universal serial bus, one serial high-order technology attachment device (Serial Advanced Technology Attachment, SATA) bus, one general flash memory stores (Universal Flash Storage, UFS) bus, movable property industry processor interface (the mobile industry processor interface of delegation, MIPI) bus or a high-speed peripheral device interconnecting interface (Peripheral Component Interconnect Express, PCIE) bus.
In an embodiment of the present utility model, second transfer bus 110 is to can be one can transmit haploidy number according to the also column bus of speed, Double Data Rate, quad data rate or similar data speed.In addition, but the programmable functions of second transfer bus 110 relates to one-time programming, can repeatedly programme, a flash memory, an in-line memory, an anti-fuse, a buffer, included firmware or software or included firmware or the software of memory chip module of electronic system device.In addition, the utility model can utilize polysilicon fuse, metal fuse, anti-fuse or electrical fuse to realize the one-time programming of second transfer bus 110 or the function that can repeatedly programme.In an embodiment of the present utility model, the second programmable transmission of second transfer bus 110 or rate of received data can be corresponding to haploidy number according to speed, Double Data Rate, quad data rate or similar data speed.In another embodiment of the present utility model, the second programmable transmission of second transfer bus 110 or rate of received data can be linked to maximum operating frequency and the minimum operation frequency relevant for second transfer bus 110 provided by the utility model.In another embodiment of the present utility model, the second programmable transmission of second transfer bus 110 or reception data signal amplitude can be corresponding to low-voltag transistor/transistor logic amplitude, complementary metal oxide semiconductor (CMOS) low-voltag transistor/transistor logic amplitude, Low Voltage Differential Signal amplitude, high-speed transceiver logic amplitude, series connection termination logic amplitude or similar amplitudes.Therefore, electronic system device (comprising integrated circuit processor 112 and high speed storing chip module 100) and high speed storing chip module 100 can be according to second default values or relevant for other value of the utility model program capability, adjust the second programmable transmission of second transfer bus 110 or receive data signal amplitude, so, second transfer bus 110 can reach higher usefulness, lower operation power consumption, lower stand-by power consumption, the battery life of growing or the enhancement of other function.Then, integrated circuit processor 112 can be carried out a predetermined function according to second group of panel data.As shown in Figure 1, logical block 106 is to be designed as one " parallel commentaries on classics universal serial bus " bridge, it receives first group of panel data by first transfer bus 108 (for example 128 buses or 256 buses) with wideer highway width, and utilizes first group of panel data of its included parallel commentaries on classics serialization controller 1062 conversions to become second group of parallel data.In addition, second transfer bus 110 and first transfer bus 108 also can be wireless first transfer bus, to optimize between power and overall efficiency.For example second transfer bus 110 and first transfer bus 108 are to can be transmission ray or electromagnetic bus.In an embodiment of the present utility model, if the bit width of first transfer bus 108 is during greater than second transfer bus 110, the power efficiency of high speed storing chip module 100 can be higher.ㄧ aspect in addition, in another embodiment of the present utility model, if the bit width of second transfer bus 110 is during greater than first transfer bus 108, the accurate position of the transmission frequency range of high speed storing chip module 100 and noise can be optimized with the applied environment in response to high speed storing chip module 100.In addition, because first transfer bus 108 has the first programmable transmission or rate of received data, the first programmable transmission or receives data signal amplitude, the first programmable highway width, the first programmable data width with the part of the first programmable position width or all, and second transfer bus 110 has the second programmable transmission or rate of received data, the second programmable transmission or receives the part of data signal amplitude, the second programmable highway width, the second programmable data width and the second programmable position width or whole.So, high speed storing chip module 100 can be saved the power consumption of self and the usefulness of optimization self.Therefore, high speed storing chip module 100 has higher manufacturability, higher elasticity, and different process technique from generation to generation with different application in lower moving costs.
In addition, first programmable transmission or the rate of received data that first transfer bus 108 has, the first programmable transmission or reception data signal amplitude, the first programmable highway width, the first programmable data width and the first programmable position width have first default value, and second programmable transmission or the rate of received data that have of second transfer bus 110, the second programmable transmission or reception data signal amplitude, the second programmable highway width, the second programmable data width and the second programmable position width have second default value.Therefore, when integrated circuit processor 112 (or chip system processor) connects high speed storing chip module 100 by second transfer bus 110, integrated circuit processor 112 (or chip system processor) can utilize the usefulness of first default value and the second default value optimization, first transfer bus 108 and second transfer bus 110, and does not need further programming.If that is when actual demand is arranged, but first default value and second default value can be by at least one one-time programming storer, repeatedly included firmware or software modification or the renewals of programmable memory, a flash memory, an in-line memory, a buffer or integrated circuit processor 112.So, because high speed storing chip module 100 can be according to different application environment and condition, first default value is carried out corresponding change with second default value, so high speed storing chip module 100 is not only applicable to various integrated circuit processor (or chip system processor), also can reduce the cost of high speed storing chip module 100 and the usefulness that improves high speed storing chip module 100, and need not bear the inventory cost of the different configuration of memory chip module.In addition, the frequency of operation of first transfer bus 108 and second transfer bus 110 and operating voltage also can dynamically change to improve the usefulness of high speed storing chip module 100 with integrated circuit processor 112.
In an embodiment of the present utility model, memory cell arrays 101, first transfer bus 108, logical block 106, second transfer bus 110 and a plurality of integrated circuit processor (or a plurality of chip system processor) are packaged together; In another embodiment of the present utility model, memory cell arrays 101 and first transfer bus 108 are packaged together, and second transfer bus 110 and logical block 106 are packaged together; In another embodiment of the present utility model, memory cell arrays 101, first transfer bus 108, second transfer bus 110, logical block 106 and integrated circuit processor 112 are packaged together, and that is to say that high speed storing chip module 100 can wrap in single encapsulation together with integrated circuit processor 112.
Please refer to Fig. 2, Fig. 2 is the cross section synoptic diagram for explanation high speed storing chip module 100.As shown in Figure 2, memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and logical block 106 are to utilize Flip Chip (Flip-Chip) 103 mutual storehouses (as shown in Figure 2, memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 are that storehouse is on logical block 106), wherein Flip Chip 103 is with memory cell arrays integrated circuit 102, the liner of memory cell arrays integrated circuit 104 and logical block 106 (pad) is gone up and is formed projection (bump), will utilize projection to make memory cell arrays integrated circuit 102 then, memory cell arrays integrated circuit 104 and logical block 106 mutual storehouses.
Please refer to Fig. 3, Fig. 3 is the cross section synoptic diagram that high speed storing chip module 100 is described for another embodiment of the present utility model.As shown in Figure 3, memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and logical block 106 are to utilize routing technology (wire bonding) 107 to be connected with a substrate 114, and wherein memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 are that storehouse is on logical block 106.In another embodiment of the present utility model, logical block 106 comprises that a direct silicon wafer perforation 105 is to connect memory cell arrays integrated circuit 102, and utilize the routing technology to connect another integrated circuit, wherein another integrated circuit has an analog functuion, one digital signal processing function (digital signal processing, DSP), one communication function, one Wireless Fidelity (wireless fidelity, Wi-Fi) function, one power management (power management) function, one digital analog mixed (mix-mode) function, one less radio-frequency function or a MEMS (micro electro mechanical system) (micro electro mechanical systems, MEMS) function.
Please refer to Fig. 4, Fig. 4 is the cross section synoptic diagram that high speed storing chip module 100 is described for another embodiment of the present utility model.As shown in Figure 4, high speed storing chip module 100 also comprises an intermediary layer (interposer) 116, and wherein intermediary layer 116 is to can be silicon materials or monoxide glass (oxide glass) material.But it is to can be silicon materials or oxide glass material that the utility model is not limited to intermediary layer 116.As shown in Figure 4, memory cell arrays integrated circuit 102 be storehouse on memory cell arrays integrated circuit 104, and memory cell arrays integrated circuit 104 is to be arranged at separately on relative two limits of intermediary layer 116 with logical block 106.In addition, can utilize between memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and the logical block 106 routing technology, Flip Chip, directly silicon wafer perforation (Through Silicon Via, TSV) or wireless transmission connect.
Please refer to Fig. 5, Fig. 5 is the cross section synoptic diagram that high speed storing chip module 100 is described for another embodiment of the present utility model.As shown in Figure 5, high speed storing chip module 100 also comprises intermediary layer 118,120.As shown in Figure 5, memory cell arrays integrated circuit 102 is that storehouse is on intermediary layer 118, intermediary layer 118 is that storehouse is on memory cell arrays integrated circuit 104, memory cell arrays integrated circuit 104 be storehouse on intermediary layer 120, and intermediary layer 120 is that storehouse is on logical block 106.In addition, can utilize between memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and the logical block 106 routing technology, Flip Chip, directly silicon wafer perforation or wireless transmission are connected.
Please refer to Fig. 6, Fig. 6 is the cross section synoptic diagram that high speed storing chip module 100 is described for another embodiment of the present utility model.As shown in Figure 6, high speed storing chip module 100 also comprises an intermediary layer 119.As shown in Figure 6, memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 be storehouse on intermediary layer 119, intermediary layer 119 be storehouse on logical block 106, and logical block 106 is that storehouse is on substrate 114.In addition, can utilize routing technology, Flip Chip, direct silicon wafer perforation or wireless transmission to be connected to each other between memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and the logical block 106, or utilize routing technology, Flip Chip, direct silicon wafer perforation or wireless transmission to connect the 3rd integrated circuit with an analog functuion, a digital signal processing function, a communication function, a Wireless Fidelity function, a power management function, a digital analog mixed function, a less radio-frequency function or a MEMS (micro electro mechanical system) function.
In addition, the encapsulation 200 of the high speed storing chip module 100 of Fig. 2 to Fig. 6 be can be encapsulation (Package-in-Package), a stacking encapsulation (Package on package) or a system in package in the encapsulation (System in Package, SIP).In addition, the high speed storing chip module 100 of Fig. 2, Fig. 3, Fig. 5 and Fig. 6 is to be the 3D framework, and the high speed storing chip module 100 of Fig. 4 is to be the 2.5D framework.In addition, in Fig. 2, logical block 106 also can utilize routing technology, Flip Chip, direct silicon wafer perforation or wireless transmission to connect a substrate or a motherboard.
In addition, the data signal amplitude identical (for example 1.8V) that the data signal amplitude that transmits by first transfer bus 108 (that is voltage difference of the logical zero that transmits of first transfer bus 108 and logical one) and first transfer bus 108 receive, wherein the data signal amplitude that receives of the data signal amplitude that transmits of first transfer bus 108 and first transfer bus 108 can change with memory cell arrays integrated circuit 102,104 memory standards.In addition, for purpose of power saving, logical block 106 can be adjusted the data signal amplitude (for example 1.8V) that inputs to logical block 106 from first transfer bus 108 becomes other or the lower data signal amplitude (for example 1.2V) that exports second transfer bus 110 from logical block 106 to.In addition, when high speed storing chip module 100 whenever necessary, the data signal amplitude that the data signal amplitude that transmits by second transfer bus 110 and second transfer bus 110 receive also can identical (for example 1.2V).
In addition, because memory cell arrays integrated circuit 102,104 manufacture of semiconductor may be different with the manufacture of semiconductor of logical block 106 and integrated circuit processor 112 (or chip system processor) (for example the memory cell arrays integrated circuit 102,104 manufacture of semiconductor is to be the 0.13um-90nm manufacture of semiconductor, the manufacture of semiconductor of logical block 106 is to be the 28nm-20nm manufacture of semiconductor, and integrated circuit processor 112 (or chip system processor) is to be the 28nm-13nm manufacture of semiconductor), so memory cell arrays integrated circuit 102, the gate length of the mos field effect transistor of 104 the manufacture of semiconductor gate length than the mos field effect transistor of the manufacture of semiconductor of logical block 106 and integrated circuit processor 112 (or chip system processor) usually is long.So, in another embodiment of the present utility model, the data signal amplitude that the data signal amplitude that transmits by first transfer bus 108 and first transfer bus 108 receive can be different, and the data signal amplitude that the data signal amplitude that transmits by second transfer bus 110 and second transfer bus 110 receive also can be different.
In addition, in another embodiment of the present utility model, the data signal amplitude that the data signal amplitude that transmits by first transfer bus 108 and first transfer bus 108 receive can be different, and the data signal amplitude that the data signal amplitude that transmits by second transfer bus 110 and second transfer bus 110 receive can be identical.
In addition, in another embodiment of the present utility model, the data signal amplitude that the data signal amplitude that transmits by first transfer bus 108 and first transfer bus 108 receive can be identical, and the data signal amplitude that the data signal amplitude that transmits by second transfer bus 110 and second transfer bus 110 receive can be different.
In addition, for power saving and the advantage of utilizing different manufacture of semiconductor, in another embodiment of the present utility model, the transmit data rate of first transfer bus 108 can be different with the rate of received data of first transfer bus 108, and the transmit data rate of second transfer bus 110 also can be different with the rate of received data of second transfer bus 110.In addition, in another embodiment of the present utility model, the rate of received data of the transmit data rate of first transfer bus 108 and first transfer bus 108 can be identical, and the rate of received data of the transmit data rate of second transfer bus 110 and second transfer bus 110 also can be identical.In addition, in another embodiment of the present utility model, the transmit data rate of first transfer bus 108 can be different with the rate of received data of first transfer bus 108, and the transmit data rate of second transfer bus 110 also can be different with the rate of received data of second transfer bus 110, and the data signal amplitude that the data signal amplitude that transmits by first transfer bus 108 and first transfer bus 108 receive can be different, and the data signal amplitude that the data signal amplitude that transmits by second transfer bus 110 and second transfer bus 110 receive also can be different.
In addition, as shown in Figure 1, the memory cell arrays of being made up of memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 101 can have multiple different memory sizes and highway width.For example, if the memory capacity of each memory cell arrays in memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 and highway width are to be 512M and 32, then the memory capacity of the memory cell arrays 101 formed of memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 and highway width are to can be 512M and 128, or can be 1G and 64.But it is to be 512M and 128 that the utility model is not limited to the memory capacity of the memory cell arrays 101 that memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 form and highway width, or is 1G and 64.In addition, if the memory capacity of memory cell arrays integrated circuit 102 and highway width are for the memory capacity of 512M and 64 and memory cell arrays integrated circuit 104 and highway width are to be 1G and 64, then the memory capacity of the memory cell arrays 101 formed of memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 and highway width are to can be 1.5G and 128.
Please refer to Fig. 7, Fig. 7 is the synoptic diagram of corresponding one first sealing ring (the seal ring) 126 of each the memory cell arrays integrated circuit in explanation memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 with logical block 106 corresponding one second sealing rings 129.As shown in Figure 7, circuit in each memory cell arrays integrated circuit in memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 is surrounded by one first sealing ring 126, and the circuit in the logical block 106 is surrounded by second sealing ring 129.
Please refer to Fig. 8, Fig. 8 is first sealing ring, the 126 outer exploded perspective views with a plurality of direct silicon wafer perforation for each the memory cell arrays integrated circuit in explanation memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104, and wherein a plurality of direct silicon wafer perforation are in order to connect a power supply or a ground end.But the utility model is not limited to first sealing ring of each memory cell arrays integrated circuit has a plurality of direct silicon wafer perforation outward, that is first sealing ring of each memory cell arrays integrated circuit has at least one direct silicon wafer perforation outward.As shown in Figure 8, the relative position of a plurality of direct silicon wafers perforation outside first sealing ring 126 of each memory cell arrays integrated circuit is all identical with quantity.Because the relative position that first sealing ring, the 126 outer a plurality of direct silicon wafers of each memory cell arrays integrated circuit are bored a hole is all identical with quantity, so when memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 storehouses together the time, can form a wire netting 121 (Fig. 8 only draws two limits of wire netting 121) by first sealing ring, the 126 outer a plurality of direct silicon wafer perforation of each memory cell arrays integrated circuit, wherein wire netting 121 is to center on memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 or part around one side of memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104, two limits or three limits.Wire netting 121 has electromagnetic interference (EMI) (electromagnetic interference, shield effectiveness EMI), the function that has preferable heat-sinking capability and have preferable isolation outside noise.In addition, because first sealing ring, the 126 outer a plurality of direct silicon wafer perforation of each memory cell arrays integrated circuit are in order to connect power supply or ground end, so can save in first sealing ring 126 of each memory cell arrays integrated circuit in order to connect the circuit area of power supply or ground end.
Please refer to Fig. 9, Fig. 9 be for be for explanation when high speed storing chip module 100 be during for the 3D framework, high speed storing chip module 100 also comprises the exploded perspective view of a metal level 122 and an insulation course 124.As shown in Figure 8, metal level 122 is arranged on the superiors' memory cell arrays in the memory cell arrays integrated circuit 102, and insulation course 124 is arranged between the superiors' memory cell arrays in metal level 122 and the memory cell arrays integrated circuit 102, and wherein metal level 122 can electrically connect by at least one direct silicon wafer perforation in the insulation course 124 and the superiors' memory cell arrays in the memory cell arrays integrated circuit 102.In addition, metal level 122 is to can be a single chip architecture or a fluting chip architecture (slotted piece).In addition, metal level 122 is the superiors' memory cell arrays areas more than 50% that cover in the memory cell arrays integrated circuit 102, and memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 are that storehouse is on logical block 106.In addition, metal level 122 can connect power supply or ground end by at least one direct silicon wafer perforation, to carry out the shield effectiveness of preferable electromagnetic interference (EMI).
Please refer to Figure 10, Figure 10 is the square section synoptic diagram for the heat dissipation path 125 of the high speed storing chip module 100 of key diagram 9.As shown in figure 10, high speed storing chip module 100 can utilize the outer a plurality of direct silicon wafer perforation of first sealing ring of memory cell arrays integrated circuit 102 upwards to dispel the heat to heat radiator 127 by metal level 122, or utilizes wire netting 121 by direct silicon wafer perforating radiating to a motherboard 128 (shown in the arrow of Figure 10) of logical block 106 and substrate 114.
Please refer to Figure 11, Figure 11 is the square section synoptic diagram that the heat dissipation path 125 of high speed storing chip module 900 is described for another embodiment of the present utility model, and wherein the difference of the high speed storing chip module 100 of high speed storing chip module 900 and Figure 10 is that the logical block 106 in the high speed storing chip module 900 is that storehouse is on memory cell arrays 101.The a plurality of direct silicon wafer perforation that first sealing ring of each the memory cell arrays integrated circuit in memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 is outer, and the outer a plurality of direct silicon wafer perforation of second sealing ring of logical block 106 is in order to connect power supply or ground end.But the utility model is not limited to second sealing ring of logical block 106 has a plurality of direct silicon wafer perforation outward, that is second sealing ring of logical block 106 has at least one direct silicon wafer perforation outward.As shown in figure 11, metal level 122 is arranged on the logical block 106, and insulation course 124 is arranged between metal level 122 and the logical block 106, wherein metal level 122 can electrically connect with logical block 106 by at least one direct silicon wafer perforation in the insulation course 124, and metal level 122 is covering logic unit areas more than 10650%.In addition, as shown in figure 11, high speed storing chip module 900 can utilize the outer a plurality of direct silicon wafer perforation of second sealing ring of logical block 106 upwards to dispel the heat to heat radiator 127 by metal level 122, or utilizes wire netting 121 to pass through the direct silicon wafer perforating radiating of substrate 114 to motherboard 128 (shown in the arrow of Figure 11).In addition, because the outer a plurality of direct silicon wafer perforation of second sealing ring of logical block 106 are in order to connect power supply or ground end, so can save in second sealing ring of logical block 106 in order to connect the circuit area of power supply or ground end.
Please refer to Figure 12, Figure 12 be for explanation in the manufacture process of the assembling of the high speed storing chip module 100 of Fig. 8 or encapsulation, the edge of memory cell arrays integrated circuit 102 occur slight crack 133 on look synoptic diagram.As shown in figure 12, when slight crack appears in the edge of memory cell arrays integrated circuit 102, slight crack will can not influence the function of memory cell arrays integrated circuit 102, but slight crack 133 can make and be connected direct silicon wafer perforation 130,132 short circuits together with power supply, and feasible the end with ground is connected direct silicon wafer perforation 134,136 short circuits together.So because directly silicon wafer perforation 130,132 short circuits together, and directly silicon wafer perforation 134,136 also short circuit together, so the shield effectiveness of the electromagnetic interference (EMI) of wire netting 121, heat-sinking capability and have the function of isolating outside noise and all can strengthen.In addition, because the shield effectiveness of the electromagnetic interference (EMI) of wire netting 121, heat-sinking capability and have the function of isolating outside noise and all can strengthen, so the slight crack 133 of Figure 12 will can not influence the function of memory cell arrays integrated circuit 102, but can improve the fine ratio of product of assembling or the encapsulation of high speed storing chip module 100.
On the other hand, the cutting mode of traditional diamond saw (diamond-saw) and can't memory cell arrays integrated circuit 102,104 be cut into other crystal grain not causing the crystal grain edge to have under the situation of slight crack.In another embodiment of the present utility model, the crystal grain edge that causes for the cutting mode that overcomes diamond saw has the shortcoming of slight crack, and the cutting mode of at least one memory cell arrays integrated circuit in the memory cell arrays integrated circuit 102,104 comprises the step of at least one laser cutting processing procedure.For example, before or after the cutting mode of traditional diamond saw, utilize the step process memory cell arrays integrated circuit 102,104 of laser cutting processing procedure, with the slight crack (that is to say that the crystal grain edge after the step process of laser cutting processing procedure can be more smooth) at the crystal grain edge that reduces memory cell arrays integrated circuit 102,104, and improve memory cell arrays integrated circuit 102,104 fine ratio of product.
Please refer to Figure 13, Figure 13 is the synoptic diagram that has the electronic system device 1200 of high speed storing chip module for another embodiment explanation of the present utility model.Electronic system device 1200 is to utilize the interior encapsulation of encapsulation, stacking encapsulation (Package on package) or system in package that integrated circuit processor (or chip system processor) 112, memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 are combined with logical block 106.Because all integrated circuit processor 112, memory cell arrays integrated circuit 102, the memory cell arrays integrated circuit 104 with Fig. 1 is identical with logical block 106 with logical block 106 for integrated circuit processor 112, memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104, so repeat no more its principle of operation.
Please refer to Figure 14, Figure 14 is for having the exploded perspective view of a plurality of direct silicon wafers perforation 105 in the non-active circuits district 139 that the active circuits district 137 that centers on or partly center on each the memory cell arrays integrated circuit in memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 in another embodiment of the present utility model is described, wherein non-active circuits district 139 is only constituted (insulator for example by passive component, as the metal wire (interconnect) that connects, resistance, electric capacity, inductance, engage diode (junction diode), metal-oxide-semiconductor diode (Metal-Oxide-Semi-conductor diode) and similar assembly), and active circuits district 137 is by in order to temporary, the driving component 140 (for example N-type mos field effect transistor (Metal-Oxide-Semi-conductor diode field-effect transistor) and the similar assembly of P-type mos field effect transistor) of switch and amplification application or similar functions.In an embodiment of the present utility model, the width in non-active circuits district 139 is less than 50 to 100um to save the chip area of each memory cell arrays integrated circuit, and wherein non-active circuits district 139 can improve the defective that memory cell arrays integrated circuit 102,104 cutting yield and cutting slight crack produce.In another embodiment of the present utility model, at least one direct silicon wafer perforation or a plurality of direct silicon wafer perforation have less than 10 to 20um width (or diameter) and the spacing with 10 to 30um, so can further reduce memory cell arrays integrated circuit 102,104 chip area and manufacturing cost.A plurality of direct silicon wafers perforation 105 in the non-active circuits district 139 of each memory cell arrays integrated circuit is in order to connecting a power supply or a ground end, and the active circuits district 137 of each memory cell arrays integrated circuit is in order at least one driving component 140 that forms each memory cell arrays integrated circuit (for example at least one transistor or mos field effect transistor are temporary to carry out, switch and amplification application or similar functions).The non-active circuits district 139 of each memory cell arrays integrated circuit also comprises in order to connecting at least one transistorized at least one metal level, and the non-active circuits district 139 of each memory cell arrays integrated circuit is to be less than or equal to 50um to 100um.But the utility model is not limited to have in the non-active circuits district 139 of each memory cell arrays integrated circuit a plurality of direct silicon wafers perforation, that is has at least one direct silicon wafer perforation in the non-active circuits district 139 of each memory cell arrays integrated circuit.In addition, because a plurality of direct silicon wafer perforation in the non-active circuits district of each memory cell arrays integrated circuit 139 is in order to connect power supply or ground end, so can in the active circuits district 137 of each memory cell arrays integrated circuit, save in order to connect the circuit area of power supply or ground end, with fine ratio of product and the manufacturing cost of improving each memory cell arrays integrated circuit.In addition, can utilize processing procedure behind (via middle) in (via first) before the hole, the hole or the hole to face upward or downward a plurality of direct silicon wafers perforation in the non-active circuits district 139 that forms each memory cell arrays integrated circuit.As shown in figure 14, when memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 storehouses together the time, can form and wire netting 121 similar wire nettings 123 (Figure 14 only draws two limits of wire netting 123) by a plurality of direct silicon wafers perforation in the non-active circuits district 139 of each memory cell arrays integrated circuit.Therefore, wire netting 123 also has electromagnetic interference (EMI) (electromagnetic interference, shield effectiveness EMI), the function that has preferable heat-sinking capability and have preferable isolation outside noise.In addition, around or part in the non-active circuits district in the active circuits district of logical block 106, also have a plurality of direct silicon wafers perforation, wherein a plurality of direct silicon wafer perforation in the non-active circuits district of logical block 106 is in order to connect power supply or ground end, the active circuits district of logical block 106 is that (for example at least one transistor or mos field effect transistor are temporary to carry out in order at least one driving component of forming logical block 106, switch and amplification are used or similar functions), the non-active circuits district of logical block 106 also comprises in order to connect at least one transistorized at least one metal level, and the non-active circuits district of logical block 106 is less than or equal to 50um to 100um, to save the chip area of volume unit 106.The same with memory cell arrays integrated circuit 104 with memory cell arrays integrated circuit 102, can utilize a plurality of direct silicon wafer that processing procedure faces upward or downward in the non-active circuits district that forms logical block 106 behind (via middle) in (via first) before the hole, the hole or the hole to bore a hole.In addition, direct silicon wafer perforation in a plurality of direct silicon wafer perforation in the non-active circuits district of logical block 106 is in order to connect one of memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104, and logical block 106 also comprises the routing liner (wire bonding pad) in order to connect another integrated circuit, and wherein another integrated circuit has an analog functuion, one digital signal processing function, one communication function, one Wireless Fidelity function, one power management function, one digital analog mixed function, one less radio-frequency function or a MEMS (micro electro mechanical system) function.In addition, a plurality of direct silicon wafer perforation in the non-active circuits district of logical block 106 is bored a hole with a plurality of direct silicon wafer in the non-active circuits district 139 of each memory cell arrays integrated circuit and is also had the function of Figure 10 and Figure 11, does not repeat them here.
In addition, in another embodiment of the present utility model, around or the non-active circuits district 139 in the active circuits district 137 of each the memory cell arrays integrated circuit of part in memory cell arrays integrated circuit 102 and the memory cell arrays integrated circuit 104 in have at least one pair of adjacent direct silicon wafer perforation and (just do not overlap or entity is not connected, wherein the spacing of a pair of adjacent direct silicon wafer perforation approximately less than 10 to 30um), and also have at least one pair of adjacent direct silicon wafer perforation in the non-active circuits district of logical block 106.Therefore, if in the assembling of high speed storing chip module 100 or the manufacture process of encapsulation, when slight crack appearred in the edge of memory cell arrays integrated circuit 102, the direct silicon wafer perforation of at least one pair of in the non-active circuits district 139 of memory cell arrays integrated circuit 102 also can show the slight crack abort function (cracking stop function) with similar Figure 12.So, the slight crack at the edge of memory cell arrays integrated circuit 102 will can not influence the function of memory cell arrays integrated circuit 102, but can improve the fine ratio of product of assembling or the encapsulation of high speed storing chip module 100.Therefore, the shield effectiveness of the electromagnetic interference (EMI) of wire netting 123, heat-sinking capability and have the function of isolating outside noise and also all can strengthen.
Please refer to Figure 15, Figure 15 illustrates memory cell arrays integrated circuit 102 for another embodiment of the present utility model, one jiao of synoptic diagram with a calibration (alignment) or direction identification sign (orientation identification mark) of memory cell arrays integrated circuit 104 or logical block 106, wherein direction identification indicates and is formed by the processing procedure that comprises a laser step, and it is to can be at memory cell arrays integrated circuit 102 that direction identification indicates, 104 or logical block 106 on a laser cut edge (edge cut), the line of one laser graphic (line of Laser drawing mark) 141, the line 142 of two laser graphic, at least one single hole, a plurality of holes,, a line, two-lines or by laser deposition, the formed arbitrary pattern of grooving or cutting step, wherein direction identification indicates and can pass through a conductive layer (bronze medal layer for example, one aluminium lamination or similar metal level) or form by non-conductive layer (a for example dielectric layer).In addition, in order to adjust processing procedure better, direction identification indicates and can be filled with, the material of part filling or not filling assembling or encapsulation (epoxy shaping mould material (Epoxy Molding Compound, EMC) or materials similar) for example.As shown in figure 15, the direction identification that the upper left corner of memory cell arrays integrated circuit 102 has laser cutting indicates 143, and wherein identifying the size that indicates in the direction of embodiment laser cutting of the present utility model is between between the 1um to 5um.Please refer to Figure 16, Figure 16 illustrates memory cell arrays integrated circuit 102 for another embodiment of the present utility model, one jiao of synoptic diagram with direction identification sign 145 of a calibration or direction identification sign 144 and one hole of memory cell arrays integrated circuit 104 or logical block 106, wherein direction identification sign is to utilize to comprise that the processing procedure of a direct silicon wafer perforation step is formed at memory cell arrays integrated circuit 102,104 or logical block 106 on, and direction identification to indicate be to can be single direct silicon wafer perforation, a plurality of direct silicon wafer perforation, one direct silicon wafer perforation indicates line (line of marks), two direct silicon wafer perforation indicate line or arbitrary by the formed direct silicon wafer hole pattern of the processing procedure that comprises direct silicon wafer perforation step.In addition, in order to calibrate processing procedure better, directly the silicon wafer perforation indicate can be filled with, the material (for example epoxy shaping mould material or materials similar) of part filling or not filling assembling or encapsulation.Above-mentioned calibration or direction identification indicate the effort of the storehouse memory cell arrays integrated circuit 102 of can releiving, the effort of slow storehouse logical block 106 and memory cell arrays integrated circuit 102 and storehouse memory cell arrays integrated circuit 104 of relaxing, or the slow storehouse logical block 106 of relaxing has the effort of the integrated circuit of an analog functuion, a digital signal processing function, a communication function, a Wireless Fidelity function, a power management function, a digital analog mixed function, a less radio-frequency function or a MEMS (micro electro mechanical system) function with another.
In addition, the upper left corner of memory cell arrays integrated circuit 104 also has the direction identification sign of identical laser cutting.Because memory cell arrays integrated circuit 102 indicates with the direction identification that memory cell arrays integrated circuit 104 has identical laser cutting, so when memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 storehouses together the time, the direction identification of laser cutting indicates can guarantee that memory cell arrays integrated circuit 102 and memory cell arrays integrated circuit 104 align mutually more accurately.In another embodiment of the present utility model, direction identification indicates the programmed screening test that can minimize after resurvey (re-test), the initial screening test (screening test) or in order to cost and the effort of the filler test of memory cell arrays integrated circuit 102 or logical block 106.Therefore, the direction identification of memory cell arrays integrated circuit 102, memory cell arrays integrated circuit 104 and logical block 106 indicates the back encapsulation assembling processing procedure (post package assembly process) that can be applicable to the detection that comprises visual detection, X-ray check or ultrasonic scanning microscope (C-SAM), does not repeat them here.
In sum, high speed storing chip module provided by the utility model and the electronic system device with high speed storing chip module have following advantage: the first, the utility model when operation, power consumption is less, have higher transfer efficiency, be applicable to various integrated circuit processor (or chip system processor), have lower cost and have higher usefulness; The second, because the utility model can utilize a plurality of direct silicon wafer perforation formation wire netting in the non-active circuits district of a plurality of direct silicon wafer perforation in the non-active circuits district of each memory cell arrays or logical block, so the utlity model has the shield effectiveness of preferable electromagnetic interference (EMI), the function that has preferable heat-sinking capability and have the isolation outside noise of the electromagnetics principle of using always based on today.Therefore, compared to prior art, the utility model power consumption is less, have higher transfer efficiency, be applicable to various integrated circuit processor (or chip system processor), have lower cost, have higher usefulness, have electromagnetic interference (EMI) shield effectiveness, have preferable heat-sinking capability, have the function of isolating outside noise, and can be used in the portable electric system device that comprises various application integrated circuit processor (or various chip system processor), logical block or storage chip module.
The above is preferred embodiment of the present utility model only, is not limited to the utility model, and for a person skilled in the art, the utility model can have various changes and variation.All within spirit of the present utility model and principle, any modification of doing, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.

Claims (23)

1.一种可重组态的高速存储芯片模块，包括：  1. A reconfigurable high-speed memory chip module, comprising: 一种型式的存储单元数组，其中该种型式的存储单元数组包括多个存储单元数组集成电路；  A type of memory cell array, wherein the type of memory cell array includes a plurality of memory cell array integrated circuits; 该高速存储芯片模块的特征在于还包括：  The high-speed memory chip module is characterized in that it also includes: 一第一传输总线，耦接于该种型式的存储单元数组，具有一第一可编程的传送或接收数据速率、一第一可编程的传送或接收数据信号振幅；及  A first transmission bus, coupled to this type of memory cell array, has a first programmable transmission or reception data rate, a first programmable transmission or reception data signal amplitude; and 一逻辑单元，耦接于该第一传输总线，用以通过该第一传输总线存取该种型式的存储单元数组。  A logic unit, coupled to the first transmission bus, is used for accessing the type of storage unit array through the first transmission bus. the 2.如权利要求1所述的高速存储芯片模块，其特征在于，该第一传输总线是用以传送伴随该多个存储单元数组集成电路的一第一组平行数据，且该第一传输总线的总线宽度是大于每一存储单元数组集成电路的输入/输出数据总线的总线宽度。  2. The high-speed memory chip module according to claim 1, wherein the first transmission bus is used to transmit a first set of parallel data accompanying the plurality of memory cell array integrated circuits, and the first transmission bus The bus width is greater than the bus width of the input/output data bus of each memory cell array integrated circuit. the 3.如权利要求1所述的高速存储芯片模块，其特征在于，还包括：  3. the high-speed memory chip module as claimed in claim 1, is characterized in that, also comprises: 一第二传输总线，耦接于该逻辑单元，具有一第二可编程的传送或接收数据速率、一第二可编程的传送或接收数据信号振幅，其中该逻辑单元另用以通过该第二传输总线转换该第一组平行数据成为一第二组平行资料。  A second transmission bus, coupled to the logic unit, has a second programmable transmit or receive data rate, a second programmable transmit or receive data signal amplitude, wherein the logic unit is also used to pass the second The transmission bus converts the first group of parallel data into a second group of parallel data. the 4.如权利要求3所述的高速存储芯片模块，其特征在于，该第二传输总线具有一第二可编程的数据宽度与一第二可编程的位置宽度，以及该第一传输总线具有一第一可编程的数据宽度与一第一可编程的位置宽度。  4. The high-speed memory chip module according to claim 3, wherein the second transmission bus has a second programmable data width and a second programmable location width, and the first transmission bus has a A first programmable data width and a first programmable location width. the 5.如权利要求4所述的高速存储芯片模块，其特征在于，该第一可编程的传送或接收数据速率、该第一可编程的传送或接收数据信号振幅、该第一可编程的数据宽度与该第一可编程的位置宽度具有第一默认值，且该 第二可编程的传送或接收数据速率、该第二可编程的传送或接收数据信号振幅、该第二可编程的数据宽度与该第二可编程的位置宽度具有第二默认值。  5. The high-speed memory chip module according to claim 4, characterized in that, the first programmable transmit or receive data rate, the first programmable transmit or receive data signal amplitude, the first programmable data The width and the first programmable position width have a first default value, and the second programmable transmit or receive data rate, the second programmable transmit or receive data signal amplitude, the second programmable data width and this second programmable position width has a second default value. the 6.如权利要求3所述的高速存储芯片模块，其特征在于，该第一传输总线和该第二传输总线的可编程功能是有关于可一次编程、可多次编程、一快闪存储器、一嵌入式存储器、一反保险丝、一缓存器、一韧体或一软件。  6. The high-speed memory chip module as claimed in claim 3, wherein the programmable functions of the first transfer bus and the second transfer bus are related to one-time programming, multiple programming, a flash memory, An embedded memory, an anti-fuse, a register, a firmware or a software. the 7.如权利要求1所述的高速存储芯片模块，其特征在于，围绕或部分围绕该多个存储单元数组集成电路中的每一个存储单元数组集成电路的主动电路区的非主动电路区内具有至少一直接硅晶穿孔，且该主动电路区是用以形成该存储单元数组集成电路的至少一主动组件。  7. The high-speed memory chip module according to claim 1, characterized in that, there are At least one direct TSV, and the active circuit area is used to form at least one active device of the memory cell array integrated circuit. the 8.如权利要求7所述的高速存储芯片模块，其特征在于，该至少一直接硅晶穿孔是用以连接一电源或一地端。  8. The high-speed memory chip module according to claim 7, wherein the at least one direct TSV is used to connect a power supply or a ground terminal. the 9.如权利要求7所述的高速存储芯片模块，其特征在于，该存储单元数组集成电路的一角具有一方向识别标示，其中该方向识别标示是由包括一雷射步骤的制程所形成。  9. The high-speed memory chip module according to claim 7, wherein a corner of the memory cell array integrated circuit has a direction identification mark, wherein the direction identification mark is formed by a process including a laser step. the 10.如权利要求7所述的高速存储芯片模块，其特征在于，该存储单元数组集成电路的一角具有一方向识别标示，其中该方向识别标示包括至少一切割边缘、一画线、一孔洞或任一样式。  10. The high-speed memory chip module according to claim 7, wherein a corner of the memory cell array integrated circuit has a direction identification mark, wherein the direction identification mark includes at least a cutting edge, a drawing line, a hole or Either style. the 11.如权利要求7所述的高速存储芯片模块，其特征在于，该存储单元数组集成电路的一角具有一识别标示，其中该识别标示是由包括一直接硅晶穿孔步骤的制程所形成。  11. The high-speed memory chip module as claimed in claim 7, wherein a corner of the memory cell array integrated circuit has an identification mark, wherein the identification mark is formed by a process including a direct TSV step. the 12.如权利要求1所述的高速存储芯片模块，其特征在于，围绕或部分围绕该逻辑单元的主动电路区的非主动电路区内具有至少一直接硅晶穿孔，且该主动电路区是用以形成该逻辑单元的至少一主动组件，其中该至少一直接硅晶穿孔是用以连接一电源或一地端。  12. The high-speed memory chip module according to claim 1, wherein at least one direct TSV is provided in the non-active circuit area surrounding or partially surrounding the active circuit area of the logic unit, and the active circuit area is used To form at least one active device of the logic unit, wherein the at least one direct TSV is used to connect a power supply or a ground terminal. the 13.如权利要求12所述的高速存储芯片模块，其特征在于，该逻辑单元包括一直接硅晶穿孔以连接该多个存储单元数组集成电路中的一存储单元数组集成电路，以及还包括一打线衬垫以连接另一集成电路，其中该另一集成电路具有一模拟功能、一数字信号处理功能、一通信功能、一无线保真功能、一电源管理功能、一数字模拟混合功能、一无线射频功能或一微机电系统功能。  13. The high-speed memory chip module as claimed in claim 12, wherein the logic unit comprises a direct through-silicon via to connect a memory cell array integrated circuit among the plurality of memory cell array integrated circuits, and further comprises a bonding pads to connect another integrated circuit, wherein the other integrated circuit has an analog function, a digital signal processing function, a communication function, a wireless fidelity function, a power management function, a digital-analog mixing function, a A radio frequency function or a MEMS function. the 14.如权利要求7或12所述的高速存储芯片模块，其特征在于，该非主动电路区的宽度小于50um。  14. The high-speed memory chip module according to claim 7 or 12, wherein the width of the non-active circuit area is less than 50um. the 15.如权利要求7或12所述的高速存储芯片模块，其特征在于，该至少一直接硅晶穿孔的宽度小于20um。  15. The high-speed memory chip module according to claim 7 or 12, wherein the width of the at least one direct TSV is less than 20 um. the 16.如权利要求1所述的高速存储芯片模块，其特征在于，围绕或部分围绕该多个存储单元数组集成电路中的每一个存储单元数组集成电路的主动电路区的非主动电路区内具有至少一对相邻的直接硅晶穿孔，且该至少一对直接硅晶穿孔是用以连接一电源或一地端。  16. The high-speed memory chip module according to claim 1, characterized in that there are At least one pair of adjacent TSVs are used for connecting a power supply or a ground terminal. the 17.如权利要求1所述的高速存储芯片模块，其特征在于，围绕或部分围绕该逻辑单元的主动电路区的非主动电路区内具有至少一对相邻的直接硅晶穿孔，且该至少一对直接硅晶穿孔是用以连接一电源或一地端。  17. The high-speed memory chip module according to claim 1, wherein there are at least one pair of adjacent direct TSVs in the non-active circuit area surrounding or partially surrounding the active circuit area of the logic unit, and the at least one A pair of TSVs are used to connect a power supply or a ground terminal. the 18.如权利要求1所述的高速存储芯片模块，其特征在于，该多个存储单元数组集成电路中的至少一存储单元数组集成电路的切割方式包括一雷射制程。  18. The high-speed memory chip module according to claim 1, wherein the cutting method of at least one memory cell array integrated circuit among the plurality of memory cell array integrated circuits includes a laser process. the 19.如权利要求1所述的高速存储芯片模块，其特征在于，该逻辑单元的切割方式包括一雷射制程。  19. The high-speed memory chip module as claimed in claim 1, wherein the cutting method of the logic unit comprises a laser process. the 20.一种具有高速存储芯片模块的电子系统装置，包括：  20. An electronic system device with a high-speed memory chip module, comprising: 一集成电路处理器；  an integrated circuit processor; 一种型式的存储单元数组，其中该种型式的存储单元数组包括多个存储单元数组集成电路；  A type of memory cell array, wherein the type of memory cell array includes a plurality of memory cell array integrated circuits; 该电子系统装置的特征在于还包括：  The electronic system device is characterized in that it also includes: 一第一传输总线，耦接于该种型式的存储单元数组，其中该第一传输总线具有与该集成电路处理器所包括的一韧体或一软件相关的一第一可编程的传送或接收数据速率、一第一可编程的传送或接收数据信号振幅；及  A first transmission bus, coupled to the memory cell array of this type, wherein the first transmission bus has a first programmable transmission or reception associated with a firmware or a software included in the integrated circuit processor data rate, a first programmable transmit or receive data signal amplitude; and 一逻辑单元，耦接于该第一传输总线，用以通过该第一传输总线存取该种型式的存储单元数组。  A logic unit, coupled to the first transmission bus, is used for accessing the type of storage unit array through the first transmission bus. the 21.如权利要求20所述的电子系统装置，其特征在于，还包括：  21. The electronic system device as claimed in claim 20, further comprising: 一第二传输总线，耦接于该逻辑单元和该集成电路处理器之间，具有与该韧体或该软件相关的一第二可编程的传送或接收数据速率、一第二可编程的传送或接收数据信号振幅。  A second transmission bus, coupled between the logic unit and the integrated circuit processor, has a second programmable transmit or receive data rate associated with the firmware or the software, a second programmable transmit Or receive data signal amplitude. the 22.如权利要求21所述的电子系统装置，其特征在于，该第二传输总线具有与该韧体或该软件相关的一第二可编程的数据宽度与一第二可编程的位置宽度，以及该第一传输总线具有与该韧体或该软件相关的一第一可编程的数据宽度与一第一可编程的位置宽度。  22. The electronic system device according to claim 21, wherein the second transmission bus has a second programmable data width and a second programmable location width related to the firmware or the software, And the first transmission bus has a first programmable data width and a first programmable location width related to the firmware or the software. the 23.如权利要求21所述的电子系统装置，其特征在于，该第一传输总线和该第一传输总线的可编程功能是有关于可一次编程、可多次编程、一快闪存储器、一嵌入式存储器、一反保险丝、一缓存器、该韧体或该软件。  23. The electronic system device as claimed in claim 21, wherein the first transmission bus and the programmable function of the first transmission bus are related to one-time programming, multiple programming, a flash memory, a Embedded memory, an anti-fuse, a register, the firmware or the software. the
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