CN201417298Y - test circuit board - Google Patents
test circuit board Download PDFInfo
- Publication number
- CN201417298Y CN201417298Y CN 200920150603 CN200920150603U CN201417298Y CN 201417298 Y CN201417298 Y CN 201417298Y CN 200920150603 CN200920150603 CN 200920150603 CN 200920150603 U CN200920150603 U CN 200920150603U CN 201417298 Y CN201417298 Y CN 201417298Y
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- Prior art keywords
- test
- tested
- circuit board
- testing circuit
- testing
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- 238000012360 testing method Methods 0.000 title claims abstract description 160
- 238000010586 diagram Methods 0.000 description 9
- 238000006073 displacement reaction Methods 0.000 description 5
- 238000004804 winding Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000008054 signal transmission Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000013142 basic testing Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000004353 relayed correlation spectroscopy Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
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- Tests Of Electronic Circuits (AREA)
Abstract
The utility model provides a test circuit board installs on a test machine for test at least an element that waits to test, and this test circuit board includes: at least one test circuit, which is directly mounted on the test circuit board by means of printed circuit and is provided with at least one element slot to be tested for placing the element to be tested for testing; and a plurality of signal receiving and sending points, which are used for receiving a plurality of test signals sent by the tester, sending the plurality of test signals to the at least one element to be tested slot through the at least one test circuit to test the at least one element to be tested, and sending a plurality of output signals correspondingly generated by the at least one element to be tested according to the plurality of test signals to the tester. The utility model discloses can make the work complexity of test simplify by a wide margin and make efficiency promote, the data information that records simultaneously is also comparatively accurate.
Description
Technical field
The utility model is a kind of testing circuit board, refers to a kind of testing circuit board that is used for testing element to be tested especially.
Background technology
In order to ensure integrated circuit (integrated circuit, IC) quality during shipment, after finishing manufacture process, generally all can carry out test to each IC, manufacturer can be according to the result who IC is carried out test, decide this IC whether qualified, and judge whether this IC to be supplied to the manufacturer in downstream according to this.
See also Fig. 1, Figure 1 shows that prior art is used for carrying out the test structure synoptic diagram of IC volume production test.In this test structure, utilize test machine (tester) 10 to be used as testing element to be tested (Device Under Test, DUT) 22 instrument.Wherein, element 22 to be tested can be an integrated circuit (IC) to be measured, and for convenient test, element 22 to be tested is arranged on the element circuitry plate to be tested (DUT board) 20 usually.
See also Fig. 2, Figure 2 shows that the synoptic diagram of the testing circuit board of prior art.As Fig. 1 and shown in Figure 2, usually, test machine (10) is when testing, usually the exclusive element circuitry plate to be tested (20) of all arranging in pairs or groups is tested, and according to different elements to be tested (22), circuit on its corresponding element circuitry plate to be tested (20) is also different, usually include some basic test connection end points (24) on the element circuitry plate to be tested (20) and test, for example: power end (DPS) in order to treat testing element (22), relay control end (RELAY CONTROL), tunnel ends (CHANNEL), the CBIT end, general-purpose hole or the like.
In addition, the problem of utilizing artificial wiring to bring that solves has also been arranged artificially, and adopted another kind of mode, this kind mode utilizes the test circuit with required use to be installed in addition on the printed circuit board (PCB), and on the printed circuit board (PCB) with on the element circuitry plate to be tested (DUT board) a plurality of winding displacement access slots are being set respectively, utilize winding displacement to connect printed circuit board (PCB) and element circuitry plate to be tested (DUT board) again,, test to treat testing element in order to test signal is sent to printed circuit board (PCB).
The utility model content
Past often all needs to utilize the mode of artificial wiring to make element circuitry plate to be tested when carrying out the IC test, but this mode is trouble and easy wrong quite, can cause the tester must waste the extra time in such cases and carry out debug, not only expend time in and labor intensive; If utilizing the mode that connects a P.e.c. tests, though the problem that can avoid artificial wiring to give birth to, but as the element to be tested of required test is when needing the above high-frequency element under test of high stable voltage and 20MHZ, then disturb because of winding displacement produces signal when carrying out the signal transmission easily, make test produce error; Therefore, the utility model fundamental purpose is for a kind of testing circuit board is provided, to solve the above problems.
The utility model is a kind of testing circuit board, be installed on the test machine, be used for testing at least one element to be tested (device under test, DUT), comprise: at least one test circuit, utilize the mode of P.e.c. directly should to be installed on this testing circuit board by at least one test circuit, and this at least one test circuit is provided with at least one element slot to be tested, in order to place this at least one element to be tested to test; And a plurality of signals are picked a little, be used for receiving a plurality of test signals that this test machine sends, and should a plurality of test signals be sent to this at least one element slot to be tested by this at least one test circuit and come this at least one element to be tested is tested, and transmit a plurality of output signal to this test machines of this at least one element to be tested according to the correspondence generation of this a plurality of test signals institute.
Testing circuit board described in the utility model, this at least one test circuit refers to four groups of test circuits, makes this testing circuit board once test four elements to be tested.
Testing circuit board described in the utility model also comprises on this testing circuit board: a plurality of bolt-lock posts or bolt-lock hole firmly are set up on this test machine this testing circuit board.
Testing circuit board described in the utility model, this test machine are the test machine of a VTT V8000.
Testing circuit board described in the utility model, this at least one element to be tested is integrated circuit or wafer.
Testing circuit board described in the utility model, this at least one element to be tested refer to that needs 20 megahertzes are with the element under test of upper frequency when testing.
Testing circuit board described in the utility model, this at least one element to be tested need to refer to the element under test of high stable voltage when testing, and the size of this high stable voltage is between 2.5 volts to 60 volts.
By testing circuit board of the present utility model, not only can solve outside the time-consuming problem of easily makeing mistakes of utilizing artificial wiring generation, simultaneously also because of only needing with utilizing single testing circuit board to survey, so do not have because of the winding displacement problem that the generation signal disturbs when carrying out the signal transmission; The work complexity of test is significantly simplified and made improved efficiency, simultaneously measured data message is also comparatively accurate.
Description of drawings
Fig. 1 is used for carrying out the test structure synoptic diagram of IC volume production test for prior art.
Figure 2 shows that the synoptic diagram of the testing circuit board of prior art.
Figure 3 shows that the synoptic diagram (front) of testing circuit board of the present utility model.
Figure 4 shows that the synoptic diagram (reverse side) of testing circuit board of the present utility model.
Figure 5 shows that the synoptic diagram of test machine.
Figure 6 shows that the synoptic diagram of the locking dish of test machine.
Figure 7 shows that testing circuit board of the present utility model is incorporated into the synoptic diagram on the test machine.
Embodiment
More understand the purpose of this utility model, technical characterictic and effect for making, enumerate a preferred embodiment, and cooperate appended graphic elaborating.
See also Fig. 3 to Fig. 7, the utility model is a kind of testing circuit board (3), be installed on a test machine (4) and go up (present embodiment is done explanation with the test machine of the VTT V8000 that VLSI TEST TECHNOLOGYInc. is produced), can once test four elements to be tested (device under test, DUT); This testing circuit board comprises:
Four groups of test circuits (31), utilize the mode of P.e.c. directly required test circuit to be installed on this testing circuit board (3), and this test circuit (31) is provided with four groups of element slots to be tested (32), in order to place this element to be tested to test;
A plurality of signals are picked point (33), be used for receiving a plurality of test signals that row's pin (41) of this test machine (4) is sent, and by this test circuit (31) this test signal be sent to this element slot to be tested (32) this element to be tested is tested; Also transmit simultaneously this testing element a plurality of these test machines (4) that output signal to according to the corresponding generation of this test signal institute; And
A plurality of bolt-locks hole (34) (also can be the bolt-lock post, change according to the different test modes of different test machines), go up on the corresponding bolt-lock post (42) in order to be bonded to this test machine (4), utilize the locking dish (43) on this test machine (4) that this testing circuit board (3) firmly is set up on this test machine (4) again.
Testing circuit board of the present utility model (3) refers to be used in testing integrated circuits (Integrated Circuit especially, IC) or wafer, and when the environment of test needs the above high-frequency of high stable voltage and 20MHZ, compare with other modes or testing circuit board, resulting effect is more remarkable, wherein this high stable voltage range is 2.5V to 60V, and it can reach the accurate of test value when stabilized power source is provided.
By the various embodiments described above as can be known, by testing circuit board of the present utility model, not only can solve the time-consuming problem of easily makeing mistakes of utilizing artificial wiring to produce, simultaneously also because of only utilizing single testing circuit board to survey, so do not have because of the winding displacement problem that the generation signal disturbs when carrying out the signal transmission; The work complexity of test is significantly simplified and made improved efficiency, simultaneously measured data message is also comparatively accurate.
The above only is the utility model preferred embodiment; so it is not in order to limit scope of the present utility model; any personnel that are familiar with this technology; in not breaking away from spirit and scope of the present utility model; can do further improvement and variation on this basis, so the scope that claims were defined that protection domain of the present utility model is worked as with the application is as the criterion.
Being simply described as follows of symbol in the accompanying drawing:
10: test machine
20: element circuitry plate to be tested
22: element to be tested
24: connection end point
28: connecting line
3: testing circuit board
31: test circuit
32: element slot to be tested
33: signal is picked a little
34: the bolt-lock hole
4: test machine
41: row's pin
42: the bolt-lock post
43: the locking dish.
Claims (7)
1. a testing circuit board is characterized in that, is installed on the test machine, is used for testing at least one element to be tested, and this testing circuit board comprises:
At least one test circuit, utilize the mode of P.e.c. directly should to be installed on this testing circuit board by at least one test circuit, and this at least one test circuit is provided with at least one element slot to be tested, and this at least one element slot to be tested is in order to place this at least one element to be tested to test; And
A plurality of signals are picked a little, be used for receiving a plurality of test signals that this test machine sends, and should a plurality of test signals be sent to this at least one element slot to be tested by this at least one test circuit and come this at least one element to be tested is tested, and transmit a plurality of output signal to this test machines of this at least one element to be tested according to the correspondence generation of this a plurality of test signals institute.
2. testing circuit board according to claim 1 is characterized in that, this at least one test circuit refers to four groups of test circuits, makes this testing circuit board once test four elements to be tested.
3. testing circuit board according to claim 1 is characterized in that, also comprises on this testing circuit board: a plurality of bolt-lock posts or bolt-lock hole firmly are set up on this test machine this testing circuit board.
4. testing circuit board according to claim 1 is characterized in that, this test machine is the test machine of a VTT V8000.
5. testing circuit board according to claim 1 is characterized in that, this at least one element to be tested is integrated circuit or wafer.
6. testing circuit board according to claim 1 is characterized in that, this at least one element to be tested refers to that needs 20 megahertzes are with the element under test of upper frequency when testing.
7. testing circuit board according to claim 6 is characterized in that, this at least one element to be tested need to refer to the element under test of high stable voltage when testing, and the size of this high stable voltage is between 2.5 volts to 60 volts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920150603 CN201417298Y (en) | 2009-04-28 | 2009-04-28 | test circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200920150603 CN201417298Y (en) | 2009-04-28 | 2009-04-28 | test circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201417298Y true CN201417298Y (en) | 2010-03-03 |
Family
ID=41793722
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200920150603 Expired - Fee Related CN201417298Y (en) | 2009-04-28 | 2009-04-28 | test circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201417298Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103116119A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Test board based on hyper memory (HM) 276 stack-type electronic products and test method thereof |
-
2009
- 2009-04-28 CN CN 200920150603 patent/CN201417298Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103116119A (en) * | 2011-11-17 | 2013-05-22 | 上海航天测控通信研究所 | Test board based on hyper memory (HM) 276 stack-type electronic products and test method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100303 Termination date: 20150428 |
|
| EXPY | Termination of patent right or utility model |