CN201378851Y - A CCD image data acquisition device - Google Patents

Abstract

A CCD image data acquisition device comprises a CCD camera, a Camera Link interface conversion chip, an FPGA, an SDRAM cache chip and a PCI interface chip. Among them, the CCD camera collects CCD camera data through the Camera Link interface, and the Camera Link interface conversion chip realizes the conversion of the collected CCD camera data and then inputs it to the FPGA; three module units are mainly implemented inside the FPGA: FIFO buffer unit, SDRAM controller unit and PCI interface modules. The SDRAM controller unit is used for reading and writing control of the SDRAM chip, and realizes the cache of the entire frame of CCD image data; the PCI interface module unit is connected with the PCI interface chip, and transmits the data set output from the SDRAM cache to the computer, thereby realizing the CCD image For data collection, the device has the advantages of good real-time performance and is applicable to CCD cameras with different resolutions.

Description

A CCD image data acquisition device

technical field

The utility model relates to the field of real-time image acquisition, in particular to a CCD image data acquisition device.

Background technique

Aiming at the occasion of CCD real-time acquisition and processing, a CCD image data acquisition device is designed. At present, the usual transmission interfaces include USB interface, 1394 interface and LVDS (Low Voltage Differential Signaling) interface. Among them, the LVDS interface is commonly used in various real-time data processing occasions due to its advantages of low power consumption, low noise and long transmission distance. However, in the case of high-speed transmission of large-capacity data, the transmission speed of the above-mentioned interface cannot meet the real-time requirements.

Utility model content

In order to solve the problem of mismatching transmission rate of CCD cameras with high resolution and high frame frequency, the utility model proposes a CCD image data acquisition device. The device can realize real-time acquisition and transmission of a CCD camera with high resolution and high frame rate, and has the advantages of fast transmission rate and good real-time performance.

CCD image data acquisition device of the present utility model, this device comprises CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and PCI interface chip. Among them, the CCD camera collects CCD camera data through the Camera Link interface, and the Camera Link interface conversion chip realizes the interface conversion of the collected CCD camera data and then inputs it to the FPGA. For the CCD data input to FPGA, three module units are mainly realized inside FPGA: FIFO buffer unit, SDRAM controller unit and PCI interface module unit. The FIFO buffer unit realizes the buffering of the original CCD image, and solves the problem of the mismatch between the output rate of the CCD camera and the input rate of the FPGA; the SDRAM controller unit is connected with the SDRAM buffer chip to realize the buffering of the entire frame of CCD image data; the PCI interface module unit and The PCI interface chip is connected to realize the rapid transmission of the output data from the SDRAM cache to the PC through the PCI bus.

The device is connected with a high-speed Camera Link interface through a CCD camera to realize high-speed transmission of CCD camera data. The data output from the Camera Link interface is decoded by the Camera Link decoding chip and then transmitted to the FPGA. Since the rate of the decoded CCD camera is different from the input rate of the FPGA, the buffering of the read CCD camera data is realized first through the FIFO (first in first out) unit inside the FPGA. Then, the CCD camera data buffered by FIFO is input to SDRAM to cache the whole frame image data. Because SDRAM is a complex state control machine, the SDRAM controller is constructed in FPGA to realize the read and write control of SDRAM. Here, the SDRAM controller is connected to the SDRAM chip. Finally, the output data cached by SDRAM is input to the PCI interface module unit constructed in the FPGA. This unit is connected with the PCI interface chip, and finally the output data from the SDRAM cache is quickly transmitted to the PC through the PCI bus.

The utility model realizes the real-time acquisition and transmission of CCD camera data with high resolution and high frame frequency, has the advantage of good real-time performance and is applicable to CCD cameras with different resolutions.

Description of drawings

The utility model will be explained by way of example and with reference to the accompanying drawings, wherein:

Fig. 1 is the schematic diagram of the principle of the utility model.

Fig. 2 is the read/write state transfer diagram of SDRAM.

Detailed ways

Fig. 1 is the principle schematic diagram of the present utility model, and this device comprises CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and PCI interface chip. Among them, the CCD camera collects CCD camera data through the CameraLink interface, and the Camera Link interface conversion chip realizes the interface conversion of the collected CCD camera data and then inputs it to the FPGA. FPGA mainly implements three module units: FIFO buffer unit, SDRAM controller unit and PCI interface module unit. The FIFO buffer unit realizes the buffering of the original CCD image and solves the problem of the mismatch between the output rate of the CCD camera and the input rate of the FPGA; the SDRAM controller unit is connected with the SDRAM cache chip to control the reading and writing of the SDRAM and realize the entire frame of CCD image data The cache; the PCI interface module unit is connected to the PCI interface chip, and the output data from the SDRAM cache is quickly transmitted to the PC through the PCI bus.

The CCD camera is connected with the high-speed Camera Link interface to realize the high-speed transmission of CCD camera data. The data output from the Camera Link interface is decoded by the Camera Link decoder chip DS90CR288A and then transmitted to the FPGA. Since the data rate of the decoded CCD camera is different from the input rate of the FPGA, the buffering of the read CCD camera data is realized first through the FIFO (first in first out) unit inside the FPGA. Then, the CCD camera data buffered by FIFO is input to SDRAM to cache the whole frame image data. Because SDRAM is a complex state control machine, the SDRAM controller is constructed in FPGA to realize the read and write control of SDRAM. Here, the SDRAM controller is connected to the SDRAM chip. Finally, the output data cached by SDRAM is input to the PCI interface module unit constructed in the FPGA, and the PCI interface module unit is connected with the PCI interface chip PCI9054, and finally the output data from the SDRAM cache is quickly transmitted to the on the PC.

According to the function and design requirements of the device, a hardware platform based on programmable logic device (FPGA) is proposed. Because the real-time requirements of the device are very high, and at the same time, a large amount of data throughput (up to 80 MHz) is required, it is very difficult for existing processors to process such large-throughput data in real time. Therefore, FPGA is used to construct a special processing unit in the device. On the one hand, the rich I/O pins of the device can be used to complete data throughput, and on the other hand, it can be used to improve real-time performance; at the same time, the superiority of FPGA in complex logic control The SDRAM controller and the PCI interface module are constructed in the FPGA to realize the complex logic timing control of the SDRAM chip and the PCI interface chip.

First, the data exchange between the CCD camera and the Camera Link interface. Currently, most digital video solutions are considered as LVDS communication technology. Although LVDS has been improved compared to RS-422, it still requires large-capacity cables and is limited in transmission rate. In order to solve this problem, National Semiconductor developed the Camera Link standard based on Channel Link technology. Channel Link is developed based on LVDS technology, which is a new technology used to transmit video data. Channel Link uses a parallel-to-serial driver and a serial-to-parallel receiver to transmit data, and its maximum rate can reach 2.38G. The Channel Link driver converts 28-bit CMOS/TTL signals into four LVDS data streams. A PLL clock is transmitted in parallel with the other LVDS data streams over the fifth LVDS link. In each cycle of the transmit clock, 28 bits of input data are sampled and transmitted. The Channel Link receiver converts the data stream back to 28-bit CMOS/TTL parallel data.

In the Camera Link standard, camera signals are divided into 4 types:

1. High-speed camera control signal: 4 pairs of LVDS differential signals are used as conventional camera control signals. They are external synchronization signal (EXSYNC), reset signal (PRIN), forward signal (FORWARD) and reserved signal (Future Use).

2. Video data: 4 pairs of LVDS data signals (X0, X1, X2, X3) and a pair of LVDS clock signals (XCLK)

3. Power supply: transmitted by a dedicated cable.

4. Low-speed serial communication: Two pairs of LVDS signals are used as asynchronous communication signals between the camera and the board. Serial-To-Frame-Grabbers (SerTFG) is the communication signal received by the camera output board; Serial-To-Camera (SerTC) is the communication signal received by the camera output by the board. The communication protocol complies with the asynchronous communication protocol, which is the RS232 protocol. The Camera Link standard recommends using a format with a minimum of 9600bps, 1 start bit, 8 data bits, 1 stop bit, no handshake and no parity.

It can be seen that the CCD digital camera realizes the conversion of multiple high-speed parallel data lines into serial data line output through the connection of the Camera Link interface. At the same time, the receiving board restores the serial data output by the CCD camera to the original parallel data output through the receiving chip DS90CR288A, and at the same time provides the corresponding CCD camera communication signals and effective control signals.

Then, input the CCD camera data that DS90CR288A decodes and outputs to FPGA. There are mainly three processing units in FPGA: FIFO buffer unit, SDRAM controller unit and PCI interface module unit.

The FIFO buffer unit mainly realizes the matching of the CCD camera data rate and FPGA rate decoded and outputted from DS90CR288A.

The SDRAM controller unit realizes the cache of the original image by constructing the SDRAM controller inside the FPGA. Here, the SDRAM controller unit is connected to the SDRAM memory chip. SDRAM memory chooses HY57V281620HCT produced by HYNIX Company. Its synchronous interface and fully pipelined internal structure make it have a huge data rate, which is very suitable for large throughput data storage.

The SDRAM controller is implemented using a state machine. The state machine includes the following states: initialization state, idle state, read-write state, pre-charge state, refresh state, and activation state. When the system is powered on and reset, the initialization of SDRAM is completed first. Initialization includes initialization delay, initialization precharge, initialization refresh and initialization mode register setting. Considering the efficiency problem, the working mode of the mode register is a full-page burst, and the fixed CAS (read command input to data output delay) is 2 clock cycles. After initialization, SDRAM enters the idle state. In the idle state, if a read and write request is sent to SDRAM, the SDRAM controller enters the row activation state, and then enters the read/write state after two clock cycles to read and write SDRAM.

After the SDRAM enters the state of writing data, due to the full-page burst working mode, one line of data can be written in one write operation. It should be noted that the current line must be closed to execute the prefill command before the last write operation ends and the next write operation. After the pre-charge state, the next line can be activated again for the next write operation after two clock cycles. Since the dynamic memory has the problem of timing refresh, after data is written into the storage unit, if the data is not lost, it needs to be refreshed within a given interval, that is, it enters the refresh state. It can be seen that under the control of the high-speed clock rate of SDRAM, through the full-page burst write operation mode, the transmission of one line of image data can be completed during the line blanking period for the collected video image. When receiving the next line of image data, repeat the above operations until the entire image data is written into the SDRAM.

After the SDRAM enters the state of reading data, the SDRAM data terminal can read the data only after the CAS (read command input to data output delay) time. Since the SDRAM read/write operation adopts the full-page burst mode, when the SDRAM reads a row of data, a read data operation is completed. At this time, execute the precharge command to close the current row. After the precharge state, it takes two clock cycles to activate the next row again. Since SDRAM uses capacitors to store data information, the data needs to be refreshed regularly just like the write operation. After the refresh operation is completed, the read command can be sent again until all the data of one frame is read out. The state transition diagram of the entire SDRAM is shown in Figure 2.

Finally, the output data cached by the SDRAM is input to the PCI interface module unit. The meaning of PCI is Peripheral Component Interconnect. The PCI local bus is a high-performance 32/64-bit bus with multiple address lines and data lines. It is used as an interconnect mechanism between high-density integrated peripheral control devices, peripheral plug-in boards and processors/memory. Here, what the PCI chip chooses is the PCI9054 that American PLX Company puts out. PCI9054 adopts the advanced PLX data pipeline structure technology, which can make the data on the local bus be quickly transferred to the PCI bus. In this interface design, we adopted the following design methods:

1. Selection of transmission mode: PCI9054, as a bus master device, supports three transmission modes: master device, slave device and DMA transfer.

The master device mode means that the local processor uses the PCI bus control right to initiate bus transmission.

The slave device mode means that the master device on the PCI bus has the control right of the PCI bus, initiates bus transmission, and operates on the local end.

The DMA transfer method is unique to this bus master device and supports transfers in two directions.

According to actual needs, the slave device mode is mainly used in the system to realize the high-speed storage of the system, and the DMA mode is designed for backup.

2. Selection of working mode: PCI9054 supports three working modes: C mode, J mode and M mode. C mode is a non-multiplexed bus mode that can be controlled by on-chip logic to separate address lines from data lines. M mode is designed for seamless connection with some specific processors, and the hardware interface design is simple without any redundant connection. J mode is a working mode of taking the bus. Its advantage is that the address and data lines are not separated, and it strictly imitates the timing of the PCI bus, which provides a good environment for designers to understand the PCI protocol and better control PCI communication, but it adds a lot the control signal,

In the actual design, the C mode is chosen for simple and reliable logic control.

Through the timing logic control of the PCI interface module unit inside the FPGA to the PCI9054 interface chip, the transmission of commands and parameters is well completed, and the output data of the SDRAM cache is quickly transmitted to the PC through the PCI bus.

Any feature disclosed in this specification (including any appended claims, abstract and drawings), unless expressly stated otherwise, may be replaced by alternative features which are equivalent or serve a similar purpose. That is, unless expressly stated otherwise, each feature is one example only of a series of equivalent or similar features.

The above descriptions are only preferred embodiments of the present utility model, and are not intended to limit the present utility model. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present utility model shall be included in this utility model. within the scope of protection of utility models.

Claims (2)

1, a kind of ccd image data acquisition unit is characterized in that: this device comprises CCD camera, Camera Link interface conversion chip, FPGA, SDRAM cache chip and pci interface chip;

Wherein the CCD camera is gathered the CCD camera data by Camera Link interface, and Camera Link interface conversion chip carries out the CCD camera data to input to FPGA after the interface conversion;

Wherein at inner main three modular units of realizing of FPGA: FIFO buffer cell, sdram controller unit and pci interface module; The sdram controller unit links to each other with the SDRAM cache chip, by reading of SDARM controller control SDRAM cache chip, realizes the buffer memory to whole frame ccd image data; The pci interface modular unit links to each other with pci interface chip, realizes the dateout from the SDRAM buffer memory is passed through pci bus, is transferred on the PC fast.

2, a kind of ccd image data acquisition unit as claimed in claim 1 is characterized in that: described sdram controller unit adopts state machine to realize.