CN104599227B - DDR3 arbitration controllers and method for high-speed CCD data storage - Google Patents

Abstract

DDR3 arbitration controller and method for high-speed CCD data storage. A DDR3 arbitration controller of the present invention includes a read-write control module, a DDR3 arbitration module, an IP core control module, a data format replacement module, and a read-write storage module. The IP core control module is mainly responsible for driving the read-write storage module, so that the read-write storage module can read and write data correctly. The read-write storage module is responsible for matching the data stream given by the front-end with the read-write speed of the read-write storage module. The read-write speed of the read-write storage module is much faster than the front-end data stream and the data stream required by the subsequent circuit, so data is written to read and write The memory module and the data read from the read-write memory module must be speed-matched. The arbitration module is responsible for arbitrating the order of applications when multiple data streams apply for the use of the read-write storage module, determining the response order, and allocating resources for the use of the read-write storage module. The data format conversion module is responsible for converting the data format read from the read-write storage module into the standard format required by subsequent modules.

Description

DDR3 arbitration controller and method for high-speed CCD data storage

technical field

The invention belongs to the field of high-speed CCD image storage, in particular to a DDR3 arbitration controller and method for high-speed CCD data storage.

Background technique

In the video image display of high-speed CCD, some algorithms will use external memory, and the external memory used in the past is SRAM, because SRAM is easy to use, and the use technology of SRAM is close to maturity at present. As the external memory of CCD, the current technology of SRAM can reach the highest operating frequency of 167M, which cannot meet the storage requirements of high-speed CCD. At the same time, SRAM is limited by the technology of chip manufacturing, and its volume can no longer be reduced, and its integration level is low, so it cannot meet the development requirements of miniaturized CCD. In addition, the power consumption of SRAM is relatively large, which is also a problem that cannot be solved by the current technology, so SRAM cannot meet the development requirements of low-power CCD.

Based on the various limitations of SRAM use, the external memory of high-speed CCD is replaced by SDRAM. The first generation SDRAM and the second generation DDR use single-ended clock signals. When the operating frequency is high, the interference is large, and it is rarely used for CCD external storage. The operating frequency of the third-generation DDR2 and the fourth-generation DDR3 is higher than that of the first-generation SDRAM and the second-generation DDR, so a differential clock signal that can reduce interference is used as a synchronous clock. DDR3 has been very mature as a memory technology for notebooks. Due to the fast working speed of DDR3, it is more suitable for high-speed storage, small in size, easy to integrate, and low in power consumption. The external memory of high-speed CCD has also begun to use DDR3, but the interface used by DDR3 The configuration is complex, the data flow speed of the CCD front-end to the memory does not match the read and write speed of DDR3, etc. To use DDR3 as an external memory in a high-speed CCD system, it is necessary to solve problems such as interface configuration and speed matching. But there is still no good solution in the prior art.

Contents of the invention

The technical problem solved by the invention is to provide a DDR3 arbitration controller and method for high-speed CCD data storage.

The technical solution that realizes the object of the present invention is: a kind of DDR3 arbitration controller that is used for high-speed CCD data storage, comprises read-write control module, DDR3 arbitration module, IP core control module, data format conversion module and read-write storage module, so The read-write control module, DDR3 arbitration module, IP core control module, and read-write storage module are connected sequentially, wherein the read-write control module is also connected with the data format conversion module, and the IP core control module and read-write storage module are also connected with the read-write control module connected;

The read-write control module receives the data written to the read-write storage module and the corresponding address input from the outside world, as well as the address corresponding to the data to be read from the read-write storage module. The read-write control module converts the three Signals and read-write control signals are transmitted to the subsequent DDR3 arbitration module;

The DDR3 arbitration control module decides whether to send these three signals to the IP core control module. When the DDR3 arbitration control module decides to give these three signals to the IP core control module, the IP core control module transmits the above three signals to the read-write storage module. At the same time, the write data to be stored in the read-write storage module is written into the corresponding write address in the read-write storage module; the data in the read-write storage module corresponding to the read address is transmitted from the read-write storage module back to the IP core control module, and the IP core The control module transmits the read data and read data enable to the read-write control module, and the read-write control module outputs the read data and read data enable to the data format conversion module, and then outputs to the subsequent circuit after data format conversion use.

The read-write control module includes an address format conversion module, a write data format conversion module, a first read-write control module, a second read-write control module, a write address FIFO module, a write data FIFO module, a read address FIFO module, and a read data FIFO module, a first delay module, a second delay module, a signal feedback module, a FIFO clearing signal generation module and a read data format conversion module;

The address format conversion module and the write data format conversion module are connected to the first read-write module, and the first read-write module is connected to the write address FIFO module, write data FIFO module, read address FIFO module, and signal feedback module; write address FIFO module, write data The FIFO module is connected with the first delay module; the read address FIFO module is connected with the second delay module; the write address FIFO module, the write data FIFO module, and the read address FIFO module are also connected with the second read-write module; the signal feedback module and the read The data FIFO module is connected; the read data FIFO module is connected with the read data format conversion module; the FIFO clearing signal generation module is connected with the write address FIFO module, write data FIFO module, read address FIFO module, and read data FIFO module;

The address format conversion module and the write data format conversion module receive the write data input by the front-end data stream and the corresponding write address, read address, and the read and write control signals fed back from the arbitration module, and convert the four consecutive addresses and data into An address and a data are output together, and a write enable signal is output at the same time. This signal indicates that the data format conversion is completed, and the next step can be performed. These signals are output to the first read-write control module; the first read-write control module will write The address, write data, and read address signals are respectively transmitted to the write address FIFO module, write data FIFO module, and read address FIFO module. The first read and write control module transmits the FIFO write enable signal to the above three FIFO modules at the same time; the second read The write control module receives the write address and write data output from the write address FIFO module and the write data FIFO module, and the second read and write control module simultaneously receives signals indicating the number of data in the two FIFO modules. If the write address FIFO module and the write In the data FIFO module, the number of data reaches a high threshold, and the second read-write control module responds to the write request of the first read-write control module, otherwise it does not respond; the first delay module receives signals indicating whether the two FIFO modules are empty, and then Connect the signal indicating whether the two FIFO modules are read empty to the read enable terminal of the write address FIFO module and the write data FIFO module. When the read empty signal is low, that is, when it is not empty, the read enable is valid, and the high level Invalid; the first read-write control module transmits the read address and FIFO write enable to the read address FIFO module, and the second read-write control module receives the read address read from the read address FIFO module and the data in the flag read address FIFO module If the number of data in the read address FIFO module reaches a high threshold, the second read-write control module responds to the read request of the first read-write control module; the signal indicating whether the read address FIFO module is empty passes through the second delay module Transmitted to the read enable terminal of the read address FIFO module, when the read empty signal is low, the read enable is valid, and the high level is invalid; the data input terminal of the read data FIFO module receives the read data transmitted back from the IP core control module , the write enable end of the read data FIFO receives the read data transmitted back from the IP core control module, and the first read-write control module receives the signal indicating the read data FIFO module, so that the read-write control module reads according to the data in the address FIFO module Number to decide to respond to the read request, the feedback module receives the signal indicating whether the read data FIFO module is empty. Data readout, that is, if the read data FIFO module has been read empty, the signal indicating whether the read data FIFO module is read empty is high level, and becomes low level after passing through the NOT gate, no matter whether the feedback signal is high level or low level Ping, the FIFO read enable of the read data FIFO module is invalid, if the signal indicating whether the read data FIFO module is empty is low level, and becomes high level after passing through the NOT gate, then it is judged that the first read/write control module sends opposite Feed request signal, if the signal is high level, the FIFO read enable of the read data FIFO module is valid, otherwise it is invalid; the read data format conversion module receives the read data read by the read data FIFO module, and converts one data into continuous Four data, the read data output from the read data format conversion module is used by the subsequent arbitration module; the clear signal generation module receives the frame signal input by the front-end data stream, the read and write request signal fed back by the arbitration module, and whether the flag read data FIFO module Read the empty signal, the clear signal generated by this module is used by the four FIFO modules to ensure that the four FIFO modules are cleared at the end of each frame.

The first delay module and the second delay module in the read-write control module all include a NOT gate, two AND gates and a clock delay module, and the above-mentioned NOT gate is connected with the clock delay module through an AND gate, and the clock The delay module is also connected with another AND gate, and the output of the other AND gate is the output of the delay module;

The clock delay module receives the signal indicating whether the FIFO is empty and passes through the NOT gate and the high-level signal. After the clock delay module delays one clock, the output signal is again ANDed with the high level, and the output result is used as a read-write The read enable signal of the read data FIFO module in the control module.

The data format conversion module includes a data buffer FIFO module and a format conversion module, the data buffer FIFO module and the format conversion module are connected in sequence, and the data buffer FIFO module receives the data read from the read-write storage module and the corresponding data output enable, The format conversion module receives the data output from the data buffer FIFO module and the frame signal from the front-end data stream, and the final output data of the format conversion module is a standard image signal.

The read-write storage module adopts DDR3 chip, and the model is MT41J128M16-15E.

A method based on the above-mentioned DDR3 arbitration controller, specifically comprising the following steps:

(1) The front-end data stream writes the data to be written into the read-write storage module, the address to be written, and the address to read out to the read-write control module. The read-write control module judges whether the written data meets the threshold condition. When When the threshold condition is reached, the read-write control module sends a read-write request to the DDR3 arbitration module;

(2) The DDR3 arbitration module performs arbitration according to the order of multiple data stream applications, and determines the response order of the read-write storage module. When it decides to respond to the data stream application, the DDR3 arbitration module sends a read-write request to the IP core control module. ;

(3) The IP core control module responds to the read-write request of the DDR3 arbitration module, starts to drive the read-write storage module, writes data into the address corresponding to the read-write storage module, or reads out the data corresponding to the address in the read-write storage module, and inputs Data format conversion module;

(4) The data format conversion module converts the data read from the read-write storage module into the standard format required by the subsequent modules, and creates line and frame signals that match the standard image format for use by the subsequent modules.

Compared with the prior art, the present invention has the remarkable advantages as follows: 1) The DDR3 arbitration controller of the present invention has a fast read and write speed, which is much faster than the memory SRAM made by the previous CCD, and the SRAM read and write speed is the highest. It can reach 167 megabytes, and DDR3 chips can reach hundreds of megabytes. 2) The DDR3 chip is much smaller than the SRAM, and has a high degree of integration, which saves design space. 3) The power consumption of DDR3 chips is lower than that of SRAM, which can reduce the working pressure of the power board in the CCD system. 4) The DDR3 arbitration controller of the present invention can realize the alternate use of DDR3 chips by multiple data streams. 5) The use interface and configuration of DDR3 chips are much more complicated than SRAM, and there are more restrictions, but the use interface provided by the present invention to users is simple, with fewer restrictions, and the use of the interface is almost the same as that of SRAM.

The present invention will be described in further detail below in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a basic flow chart of the read and write control module.

FIG. 2 is a schematic structural diagram of the delay module in FIG. 1 .

Fig. 3 is a structural diagram of the data format conversion module.

Figure 4 is a complete external interface diagram of the DDR3 arbitration controller.

FIG. 5 is a structural diagram of the DDR3 arbitration controller of the present invention.

Figure 6 is a pin interface diagram of the IP core control module.

Fig. 7 is a format diagram of the data stream read and written according to the specific embodiment of the present invention.

detailed description

A DDR3 arbitration controller of the present invention includes a read-write control module, a DDR3 arbitration module, an IP core control module, a data format replacement module, and a read-write storage module. The IP core control module is mainly responsible for driving the read-write storage module, so that the read-write storage module can read and write data correctly. The read-write storage module is mainly responsible for matching the data flow provided by the front-end with the read-write speed of the read-write storage module. The read-write speed of the read-write storage module is as high as hundreds of megabytes. The front-end data stream cannot reach this speed, and subsequent modules cannot. Such a fast speed is required, so the data written into the read-write storage module and the data read from the read-write storage module must be matched in speed. The arbitration module is mainly responsible for arbitrating the order of applications when multiple data streams apply for the use of the read-write storage module, deciding which data stream application to respond to first, and allocating resources for the read-write storage module. The data format conversion module is mainly responsible for converting the data format read from the read-write storage module into the standard format required by subsequent modules.

The present invention will be further elaborated below in conjunction with the accompanying drawings.

In conjunction with Fig. 1, the read-write control module invented by the DDR3 arbitration controller of the present invention for high-speed CCD data storage includes an address format conversion module, a write data format conversion module, a first read-write control module, a second read-write control module, Write address FIFO module, write data FIFO module, read address FIFO module, read data FIFO module, first delay module, second delay module, signal feedback module, FIFO clear signal generation module, read data format conversion module.

The address format conversion module and the write data format conversion module convert 4 consecutive input addresses and data into one address and data, so the number of addresses and data lines provided for the previous data stream must be an integer multiple of 4. The read data format conversion module converts one data into data with 4 consecutive addresses. Therefore, the number of output data lines is also an integer multiple of 4, so combined with Figure 5, the data output from DDR3 must be converted into a standard data format through the data format before it can be used by subsequent modules.

When data needs to be written, the algorithm basic module continuously sends the address and data to be written to the write address FIFO and write data FIFO; when the number of write data FIFO and write address FIFO exceeds the set high threshold (the threshold is determined according When setting, such as 512 bytes), apply to the DDR3 arbitration controller to start reading the write address FIFO and write data FIFO, write the data in the write data FIFO to the corresponding address in DDR3, when the number of write address FIFO When it is lower than the set low threshold (the threshold is set according to needs, such as 256 bytes), it applies to the DDR3 arbitration controller to stop reading the write address FIFO and write data FIFO; The number of addresses in the write address FIFO is counted. When the number of frames is almost full, a write frame end signal wf_end is given (after the penultimate read stop signal, a high level is given before the last read stop signal, Set to zero after the last read stop signal) to the arbitration controller, this signal shields the last read stop signal, so that the arbitration module can read the address and data in the two FIFOs respectively until the two FIFOs are empty (the FIFO can be set to The empty signal is connected to the arbitration module to monitor whether the FIFO is empty), and the read operation is stopped. At this time, the address and data read operation of a whole frame of image is completed, and the entire image is written into DDR3.

Before the algorithm needs to read data in a certain memory space, it needs to store the address of the data to be read into the read address FIFO, and the basic module of the algorithm continuously writes the read address into the read address FIFO under the control of the read control signal; When the memory space of the read address FIFO is more than the set high threshold (the threshold is set according to the need, such as 896 bytes), apply to the DDR3 arbitration controller to start the read operation of the read address FIFO, and read the corresponding The data at the address is written to the read data FIFO. When the memory space of the read address FIFO is less than the set low threshold (the threshold is set according to needs, such as 768 bytes), apply to the DDR3 arbitration controller to stop the read operation of the read address FIFO; in the algorithm basic module Count the number of addresses that have been written into the read address FIFO. When the number of frames is almost full, a read frame end signal rf_end is given (after the penultimate read stop signal and before the last read stop signal) High level, set to zero after the last read stop signal) to the arbitration controller, this signal shields the read stop signal of the last read address FIFO, so that the arbitration module can always read the addresses in the read address FIFO until it is empty (The empty signal of the read address FIFO can be connected to the arbitration module to monitor whether it is empty). The read data FIFO is: if the read data FIFO data exceeds the set high threshold (such as 768 bytes), the algorithm basic module continuously reads the data in the read data FIFO and counts them. Stop reading at frame time. The blanking time between frames is made the same by FIFO buffering.

All FIFOs need to be emptied after read and write operations are complete. The data output enable signal output from the read-write control module is synchronized with the data output from the read data FIFO. When the data is output from the read data FIFO, the data output enable is set to high level, otherwise it is set to low power. flat.

In conjunction with Fig. 2, the read-write control module invented by the DDR3 arbitration controller used for high-speed CCD data storage in the present invention, the signal indicating whether the FIFO is read empty is output to the delay module through the signal of the NOT gate and the high-level phase AND, and the delay The signal output by the timing module after a delay of one clock is ANDed with the high level again, and the output result is used as the read enable signal of the FIFO.

In conjunction with FIG. 3 , the data format conversion module invented by the DDR3 arbitration controller for high-speed CCD data storage of the present invention includes a data buffer FIFO module and a format conversion module. When the data output is enabled at a high level, it means that DDR3 starts to read data. The data read from DDR3 is cached in the data buffer FIFO module for 3 lines, and the data read from the FIFO and the frame signal given by the front-end data stream ( mark the beginning of a frame image) input format conversion module, and finally output the standard data format, line signal (marking the beginning of a line of image image) and frame signal required by subsequent modules.

Combined with Figure 5, it is a single data stream application to use the DDR3 signal connection structure, including the read-write control module, arbitration module, IP core control module, data format conversion module, the data and corresponding addresses that the front-end data stream will write to DDR3, and the required The address corresponding to the read data is written to the read-write control module, and the read-write control module decides whether to send these three signals and the read-write control signal to the subsequent arbitration module according to the threshold condition, and the arbitration module decides whether to send these three signals to DDR3 Controller IP core. When the arbitration module decides to send the three signals to the controller IP core, the DDR3 controller IP core transmits these three signals to the DDR3 chip. The write data to be stored in DDR3 is written into the corresponding write address in DDR3. The data in the DDR3 corresponding to the read address is sent back from the DDR3 chip to the IP core of the DDR3 controller. The IP core transmits the read data and the read data enable to the read-write control module, and the read-write control module outputs to the data format conversion module. After the data format is converted, it is output to the subsequent circuit for use.

The working process of the arbitration module takes two data streams as an example. Data stream 1 is marked as '01' and data stream 2 is marked as '10'. When neither algorithm is applied, the current state is marked as '00'. When When data stream 1 is applied for, the current state is marked as '01'. When data stream 1 has not been executed, if data stream 2 also applies for DDR3 at this time, DDR3 will continue to apply for data stream 1 at this moment, and data stream 2 will be Be in the application queue. After data flow 1 is executed, mark the current mark as '10' and execute data flow 2. If data stream 1 and data stream 2 apply at the same time, according to the sequence, DDR3 responds to the application of data stream 1 first, and then responds to the application of data stream 2 after execution.

In the case of a single data stream application, the arbitration module does not actually play a role. Only when multiple data streams apply for DDR3 will the arbitration module play a substantial role.

Combined with Figure 6, the pin interface diagram of the IP core control module, the IP core control module is a soft core generated by quartus, and the generation steps are:

TOOLS->MegaWizard Plug-In Manager. The setting of the IP core is based on the DDR3 model, refer to the datasheet of the DDR3 chip to select the parameter configuration. After the parameters are configured, click Finish, and then click Generate. After generating the IP core, you need to configure the pins of the module. Some pins are defined as follows:

(1) The pins beginning with mem are directly connected to the DDR3 chip and do not need to be configured.

(2) pll_ref_clk is the reference clock of the IP core, which is different from afi_clk and afi_half_clk. Afi_clk and afi_half_clk are the clocks for DDR3 to read data. Which clock to use to read data needs to be set when generating the IP core.

(3) global_reset_n and soft_reset_n are reset signals, which are generally set to high level.

(4) avl_ready is similar to the enable signal, it is DDR3 telling the user that it is ready to start reading and writing data.

(5) avl_rdata_valid is a read valid signal. When it is high level, the read data is valid. This signal is used as the enable port of DDR3 data output for the data format conversion module.

(6) avl_be is a bit enable signal, generally set to 1.

(7) avl_size is the number of data read and written at one time.

(8) avl_addr, avl_wdata, and avl_write_req are the write address, write data, and write enable respectively.

(9) avl_rdata and avl_read_req are read data and read enable respectively.

(10) local_init_done, local_cal_success, and local_cal_fail are DDR3 initialization flag signals. When local_init_done, local_cal_success is high and local_cal_fail is low, DDR3 initialization is successful, otherwise initialization is unsuccessful.

(11) oct_rzqin is the impedance matching pin of DDR3, which needs to be connected to a certain pin of FPGA.

After the pins are configured, compile first. When the compilation proceeds to Fitter (Place&Route), an error will be reported. When the reported errors are more than 700 identical errors, you need to run a program that automatically allocates pins. Steps: Tools->TclScripts ->Pin assignment, and then compile again to compile successfully. After experimental debugging, it is found that these two steps must be followed in order to compile and pass.

In conjunction with Fig. 4, it is a schematic diagram of a complete external interface of the present invention, which is an interface with 5 data streams in total, and the interface of each algorithm includes write clock, write enable, write data, write address, read enable, read address, read Data is used in the same way as RAM. Each algorithm corresponds to a set of output interfaces, which are field signal, line signal, and data output.

In conjunction with Fig. 7, specific embodiments of the present invention: the software used by the present invention is quartus12.1, the FPGA used is Cyclone V, the DDR3 chip model adopted is MT41J128M16-15E, and the data format adopted by the CCD is shown in Figure 7. In this data format, there are 236 invalid data in front of each line, and 426 invalid data in the back, and only 1920 valid data in the middle. In order to meet the address of writing data is a continuous integer multiple of 4, only write when writing data into DDR3 The valid data entered in each line is 1920*1150. After the data format conversion, the input data format is shown in Figure 7, which is 2583*1150. There are 236 invalid data in the front of each line, and 426 invalid data in the back. The data stream output by the front end of the CCD is four channels of data, and DDR3 storage is required to combine these channels of data into a complete image. First, the four channels of data are combined into two channels of data through RAM, namely the upper half image and the lower half image, and the valid data of these two image signals are stored in the corresponding addresses of DDR3, and then a complete image signal is input. The signal only contains valid data of each line of signal, and the image signal can be obtained in the standard format shown in Figure 7 after passing through the data format conversion module.

Claims (5)

1. a DDR3 arbitration controller for high-speed CCD data storage, is characterized in that, comprises read-write control module, DDR3 arbitration module, IP core control module, data format conversion module and read-write storage module, described read-write control Module, DDR3 arbitration module, IP core control module, and read-write storage module are connected sequentially, wherein the read-write control module is also connected with the data format conversion module, and the IP core control module and read-write storage module are also connected with the read-write control module; The read-write control module receives the data written to the read-write storage module and the corresponding address input from the outside world, as well as the address corresponding to the data to be read from the read-write storage module. The read-write control module converts the three Signals and read-write control signals are transmitted to the subsequent DDR3 arbitration module; The DDR3 arbitration control module decides whether to send these three signals to the IP core control module. When the DDR3 arbitration control module decides to give these three signals to the IP core control module, the IP core control module transmits the above three signals to the read-write storage module. At the same time, the write data to be stored in the read-write storage module is written into the corresponding write address in the read-write storage module; the data in the read-write storage module corresponding to the read address is transmitted from the read-write storage module back to the IP core control module, and the IP core The control module transmits the read data and read data enable to the read-write control module, and the read-write control module outputs the read data and read data enable to the data format conversion module, and then outputs to the subsequent circuit after data format conversion use; The read-write control module includes an address format conversion module, a write data format conversion module, a first read-write control module, a second read-write control module, a write address FIFO module, a write data FIFO module, a read address FIFO module, and a read data FIFO module, a first delay module, a second delay module, a signal feedback module, a FIFO clearing signal generation module and a read data format conversion module; The address format conversion module and the write data format conversion module are respectively connected to the first read-write module, the first read-write module is connected to the write address FIFO module, the write data FIFO module, the read address FIFO module, and the signal feedback module; the write address FIFO module, The write data FIFO module is connected to the first delay module; the read address FIFO module is connected to the second delay module; the write address FIFO module, the write data FIFO module, and the read address FIFO module are also connected to the second read-write module; the signal feedback module It is connected with the read data FIFO module; the read data FIFO module is connected with the read data format conversion module; the FIFO clearing signal generation module is connected with the write address FIFO module, write data FIFO module, read address FIFO module, and read data FIFO module; The address format conversion module and the write data format conversion module receive the write data input by the front-end data stream and the corresponding write address, read address, and the read and write control signals fed back from the arbitration module, and convert the four consecutive addresses and data into An address and a data are output together, and a write enable signal is output at the same time. This signal indicates that the data format conversion is completed, and the next step can be performed. These signals are output to the first read-write control module; the first read-write control module will write Address, write data, and read address signals are respectively transmitted to the write address FIFO module, write data FIFO module, and read address FIFO module, and the first read-write control module transmits the FIFO write enable signal to the above-mentioned three FIFO modules; the second read The write control module receives the write address and write data output from the write address FIFO module and the write data FIFO module, and the second read and write control module simultaneously receives signals indicating the number of data in the two FIFO modules. If the write address FIFO module and the write In the data FIFO module, the number of data reaches a high threshold, and the second read-write control module responds to the write request of the first read-write control module, otherwise it does not respond; the first delay module receives signals indicating whether the two FIFO modules are empty, and then Connect the signal indicating whether the two FIFO modules are read empty to the read enable terminal of the write address FIFO module and the write data FIFO module. When the read empty signal is low, that is, when it is not empty, the read enable is valid, and the high level Invalid; the first read-write control module transmits the read address and FIFO write enable to the read address FIFO module, and the second read-write control module receives the read address read from the read address FIFO module and the data in the flag read address FIFO module If the number of data in the read address FIFO module reaches a high threshold, the second read-write control module responds to the read request of the first read-write control module; the signal indicating whether the read address FIFO module is empty passes through the second delay module Transmitted to the read enable terminal of the read address FIFO module, when the read empty signal is low, the read enable is valid, and the high level is invalid; the data input terminal of the read data FIFO module receives the read data transmitted back from the IP core control module , the write enable end of the read data FIFO receives the read data transmitted back from the IP core control module, and the first read-write control module receives the signal indicating the read data FIFO module, so that the read-write control module reads according to the data in the address FIFO module Number to decide to respond to the read request, the feedback module receives the signal indicating whether the read data FIFO module is empty, the above-mentioned signal whether to read empty and the feedback request signal sent by the first read-write control module work together to determine whether to continue to read the data in the FIFO module Data readout, that is, if the read data FIFO module has been read empty, the signal indicating whether the read data FIFO module is read empty is high level, and becomes low level after passing through the NOT gate, no matter the feedback signal is high level or low level Ping, the FIFO read enable of the read data FIFO module is invalid. If the signal indicating whether the read data FIFO module is empty is low level and becomes high level after passing through the NOT gate, it is judged at this time that the first read/write control module sends Feedback request signal, if the signal is high level, the FIFO read enable of the read data FIFO module is valid, otherwise it is invalid; the read data format conversion module receives the read data read by the read data FIFO module, and converts one data into continuous Four data, the read data output from the read data format conversion module is used by the subsequent arbitration module; the clear signal generation module receives the frame signal input by the front-end data stream, the read and write request signal fed back by the arbitration module, and whether the flag read data FIFO module Read the empty signal, the clear signal generated by this module is used by the four FIFO modules to ensure that the four FIFO modules are cleared at the end of each frame. 2. the DDR3 arbitration controller for high-speed CCD data storage according to claim 1, is characterized in that, the first delay module and the second delay module in the read-write control module all comprise a NOT gate, Two AND gates and a clock delay module, the NOT gate is connected to the clock delay module through an AND gate, the clock delay module is also connected to another AND gate, and the output of the other AND gate is the output of the delay module; The clock delay module receives the signal indicating whether the FIFO is empty and passes through the NOT gate and the high-level signal. After the clock delay module delays one clock, the output signal is again ANDed with the high level, and the output result is used as a read-write The read enable signal of the read data FIFO module in the control module. 3. the DDR3 arbitration controller for high-speed CCD data storage according to claim 1, is characterized in that, described data format conversion module comprises data buffer FIFO module and format conversion module, and data buffer FIFO module, format conversion module are sequential Connected, the data cache FIFO module receives the data read from the read-write storage module and the corresponding data output enable, the format conversion module receives the data output from the data cache FIFO module and the frame signal given by the front-end data stream, the format conversion module The final output data is a standard image signal. 4. The DDR3 arbitration controller for high-speed CCD data storage according to claim 1, wherein the read-write storage module adopts a DDR3 chip, and the model is MT41J128M16-15E. 5. a processing method based on the described DDR3 arbitration controller of claim 1, is characterized in that, comprises the following steps: (1) The front-end data stream writes the data to be written into the read-write storage module, the address to be written, and the address to read the data into the read-write control module, and the read-write control module judges whether the written data reaches the threshold condition. When the threshold condition is reached, the read-write control module sends a read-write request to the DDR3 arbitration module; (2) The DDR3 arbitration module performs arbitration according to the sequence of multiple data stream applications, and determines the response sequence of the read-write storage module. When it decides to respond to the application of the data stream, the DDR3 arbitration module sends a read-write request control to the IP core control module ; (3) The IP core control module responds to the read-write request of the DDR3 arbitration module, starts to drive the read-write storage module, writes the data into the address corresponding to the read-write storage module, or reads out the data corresponding to the address in the read-write storage module, input Data format conversion module; (4) The data format conversion module converts the data read from the read-write storage module into the standard format required by the subsequent modules, and creates row signals and frame signals matching the standard image format for use by the subsequent modules.