CN200979668Y - A double-loop low-dropout voltage regulator circuit - Google Patents

Abstract

The utility model discloses a double-loop low-dropout linear regulator circuit, which comprises an error amplifier, a second-stage amplifier, a power tube, a compensation unit, an output sampling network, a load capacitor and a load circuit, a feedforward amplifier, a pull-up drive tube, Pull down the drive and sample tubes. It includes two loops. The main loop includes error amplifier, second amplifier, pull-up drive tube, power tube and output sampling network, forming a negative feedback loop to stabilize the output voltage V _OUT . The additional loop includes a feed-forward amplifier, a sampling tube, a pull-down drive tube and a power tube. The loop refers to the output voltage to form a negative feedback loop. The dynamic compensation circuit further stabilizes the output voltage V _OUT and refers to the load current to form a positive feedback loop. Accelerates the response of the circuit to a step change in load. The utility model enables the circuit to provide better transient response, better peripheral circuit selection, and better phase margin.

Description

A Double Loop Low Dropout Linear Voltage Regulator Circuit

technical field

The utility model belongs to the linear power supply technology, specifically a double-loop low-dropout linear regulator (LDO) circuit, which can improve the dynamic performance of the LDO circuit.

Background technique

With the rapid development of electronic technology, electronic products require higher performance power supply systems. LDO circuit is widely used in lithium battery charging, low-voltage digital circuit power supply and other occasions due to its simple circuit structure, small chip area occupation, low noise, high ripple suppression and other advantages. In order to meet the development needs of the power supply market, good system stability and load transient performance have become the key research direction of linear power supply technology.

A high-precision LDO circuit needs to use a high-gain error amplifier to meet the needs, and high-gain requires frequency compensation to ensure the stable performance of the circuit. However, the higher the performance of the circuit, the higher the gain of the required error amplifier, and the greater the compensation strength required, and often the dynamic performance of the circuit must be sacrificed to meet the requirements. Various frequency compensation schemes are used to provide stability, such as Miller compensation, nested Miller loops, and possibly off-chip or off-die bulk load capacitance as part of the compensation. Although these methods can achieve frequency compensation when the circuit works stably, they more or less sacrifice the dynamic performance of the LDO circuit. This places further constraints on compensation schemes.

FIG. 1 depicts a typical LDO circuit and its frequency compensation unit in the prior art. The working principle of a typical LDO circuit is to compare the output sampling signal V _FB with the reference voltage V _REF , and adjust the output voltage V _OUT to a preset value after amplification. In order to reduce the steady-state error, the circuit adopts a three-stage circuit, including an error amplifier 1, a second-stage amplifier 2, and a power tube 3 to amplify the error signal. The multi-stage amplifier circuit will bring in too many poles, resulting in excessive phase shift, resulting in a serious shortage of phase margin, making it difficult to stabilize the system. In Fig. 1, the compensation unit 4 and the output capacitor 6 are used to introduce a zero point, thereby compensating for too many poles in the circuit. High-precision LDO circuits often require large or complex compensation components to stabilize the system. For example, compensation can be realized by increasing the output capacitor 6 . In this way, the dynamic response of the system will be affected, and it is difficult to obtain a compensation method with the best accuracy and dynamic response.

Contents of the invention

The purpose of the utility model is to provide a double-loop low-dropout linear regulator circuit, which reduces the compensation strength required by the circuit and improves the dynamic performance of the circuit.

The utility model provides a double-loop low-dropout linear voltage regulator circuit, including an error amplifier, a second-stage amplifier, a power tube, a compensation unit, an output sampling network, a load capacitor, and a load circuit; the negative input terminal of the error amplifier is connected to a reference Voltage V _REF , the positive input terminal is connected to the feedback voltage signal V _FB generated by the output sampling network, the error amplifier compares the two input signals, and the error signal of the two input signals is amplified and then single-ended output, the output terminal of the error amplifier and the amplification circuit The input terminal is connected, and the output signal is input to the amplifier circuit for next-stage amplification; the compensation unit is connected at the connection between the output terminal of the error amplifier and the input terminal of the amplifier circuit, and frequency compensation is performed on the circuit; the output sampling network includes series resistors R1 and R2 , the upper end of R2 is connected to the output voltage V _OUT of the LDO circuit; the lower end is connected to the upper end of R1 to generate V _FB potential, which is input to the positive input end of the error amplifier; the lower end of R1 is grounded; the upper end of the load capacitor is connected to the output voltage V _OUT of the LDO circuit, The lower end is grounded; the load circuit is connected to the output voltage V _OUT of the LDO circuit; it is characterized in that:

The circuit also includes a feed-forward amplifier, a pull-up drive tube, a pull-down drive tube and a sampling tube; the negative input terminal of the feed-forward amplifier is connected to the output voltage V _OUT of the LDO circuit; the positive input terminal is connected to the drain end of the sampling tube, and its output The terminal is connected to the gate of the pull-down tube; the source of the pull-up drive tube is connected to the gate of the power tube, its gate is connected to the output of the amplifier circuit, and its drain is connected to the LDO input power supply V _IN or the substrate potential of the LDO power tube ; The drain of the pull-down drive tube is connected to the grid of the power tube, its grid is connected to the output of the feedforward amplifier, and its source is grounded; the sampling tube is connected in parallel with the power tube, and the grid and source of the two are connected respectively, The drain is connected to the non-inverting input of the feedforward amplifier;

The error amplifier, the second amplifier, the pull-up drive tube, the power tube and the output sampling network constitute the main loop, forming a negative feedback loop to stabilize the output voltage V _OUT ; the feedforward amplifier, the sampling tube, the pull-down drive tube and the power tube form an additional loop The loop refers to the output voltage to form a negative feedback loop, and the dynamic compensation circuit further stabilizes the output voltage V _OUT , and refers to the load current to form a positive feedback loop to accelerate the response to the load step change of the circuit.

The utility model adopts a double-loop LDO structure which improves the dynamic performance of the circuit, and the structure has excellent improvement on the load transient response, line transient response and stability of the LDO. The utility model is mainly by adding a feed-forward amplifier AMP2. Compared with the error amplifier in Fig. 1, the amplifier has the characteristics of low gain and high bandwidth. The feed-forward amplifier AMP2 compares the LDO output voltage with the sampling voltage of the sampling LDO power tube current , the output controls the gate drive of the LDO power tube, forming a second loop to improve the dynamic performance of the circuit. Compared with the existing method, the added second loop can compensate a zero point, reduce the compensation intensity of other compensation units required by the circuit, reduce the area of compensation components and crystal grains, and save costs. Another advantage of the utility model is that one input terminal of the feedforward amplifier is the sampling signal of the LDO power tube current, which forms a positive feedback loop in the circuit, which can speed up the response to changes in the load or power supply, greatly improving the LDO circuit. dynamic performance. The structure of this double-loop LDO can dynamically compensate the LDO circuit, so that the circuit can use a higher-gain error amplifier to obtain higher precision.

Description of drawings

FIG. 1 is a schematic diagram of a typical LDO voltage stabilizing circuit in the prior art;

Fig. 2 is the schematic diagram of the utility model dual-loop low-dropout linear regulator circuit;

FIG. 3 is a schematic diagram of a specific implementation circuit of the feedforward amplifier AMP2 in FIG. 2 .

Detailed ways

As shown in Figure 2, the utility model dual-loop low-dropout linear regulator circuit includes an error amplifier 1, a second-stage amplifier 2, a power tube 3, a compensation unit 4, an output sampling network 5, a load capacitor 6, a load circuit 7, a front Feed amplifier 8, pull-up drive tube 9, pull-down drive tube 10 and sampling tube 11. The above-mentioned parts constitute two loops, the main loop and the additional loop in the circuit. The main loop includes the error amplifier 1, the second amplifier 2, the pull-up drive tube 9, the power tube 3 and the output sampling network 5, forming a negative feedback The loop stabilizes the output voltage V _OUT . The additional loop includes a feed-forward amplifier 8, a sampling tube 11, a pull-down drive tube 10 and a power tube 3 to form a second loop, which refers to the output voltage to form a negative feedback loop and a dynamic compensation circuit to further stabilize the output voltage V _OUT ; With reference to the load current, a positive feedback loop is formed to accelerate the response to the load step change of the circuit. Each component will be described in detail below.

The negative input terminal of error amplifier 1 is connected to a reference voltage V _REF , which is generally generated by a bandgap circuit, has high precision stability, and does not change with changes in power supply or temperature; the positive input terminal is connected to the output sampling network generated Feedback voltage signal V _FB . The error amplifier 1 compares two input signals, amplifies the error signal of the two input signals, and then outputs it at a single end. The output terminal of the error amplifier 1 is connected to the input terminal of the amplifying circuit 2, and the output signal is input to the amplifying circuit 2 for next-stage amplification.

The output end of the amplifying circuit 2 is connected to the gate of the pull-up drive transistor 9 . In order to further amplify the error signal and reduce the steady-state error of the circuit, the amplifying circuit is often designed as an amplifying stage circuit with limited gain and high bandwidth. Therefore its frequency response has little effect on the overall frequency response of the regulator.

Power transistor 3 is usually a P-type or P-channel MOSFET, PMOS common-source stage, or its equivalent P-type or PNP transistor for bipolar processing technology, and now the trend is to use PMOS transistors to obtain the smallest Voltage drop, PMOS is used as the power tube in the circuit of the utility model, and its source terminal is connected to a power supply, generally provided by a battery; the output voltage of the drain terminal is connected to an external sampling network 5, a load capacitor 6, and a load circuit 7; its gates are respectively connected to pull-up The source end of the driving transistor 9 , the drain end of the pull-down driving transistor 10 , and the gate of the sampling transistor 11 . For convenience here, the grid potential of the power transistor 3 is referred to as PG.

The compensation unit 4 is connected to the connection between the output terminal of the error amplifier 1 and the input terminal of the amplifying circuit 2, and performs frequency compensation for the circuit. The utility model adopts the self-compensation mode of directly connecting the capacitor in parallel with the ground, and can obtain a more ideal compensation effect.

The output sampling network 5 includes two resistors R1 and R2. The upper end of R2 is connected to the output voltage V _OUT of the LDO circuit; the lower end is connected to the upper end of R1 to generate V _FB potential, which is input to the positive input end of the error amplifier; the lower end of R1 is directly grounded. The output sampling network divides the voltage through two resistors to sample the magnitude of the output voltage V _OUT . The selection of the two resistors can use separate components, or can be made directly inside the chip, and the resistor divider ratio can be adjusted through external control signals or EEPROM settings.

The upper end of the load capacitor 6 is connected to the output voltage V _OUT of the LDO circuit; the lower end is directly grounded. R _ESR is the equivalent series resistance of the capacitor parasitic. The load capacitor is used to help the LDO circuit stabilize the output, filter out high-frequency noise, and complete frequency compensation at the same time. The choice of the capacitor should not be too large, too large a capacitor will delay the dynamic response of the circuit, and it will take up too much area.

The load circuit 7 is the LDO circuit output voltage V _OUT to supply power to another circuit load, which is represented as a current load, that is, the load circuit 7 . The load circuit 7 is directly connected to V _OUT .

In the feedforward amplifier 8 in the additional loop, its negative input terminal is connected to the output voltage V _OUT of the LDO circuit; The feedforward amplifier 8 also generates an error signal output, which is connected to the gate of the pull-down tube 10 of the LDO gate drive circuit to form the second loop of the circuit, dynamically compensate the circuit, and improve the dynamic performance of the circuit at the same time.

The pull-up drive tube 9 is located in the main loop and is the pull-up network of the gate drive circuit of the LDO power tube 3. Its source is connected to the grid of the power tube 3; the grid is connected to the output of the amplifier circuit 2; the drain is connected to the power supply V _DD can also be directly connected to the LDO input power supply V _IN , or connected to a stable power supply, such as the substrate potential generated by the back gate control circuit of the power transistor of the LDO circuit.

The pull-down drive transistor 10 is located in the additional loop and is a pull-down network of the gate drive circuit of the LDO power transistor 3 . The drain of the pull-down drive transistor 10 is connected to the gate of the power transistor 3, the gate is connected to the output of the feedforward amplifier 8, and the drain is grounded.

The sampling tube 11 is connected in parallel with the LDO power tube 3, and their gates and sources are respectively connected, and have the same V _GS , which ensures that their current is proportional to the size of the device, and realizes the purpose of accurate sampling current; its drain is connected to a feedforward amplifier 8's non-inverting input.

Figure 3 depicts an exemplary circuit of the feed-forward amplifier AMP2 that constitutes the second loop in the dual-loop LDO circuit, which has the characteristics of a simple structure and dynamic compensation LDO circuit. The feedforward amplifier 8 includes first and second PMOS transistors 81 and 82 , first to third current source loads 83 , 84 and 85 , a common source amplifier transistor 86 and a feedforward amplifier output stage 87 . The main part of the feedforward amplifier 8 is a current mirror structure for comparison, and a common source amplifier tube 86 is connected to the output terminal for active negative feedback. The small-signal gain of such an amplifier is mainly determined by the common-source amplifier tube 86, which is a common-source amplifier gain stage. Its specific connection is that the gate of the first PMOS transistor 81 is connected to the drain, connected to the positive terminal of the first current source load 83, and then connected to the gate of the second PMOS transistor 82; the source of the first PMOS transistor 81 Connect to the output voltage V _OUT of the LDO. The source terminal of the second PMOS transistor 82 is connected to the drain end of the sampling tube 11, and is connected to the negative end of the third current source load 85 at the same time; end and the upper end of the resistor R of the output stage 87 of the feedforward amplifier. Both the negative terminals of the first and second current source loads 83 and 84 are grounded. The positive end of the third current source load 85 is connected to V _DD , which is the same as the power source connected to the drain end of the pull-up drive transistor 9 and can be directly connected to the LDO input voltage V _IN or the substrate potential of the LDO power transistor 3 . The third current source load 85 is the minimum branch current guarantee introduced to ensure that the feedforward amplifier circuit can still work normally under light load or no load. The feed-forward amplifier output stage 87 includes a resistor R3 and a MOS tube capacitor N1, which are connected to form a first-order low-pass filter network to filter out high-frequency disturbances generated when the amplifier responds to load step changes. Among them, the MOS capacitor N1 can be regarded as the grid as the upper plate, and the source and drain as the capacitance of the lower plate; the resistor R3 is connected to the drain of the second PMOS transistor 82 and the gate of the common source amplifier tube 86, and the second current source load The positive end of 84; the lower end of the resistor R3 outputs OUT2, and at the same time connects the gate of the MOS tube capacitor N1. The source and drain of the MOS tube capacitor N1 tube are directly grounded. The LDO circuit in the circuit shown in FIG. 3 is listed for the convenience of illustrating the connection of the sampling tube 11 .

In FIG. 2 , the working process of the feedforward amplifier 8 can be divided into two parts. One part assumes that the load current remains constant, and the feedforward amplifier responds to changes in the output voltage; the other part assumes that the output voltage remains constant, and the feedforward amplifier responds to changes in the load current. When the load current is constant, that is, the positive input terminal of the feedforward amplifier 8 can be regarded as a reference, the output voltage V _OUT changes (assuming that it becomes larger), the output of the feedforward amplifier 8 becomes lower, and the pull-down capability of the pull-down drive tube 10 decreases, and the power The gate potential of tube 3 rises, and the adjusted output V _OUT drops, forming a negative feedback loop to stabilize the output; when the output voltage V _OUT remains unchanged, that is, the negative input terminal of the amplifier can be regarded as a reference, and the load current I _LOAD changes (assuming that it needs to change large), the output of the amplifier becomes higher, the pull-down capability of the pull-down drive tube 10 is enhanced, the grid potential of the power tube 3 drops, and the adjusted output current I _LOAD increases to form a positive feedback loop and accelerate the dynamic response of the circuit. The above two parts are interlaced and mixed in practice and influence each other.

FIG. 1 of the prior art shows a typical frequency compensation technology of an LDO circuit, which uses a compensation unit 4 to complete the frequency compensation function together with a load capacitor 6 . In this typical prior art situation, the pole-zero points of the LDO circuit are as follows. The main pole PO is generated by the load capacitor 6 and the on-resistance of the LDO power transistor 3, and is given by the following formula:

$P_o=\frac{-1}{2\mathrm{\π}(R_{\mathrm{DS}}+R_{\mathrm{ESR}})C_L}\≈\frac{-1}{2{\mathrm{\πR}}_{\mathrm{DS}}{C}_L}$ Formula 1)

The pole between error amplifier 1 and the second stage amplifier is as follows:

$P_B=\frac{-1}{2{\mathrm{\πR}}_{\mathrm{EQ}}{C}_{\mathrm{EQ}}}$ Formula (2)

In the formula, R _EQ is the equivalent resistance to ground of the connection point between the two stages, which is generally the sum of the output resistance of the previous stage error amplifier 1 plus the input equivalent resistance of the second stage amplifier 2; C _EQ is the sum of the The equivalent capacitance of the node to ground is mainly the compensation capacitance plus the input capacitance of the second stage.

Usually the pole P _B will be relatively close to the main pole P _O , and compensation is required to offset the influence of the pole. Therefore, two zero points will be compensated in the circuit shown in Figure 1, which are:

$Z_B=\frac{-1}{2\mathrm{\&pi;}[(1/G_m)-R_B]C_B}\&ap;\frac{{-\mathrm{<figure-callout\; id="2"\; label="G\; m"\; filenames="Y20062016336000121.png,Y20062016336000131.png"\; state="\{\{state\}\}">G</figure-callout>}}_m}{2\mathrm{\&pi;}{C}_B}$ Formula (3)

$Z_{\mathrm{ESR}}\&ap;\frac{-1}{2{\mathrm{\&pi;R}}_{\mathrm{ESR}}{C}_L}$ Formula (4)

The zero point introduced by the compensation unit 4 is given by formula (3), where G _M is the equivalent transconductance of the second stage, and C _B is the capacitance used for compensation. The compensation zero associated with the load capacitance is given by Equation 4, where _CL is the load capacitance 6 and R _ESR is its series equivalent resistance.

The figure of this application is given by Figure 2, and the circuit in Figure 1 is called correspondingly; other identical structural units are marked sequentially. In the double-loop structure shown in Figure 2, two pathways, the fast and the slow, make a special contribution to the stability of the circuit. The first is the slow pathway with the same high gain as shown in Figure 1; the other is the low Gain fast path. Through the action of the fast and slow paths, a zero-point entry system is introduced, which is the basic principle of the double-loop structure compensation circuit in this application. The zero point of its compensation is calculated by the circuit shown in Figure 3.

${\mathrm{<figure-callout\; id="2"\; label="R\; AMP"\; filenames="Y20062016336000121.png,Y20062016336000131.png"\; state="\{\{state\}\}">R</figure-callout>}}_{\mathrm{AMP}}=\frac{R_{\mathrm{out},\mathrm{the\; <figure-callout\; id="1"\; label="loop"\; filenames="Y20062016336000121.png,Y20062016336000141.png"\; state="\{\{state\}\}">loop</figure-callout>}}}{1+A_{v,\mathrm{the\; loop}}}\&ap;\frac{1}{{\mathrm{<figure-callout\; id="86"\; label="g\; m"\; filenames="Y20062016336000141.png"\; state="\{\{state\}\}">g</figure-callout>}}_m}$ Formula (5)

$Z_{\mathrm{dual},\mathrm{the\; loop}}\&ap;\frac{-1}{2\mathrm{\&pi;}[{\mathrm{<figure-callout\; id="87"\; label="R"\; filenames="Y20062016336000141.png"\; state="\{\{state\}\}">R</figure-callout>}}_{87}+(1/g_{m86})]({\mathrm{<figure-callout\; id="87"\; label="C"\; filenames="Y20062016336000141.png"\; state="\{\{state\}\}">C</figure-callout>}}_{87}+C_{10})}$ Formula (6)

The output impedance of the feedforward amplifier 8 given by formula (5) is R _{AMP2, closed} , because 8 has a negative feedback loop inside, so its gain and output resistance are only determined by the common source amplifier tube 86 . The zero point of the double-loop structure compensation is given by formula (6), C ₈₇ is the MOS capacitor N1, and C ₁₀ is the gate input capacitance of the pull-down drive tube 10 controlled by the output of the feedforward amplifier 8 . In practice, a pair of zero-pole points should be introduced, but the zero point is closer to the coordinate origin than the pole point. By setting the zero point near the unity gain bandwidth, the pole point can be set outside the bandwidth range, so that the influence of the pole point on the circuit can be ignored.

Therefore, only the zero-point formula is given here. In addition, there is a g _m86 term in the zero point formula of formula (6), which is directly related to the load current sampled by the sampling tube 11, that is to say, the zero point Z _{dual and loop} compensated here is a dynamic compensation system. Usually, the loop frequency analysis of the LDO circuit with double-loop structure can be close to a single-pole stable system, and the phase margin is close to 90 degrees.

The implementation of the invention has been described here in the context of an exemplary embodiment. The illustrated embodiment provides an LDO circuit with a double-loop structure, which has two negative feedback loops, fast and slow. One is a high-gain error amplifier, which controls the power transistor gate to drive the pull-up network, and then controls the output to provide a stable voltage. The slow path; the other is a fast path that uses a lower-gain amplifier to compare the sampling signals of the output voltage and load current, and controls the gate drive pull-down network of the power transistor to stabilize the output. The response of these two fast and slow paths to small signals will introduce a zero point to perform frequency compensation on the system. Coupled with the other two compensations in the circuit, the frequency response of the circuit can be close to that of a single-pole system, and the circuit is excellently stabilized. At the same time, a positive feedback loop is formed through the additional second loop to respond to the step change of the load, which greatly improves the transient response of the circuit. At the same time, from a large signal point of view, when the load or power step changes, the output voltage will immediately have a negative jump. At this time, the fast path in the double-loop circuit first responds to the step change, and then the slow path also starts to adjust the circuit; when After a period of response, the adjustment effect of the fast path will decline, and the slow path will play a major role in regulation. Finally, the high gain of the slow path will realize the high precision of the circuit, that is, a very low steady-state error.

In the actual implementation circuit, the LDO circuit should also include protection units and interface components, such as over-temperature protection, short-circuit current limit and other protection units.

These examples are intended to be illustrative, not limiting. Many variations, modifications, additions and improvements are possible.

Claims (2)

1, a kind of double ring low differential voltage linear voltage stabilizer circuit comprises error amplifier (1), second level amplifier (2), power tube (3), compensating unit (4), output sampling network (5), load capacitance (6) and load circuit (7);

The negative input of error amplifier (1) meets reference voltage V _REF, positive input meets the feedback voltage signal V that the output sampling network produces _FBError amplifier (1) is two input signals relatively, the error signal of two input signals is amplified the single-ended output in back, and the output terminal of error amplifier (1) is connected with the input end of amplifying circuit (2), output signal is input to amplifying circuit (2) carries out the next stage amplification;

Compensating unit (4) is connected error amplifier (1) output terminal and amplifying circuit (2) input end junction, and circuit is carried out frequency compensation;

Output sampling network (5) comprises the resistance R 1 and the R2 of series connection, the output voltage V of the last termination LDO circuit of R2 _OUT, the upper end of lower end and R1 links to each other, and produces V _FBCurrent potential is input to the normal phase input end of error amplifier; The lower end ground connection of R1;

Load capacitance (6) goes up termination LDO circuit output voltage V _OUTThe direct ground connection in lower end;

Load circuit (7) connects the output voltage V of LDO circuit _OUT

It is characterized in that:

This circuit also comprise feed-forward amplifier (8), on draw driving tube (9), drop-down driving tube (10) and sampling pipe (11);

The negative input of feed-forward amplifier (8) connects the output voltage V of LDO circuit _OUTPositive input connects the drain terminal of sampling pipe (11), and its output terminal joins with the grid of following trombone slide (10);

On draw the source electrode of driving tube (9) to connect the grid of power tube (3), its grid connects the output of amplifying circuit (2), its drain electrode meets LDO input power supply V _INOr the substrate electric potential of LDO power tube (3);

The drain electrode of drop-down driving tube (10) connects the grid of power tube (3), and its grid connects the output of feed-forward amplifier (8), its source end ground connection;

Sampling pipe (11) is in parallel with power tube (3), and the grid of the two, source electrode join respectively, and the drain electrode of sampling pipe (11) connects the normal phase input end of feed-forward amplifier (8);

Error amplifier (1), second amplifier (2), on draw driving tube (9), power tube (3) and output sampling network (5) to constitute major loop, form negative feedback loop regulated output voltage V _OUTFeed-forward amplifier (8), sampling pipe (11), drop-down driving tube (10) and power tube (3) constitute additional loop, and this loop forms negative feedback loop with reference to output voltage, dynamics compensation circuits, further regulated output voltage V _OUT, and, forming positive feedback loop with reference to load current, the load current step of booster response circuit changes.

2, double ring low differential voltage linear voltage stabilizer circuit according to claim 1 is characterized in that: feed-forward amplifier (8) comprises first, second PMOS pipe (81,82), first to the 3rd current source load (83,84 and 85), common source amplifier tube (86) and feed-forward amplifier output stage (87);

The grid and the drain electrode of the one PMOS pipe (81) are joined, and are connected with the anode of first current source load (83) and the grid of the 2nd PMOS pipe (82) respectively again, and the source electrode of PMOS pipe (81) connects the output voltage V of LDO _OUT

The source end of the 2nd PMOS pipe (82) is connected with the drain terminal of sampling pipe (11) and the negative terminal of the 3rd current source load (85) respectively, its drain terminal links to each other with the grid of common source amplifier tube (86), and is connected with the anode of second current source load (84) and the upper end of the resistance R 3 of feed-forward amplifier output stage (87);

The equal ground connection of negative terminal of first, second current source load (83,84), the positive termination LDO input power supply V of the 3rd current source load (85) _INOr the substrate electric potential of LDO power tube (3);

Feed-forward amplifier output stage (87) comprises resistance R 3 and metal-oxide-semiconductor electric capacity N1, and mos capacitance N1 is to be top crown with the grid, and source, leakage link to each other as the electric capacity of bottom crown; The drain electrode of termination the 2nd PMOS pipe (82) and the grid of common source amplifier tube (86) on the resistance R 3, and the anode of second current source load (84); The lower end of resistance R 3 connects the grid of metal-oxide-semiconductor electric capacity N1 pipe simultaneously as output, and ground is missed in the source of metal-oxide-semiconductor electric capacity N1.

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