CN1928984A - Shift register array and its layout for a display device - Google Patents

Abstract

The invention relates to a shift register array for a display device and a layout mode thereof. The shift register array comprises a plurality of shift registers connected in series, wherein each shift register is provided with a first clock input end, a second clock input end and a first clock bus. The first clock input terminal of a specific shift register in the shift registers is connected to the first clock bus, and the second clock input terminal of a next-stage shift register in the specific shift register is connected to the first clock input terminal of the specific shift register.

Description

Shift register array and its layout for a display device

technical field

The invention relates to a shift register array and its layout method for a display device, in particular to a shift register array and its layout method which can save the layout area.

Background technique

The thin film transistor liquid crystal display is composed of a pixel array, and the pixel array includes many pixels, and each pixel includes at least one thin film transistor to control the light emission of the pixel. To drive a thin film transistor, a control signal needs to be applied to the gate and source of the thin film transistor. Generally speaking, the control signal needs to be temporarily stored by a shift register circuit, and then applied to the gate of the thin film transistor at an appropriate time. pole and source.

An existing shift register circuit contains four inputs and one output. The input terminal includes a voltage input terminal, a start signal terminal, a first clock input terminal and a second clock input terminal. The voltage input terminal receives a DC reference voltage (VSS), the start signal terminal receives a start pulse (ST), the first clock input terminal and the second clock input terminal respectively receive a clock signal (CK) and an inversion Clock signal (XCK). The output terminal outputs a square wave signal. ST is used to trigger the shift register circuit action. In addition to being electrically connected to the thin film transistor to control the light emission of the pixel, the output signal can also be used as the ST of the next-stage shift register.

In a thin film transistor liquid crystal display, the operation of the shift register must generally comply with the following rules: the first clock input terminal of the previous stage shift register circuit and the first clock input terminal of the subsequent stage shift register circuit must respectively receive CK And XCK, which means that if the first clock input terminal of the shift register circuit of the previous stage receives CK, the first clock input terminal of the shift register circuit of the subsequent stage receives XCK, and the second clock of the shift register circuit of the previous stage The input end receives XCK, and the second clock input end of the shift register circuit of the latter stage receives CK.

Due to the above-mentioned rules, the cross-line generated in the layout (layout) will generate parasitic effects in the cross-line area, such as parasitic capacitance, and affect signal transmission. At the same time, the layout of the shift register circuit must be as compact as possible, so that the design margin of the entire panel can be improved, and the cost of the area occupied by the layout can be reduced.

FIG. 1 shows an existing shift register circuit layout, wherein each shift register circuit must be connected to a bus 11 to receive signals through three signal lines. The bus 11 includes a VSS line 111, a CK line 112 and an XCK line. 113. Taking the shift register circuit 101 as an example, it includes a voltage input terminal 1011 , a first clock input terminal 1012 , a second clock input terminal 1013 , a start signal terminal 1014 and an output terminal 1015 . The voltage input terminal 1011 is connected to the VSS line 111, the first clock input terminal 1012 is connected to the CK line 112, the second clock input terminal 1013 is connected to the XCK line 113, the start signal terminal 1014 receives a ST 114, and the output terminal 1015 outputs Square wave 115. Similarly, the voltage input terminal 1021 of the shift register 102 is connected to the VSS line 111, the first clock input terminal 1022 is connected to the CK line 112, the second clock input terminal 1023 is connected to the XCK line 113, and the start signal terminal 1024 is connected to the output terminal 1015, and the output terminal 1025 outputs a square wave 125.

As can be seen from FIG. 1, the layout of each shift register circuit needs to reserve enough space for the bus 11, and when each shift register circuit is connected to the bus 11, multiple coupling points will be formed on the bus 11. Each coupling point means that a parasitic capacitance will be generated, which will affect the transmission of the signal to the shift register.

Therefore, a layout of a shift register circuit with reduced layout space and reduced parasitic effects is desired in the industry.

Contents of the invention

The object of the present invention is to provide a shift register array (shift register), including a plurality of shift registers connected in series and a first clock bus. Among the serial shift registers, each shift register has a first clock input terminal and a second clock input terminal. The first clock input terminal of a specific shift register among the shift registers is connected to the first clock bus, and the second clock input terminal of the next-stage shift register of the specific shift register is connected to the specific The first clock input of the shift register.

Another object of the present invention is to provide a display device, which includes a pixel array, a plurality of serial shift registers, and a first clock bus. Among the serial shift registers, each shift register is used to drive a pixel of the pixel array, and has a first clock input terminal and a second clock input terminal. The first clock input terminal of a specific shift register among the shift registers is connected to the first clock bus, and the second clock input terminal of the next-stage shift register of the specific shift register is connected to the specific The first clock input of the shift register.

Another object of the present invention is to provide a wiring method for a shift register array, the shift register array includes a plurality of series shift registers and a first clock bus, each shift register has a first clock input terminal and a second clock input terminal, the method comprises the steps of: connecting the first clock input terminal of a specific shift register in the shift registers to the first clock bus; and connecting the specific shift register The second clock input terminal of the next stage shift register to the first clock input terminal of the specific shift register.

The present invention has the advantages of reducing the layout space and reducing the parasitic effect of the shift register circuit layout.

After referring to the drawings and the implementation methods described later, those skilled in the art can understand other objectives of the present invention, as well as the technical means and implementation aspects of the present invention.

Description of drawings

Fig. 1 is existing shift register circuit layout;

Fig. 2 is the first embodiment of the present invention;

Fig. 3 is the second embodiment of the present invention;

Figure 4 is a third embodiment of the present invention; and

Fig. 5 is a fourth embodiment of the present invention.

Description of reference symbols

201 shift register 202 shift register

2011 voltage input terminal 2012 first clock input terminal

2013 second clock input terminal 2014 start signal terminal

2015 Output Terminal 2021 Voltage Input Terminal

2022 first clock input terminal 2023 second clock input terminal

2024 start signal terminal 2025 output terminal

211 VSS line 212 CK line

213 XCK line

301 shift register 302 shift register

3011 voltage input terminal 3012 first clock input terminal

3013 second clock input terminal 3014 start signal terminal

3015 output terminal 3021 voltage input terminal

3022 first clock input terminal 3023 second clock input terminal

3024 start signal terminal 3025 output terminal

311 VSS line 312 CK line

313 XCK line

501 shift register 502 shift register

503 shift register 504 shift register

Detailed ways

FIG. 2 depicts a first embodiment of using the present invention to lay out an array of shift registers. This embodiment may be combined with an array of pixels included in a display device such as a TFT-LCD. As shown in Figure 2, the specific shift register in this shift register array is a shift register 201, and this shift register 201 comprises a voltage input end 2011, a first clock input end 2012, a second clock input end 2013 , a start signal terminal 2014 and an output terminal 2015 . The voltage input terminal 2011 is connected to a VSS line 211, the first clock input terminal 2012 is connected to a CK line 212, the second clock input terminal 2013 is connected to an XCK line 213, and the start signal terminal 2014 receives a ST 214 , the output terminal 2015 outputs a square wave 215 .

The next-stage shift register 202 of the shift register 201 also includes a voltage input terminal 2021 , a first clock input terminal 2022 , a second clock input terminal 2023 , a start signal terminal 2024 and an output terminal 2025 . The voltage input terminal 2021 is connected to the VSS line 211, the first clock input terminal 2022 is connected to the XCK line 213, the second clock input terminal 2023 is connected to the first clock input terminal 2012 of the shift register 201, the The start signal terminal 2024 receives the square wave 215 generated by the shift register 201 , and the output terminal 2025 outputs the square wave 225 .

The other shift registers included in the shift register array of the first embodiment are interconnected in series according to the above layout rules. If the number of shift registers included in the shift register array is an odd number, the farthest shift register 201 Shift register, that is, the last shift register of the shift register array, its first clock input terminal is connected to CK line 212; if the number of shift registers included in the shift register array is an even number, the shift register is 201 The farthest shift register, ie the last shift register of the array of shift registers, has its first clock input connected to the XCK line 213 .

In this embodiment, the number of coupling points generated when the shift register is connected to the bus can be reduced by laying out the circuit connection in the middle part of the shift register array. As can be seen from FIG. 2, when every two adjacent shift registers are connected to the bus , resulting in only five coupling points in total.

FIG. 3 depicts a second embodiment of using the present invention to lay out a shift register array. This embodiment can be combined with a pixel array included in a display device such as a thin film transistor liquid crystal display. As shown in Figure 3, the specific shift register in this shift register array is a shift register 301, and this shift register 301 comprises a voltage input end 3011, a first clock input end 3012, a second clock input end 3013 , a start signal terminal 3014 and an output terminal 3015 . The voltage input terminal 3011 is connected to a VSS line 311, the first clock input terminal 3012 is connected to a CK line 312, the second clock input terminal 3013 is connected to a XCK line 313, and the start signal terminal 3014 receives a ST 314 , the output terminal 3015 outputs a square wave 315 .

The next-stage shift register 302 of the shift register 301 includes a voltage input terminal 3021 , a first clock input terminal 3022 , a second clock input terminal 3023 , a start signal terminal 3024 and an output terminal 3025 . The voltage input 3021 is connected to the VSS line 211, the first clock input 3022 is connected to the second clock input 3013 of the shift register 301, and the second clock input 3023 is connected to the shift register 301. The first clock input terminal 3012 and the start signal terminal 3024 receive the square wave 315 generated by the shift register 301 , and the output terminal 3025 outputs a square wave 325 .

The other shift registers of the second embodiment are interconnected in series according to the above-mentioned layout rules. As can be seen from FIG. The shift register only generates a coupling point in its middle part, which also reduces the influence of the parasitic capacitance generated by the coupling point on signal transmission.

FIG. 4 depicts a third embodiment of using the present invention to lay out a shift register array. This embodiment can be combined with a pixel array included in a display device such as a TFT-LCD. Except for the last shift register, the circuit layout of the third embodiment is substantially the same as that of the second embodiment, and will not be repeated here. The difference is that the last shift register of the third embodiment is connected to the CK line 312 and the XCK line 313. If the number of shift registers included in the shift register array is an odd number, the first clock of the last shift register The input end is connected to the CK line 312, and the second clock input end is connected to the XCK line 313; if the number of shift registers included in the shift register array is even, the first clock input end of the last shift register is connected to XCK Line 313 , the second clock input terminal is connected to CK line 312 . It can be seen from FIG. 4 that in this embodiment, the first and last shift registers of the shift register array are respectively connected to the CK line and the XCK line, so as to reduce the delay effect caused by the line transmission when CK and XCK are transmitted in the shift register array.

Figure 5 depicts a fourth embodiment using the present invention to lay out a shift register array, which includes all the circuit layouts of the third embodiment, this embodiment can be combined with a pixel array, included in a display device, such as a thin film transistor liquid crystal monitor. The fourth embodiment further includes connecting the first clock input terminals of every other shift register starting from the shift register 501 to the CK line 312 , such as the shift register 503 . Simultaneously connect the first clock input of every other shift register starting from shift register 502 , such as shift register 504 , to XCK line 313 .

The fifth embodiment of the present invention is a wiring method for a shift register array. The shift register included in the shift register array includes a voltage input terminal, a first clock input terminal, a second clock input terminal, a starting a signal terminal and an output terminal. The method comprises the steps of: connecting the voltage input terminal of a specific shift register to a VSS line; connecting the first clock input terminal of the specific shift register to a CK line; connecting the second clock input terminal of the specific shift register Clock input terminal to an XCK line; receive an ST at the start signal terminal of the specific shift register; connect the output terminal of the specific shift register to the start signal terminal of the next-stage shift register; connect the next Connect the voltage input end of the first stage shift register to the VSS line; connect the first clock input end of the next stage shift register to the XCK line, connect the second clock input end of the second stage shift register to the shift The first clock input end of the bit register is connected to the output end of the second-stage shift register to the start signal end of the second-stage shift register.

The fifth embodiment can further complete all wiring connections included in the first embodiment. The order of the steps described in this embodiment is only for illustration, and is not intended to limit the present invention.

The sixth embodiment of the present invention is a wiring method for a shift register array. The shift register included in the shift register array includes a voltage input terminal, a first clock input terminal, a second clock input terminal, a starting a signal terminal and an output terminal. The method comprises the steps of: connecting the first clock input of a specific shift register to a CK line; connecting the second clock input of the specific shift register to an XCK line; connecting the second clock input of the specific shift register The first clock input end of the first-stage shift register is connected to the second clock input end of the specific shift register, and the second clock input end of the second-stage shift register is connected to the second clock input end of the specific shift register. A clock input. The sixth embodiment can further complete all the wiring connections included in the second embodiment. The order of the steps described in this embodiment is only for illustration, and is not intended to limit the present invention.

The seventh embodiment of the present invention is a wiring method for a shift register array. The seventh embodiment is substantially the same as the sixth embodiment, and will not be repeated here. The difference is that the seventh embodiment includes a step to connect the last shift register to the CK line and the XCK line. If the number of shift registers included in the shift register array is odd, connect the first clock input end of the last shift register to the CK line, and connect the second clock input end to the XCK line; if the shift register If the number of shift registers included in the array is even, the first clock input end of the last shift register is connected to the XCK line, and the second clock input end is connected to the CK line. The seventh embodiment can further complete all the wiring connections included in the third embodiment. The order of the steps described in this embodiment is only for illustration, and is not intended to limit the present invention.

The eighth embodiment of the present invention is a wiring method for a shift register array, which includes all the steps of the seventh embodiment, and further includes the following steps: counting from the first shift register in the shift register array, connecting The first clock input end of every alternate shift register is connected to the CK line; counting from the second shift register, the first clock input end of every alternate shift register is connected to the XCK line. The eighth embodiment can further complete all the wiring connections included in the fourth embodiment. The order of the steps described in this embodiment is only for illustration, and is not intended to limit the present invention.

The above-mentioned embodiments are only used to illustrate the implementation of the present invention and explain the technical features of the present invention, and are not intended to limit the scope of the present invention. Any changes or equivalent arrangements that can be easily accomplished by those skilled in the art fall within the scope of the present invention, and the scope of rights of the present invention should be based on the scope of the patent application.

Claims (24)

1. shift register array comprises:

A plurality of serial shift registers, each shift register have one first input end of clock and a second clock input end; And

One first clock bus;

Wherein, this first input end of clock of a specific shift register in those shift registers is connected to this first clock bus, and this second clock input end of the inferior one-level shift register of this specific shift register is connected to this first input end of clock of this specific shift register.

2. shift register array as claimed in claim 1 wherein, is connected to this first clock bus every this first input end of clock of the shift register of fixed number.

3. shift register array as claimed in claim 1, wherein, one of them is connected to this first clock bus this first input end of clock of the shift register of this specific shift register distal-most end of distance and this second clock input end.

4. shift register array as claimed in claim 1, more comprise a second clock bus, the clock signal of this second clock bus and this first clock bus is anti-phase, and wherein, this second clock input end of this specific shift register is connected to this second clock bus.

5. shift register array as claimed in claim 4, this first input end of clock of the inferior one-level shift register of this specific shift register is connected to this second clock input end of this specific shift register.

6. shift register array as claimed in claim 4, this first input end of clock of the inferior one-level shift register of this specific shift register is connected to this second clock bus.

7. shift register array as claimed in claim 4 wherein, is connected to this second clock bus every this second clock input end of the shift register of fixed number.

8. shift register array as claimed in claim 4, wherein, one of them is connected to this second clock bus this first input end of clock of the shift register of this specific shift register distal-most end of distance and this second clock input end.

9. display device comprises:

One pel array;

A plurality of serial shift registers, each shift register are in order to driving a pixel of this pel array, and have one first input end of clock and a second clock input end; And

One first clock bus;

Wherein, this first input end of clock of a specific shift register in those shift registers is connected to this first clock bus, and this second clock input end of the inferior one-level shift register of this specific shift register is connected to this first input end of clock of this specific shift register.

10. display device as claimed in claim 9 wherein, is connected to this first clock bus every this first input end of clock of the shift register of fixed number.

11. display device as claimed in claim 9, wherein, one of them is connected to this first clock bus this first input end of clock of the shift register of this specific shift register distal-most end of distance and this second clock input end.

12. display device as claimed in claim 9 more comprises a second clock bus, the clock signal of this second clock bus and this first clock bus is anti-phase, and wherein, this second clock input end of this specific shift register is connected to this second clock bus.

13. display device as claimed in claim 12, this first input end of clock of the inferior one-level shift register of this specific shift register is connected to this second clock input end of this specific shift register.

14. display device as claimed in claim 12, this first input end of clock of the inferior one-level shift register of this specific shift register is connected to this second clock bus.

15. display device as claimed in claim 12 wherein, is connected to this second clock bus every this second clock input end of the shift register of fixed number.

16. display device as claimed in claim 12, wherein, one of them is connected to this second clock bus this first input end of clock of the shift register of this specific shift register distal-most end of distance and this second clock input end.

17. wiring method that is used for a shift register array, this shift register array comprises a plurality of serial shift registers and one first clock bus, each shift register has one first input end of clock and a second clock input end, and this method comprises the following step:

This first input end of clock that connects the specific shift register in those shift registers is to this first clock bus; And

This second clock input end of inferior one-level shift register that connects this specific shift register is to this first input end of clock of this specific shift register.

18. wiring method as claimed in claim 17 more comprises:

Connection every this first input end of clock of the shift register of fixed number to this first clock bus.

19. wiring method as claimed in claim 17 more comprises:

Connect this first input end of clock of shift register of this specific shift register distal-most end of distance and this second clock input end one of them to this first clock bus.

20. wiring method as claimed in claim 17, this shift register array more comprise a second clock bus, the clock signal of this second clock bus and this first clock bus is anti-phase, and this method more comprises:

This second clock input end that connects this specific shift register is to this second clock bus.

21. wiring method as claimed in claim 20 more comprises:

This first input end of clock of inferior one-level shift register that connects this specific shift register is to this second clock input end of this specific shift register.

22. wiring method as claimed in claim 20 more comprises:

This first input end of clock of inferior one-level shift register that connects this specific shift register is to this second clock bus.

23. wiring method as claimed in claim 20 more comprises:

Connection every this second clock input end of the shift register of fixed number to this second clock bus.

24. wiring method as claimed in claim 20 more comprises:

One of them is connected to this second clock bus this first input end of clock of the shift register of this specific shift register distal-most end of connection distance and this second clock input end.

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