CN1235182C - integrated circuit that eliminates the accumulation of duty cycle errors - Google Patents

Abstract

An integrated circuit comprising a first signal inversion switch circuit which receives a signal supplied from the outside as a first input signal, then outputs the first input signal after logically inverting the input signal in response to a first state of a switch signal, and directly outputs the first input signal without logically inverting it in response to a second state of the switch signal; a signal processing circuit that performs signal processing in accordance with an output of the first signal inverting switch circuit; and a second signal inversion switching circuit that receives an output of the first inversion switching circuit through the signal processing circuit as a second input signal, then outputs the second input signal after logically inverting the input signal in response to a second state of the switching signal, and directly outputs the second input signal without logically inverting it in response to the first state of the switching signal.

Description

integrated circuit that eliminates the accumulation of duty cycle errors

technical field

The present invention generally relates to an integrated circuit usable as a driving IC for driving a liquid crystal display panel, and more particularly to an LCD data driver for driving a data bus of a liquid crystal display panel according to display data.

Background technique

The liquid crystal display panel has pixels constituted by transistors arranged in a matrix form, has a gate bus line extending horizontally connected to the gates of the pixel transistors, and a data bus line extending vertically through the transistors connected to pixel capacitors. When data is to be displayed on the liquid crystal display panel, the gate driver sequentially drives the gate bus line one by one so that the transistors on the selected horizontal line are turned on. The data driver writes data into the pixels on the selected horizontal line through the turned-on transistors.

In a conventional structure, generally LCD data drivers are commonly connected to a bus for transmitting display data signals, clock signals, and the like. In this case, the signal lines cross each other, resulting in the provision of a large number of layers in one substrate used. In order to reduce the number of layers of the substrate, LCD data drivers may be cascaded so that the data output of a given LCD driver is provided to the next LCD data driver located at the next stage.

This cascaded structure can reduce the number of substrate levels since the LCD drivers are connected in series without crossing each other between the used signal lines. This provides the basis for manufacturing the substrate at low cost.

With LCD data drivers arranged in cascade, a signal input to a given driver device causes that signal to be provided to the next driver device through an output buffer. Due to variations in the manufacturing process that cause positive and negative transitions of the signal to have different delays in the buffer, the output signal will have a slightly different duty cycle than the input signal.

When LCD data drivers with similar delay characteristics are cascaded, this duty cycle error will be accumulated each time a signal passes through one LCD data driver. After passing through a large number of drivers, this duty cycle error will reach a level that cannot be ignored. For example, in an SXGA type LCD panel, 10 LCD data drivers are cascaded, so that accumulated errors in duty cycles may cause signals not to be transmitted correctly.

Accordingly, there is a need for an LCD data driver free from duty cycle errors, and a liquid crystal display device using such an LCD data driver.

Contents of the invention

A general object of the present invention is to provide an integrated circuit that can be used as an LCD data driver, and a liquid crystal display device using such an LCD data driver, which substantially avoids one or more of the limitations and disadvantages of the prior art. question.

The features and advantages of the present invention will be given in the following description, and will become more apparent from the description and drawings, or can be obtained by practicing the present invention according to the ideas provided in the specification. By using such complete, clear, concise and precise terms in the specification to specifically point out the LCD data driver, those skilled in the art can realize and obtain the objects and other features and advantages of the present invention.

To achieve these and other advantages, and in accordance with the objects of the invention embodied and broadly described herein, the invention provides an integrated circuit including a first signal inverting switch circuit which receives an externally supplied signal as a first input signal, and then output the first input signal after logically inverting the input signal in response to the first state of the switching signal, and directly output the first input signal without logically inverting it in response to the second state of the switching signal a signal processing circuit that performs signal processing based on the output of the first signal inverting switch circuit; and a second signal inverting switch circuit that receives the output of the first signal inverting switch circuit through the signal processing circuit as a second input signal , and then outputting the second input signal after logically inverting the input signal in response to the second state of the switch signal, and directly outputting the second input signal without logically inverting it in response to the first state of the switch signal Mutually.

In the LCD data driver having the circuit structure of the above integrated circuit, the logic of the output signal is inverted with respect to the logic of the input signal, thereby canceling the delay caused by the timing difference between the delay of the transition of the positive signal and the delay of the transition of the negative signal. resulting in duty cycle errors. Even when the data driver ICs are arranged in multi-stage cascade, accumulation of duty cycle errors due to signal transmission can be avoided. This logic inversion responds to the switching signal, the signal stage before the internal signal processing or the signal stage after the internal signal processing is selectively implemented, thereby ensuring that the signal with regular logic is provided for use by the internal signal processing .

In addition, the liquid crystal display device according to the present invention includes: a liquid crystal display panel; a gate driver, which drives the gate bus of the liquid crystal display panel; and a plurality of data drivers, which are arranged in cascade and drive the liquid crystal display panel. A data bus of the panel, wherein each of the data drivers receives a signal supplied from a previous stage, and transmits the signal to a subsequent stage after logically inverting it.

Also, a signal transmission system including: a plurality of integrated circuits arranged in cascade, wherein each of said integrated circuits receives a signal supplied from a previous stage, and after logically inverting it, transmits the signal to Poweramp.

In the above-mentioned liquid crystal display device and signal transmission system, the logic of the output signal is inverted with respect to the logic of the input signal, thereby eliminating the timing difference caused by the delay between the transition delay of the positive signal and the delay of the transition of the negative signal. duty cycle error. Even when used to provide a multi-stage circuit, accumulation of duty cycle errors due to signal layer transmission can be avoided.

Other objects and features of the present invention will become more apparent from the following detailed description in conjunction with the accompanying drawings.

Description of drawings

1 is a schematic view showing an example of the structure of a liquid crystal display device to which the present invention is applied;

FIG. 2 is a circuit diagram showing an example of the structure of a data driver IC;

3A and 3B are schematic diagrams of signal inversion processing for illustrating the difference between even-numbered positions and odd-numbered positions;

4A and 4B are schematic diagrams showing duty cycle errors observed when a clock signal is transmitted through multi-stage cascaded data driver ICs;

5 is a circuit diagram showing an example of another structure of a data driver IC;

6 is a circuit diagram showing one embodiment of a signal inversion switch circuit according to the present invention; and

FIG. 7 is a circuit diagram showing another embodiment of a signal inversion switch circuit according to the present invention.

Detailed ways

Hereinafter, embodiments of the present invention are described with reference to the accompanying drawings.

FIG. 1 is a schematic diagram showing an example of the structure of a liquid crystal display device to which the present invention is applied.

The liquid crystal display device of FIG. 1 includes a cascaded LCD panel 10 , a control circuit 11 , a gate driver 12 , and a plurality of data driver ICs 13 .

The LCD panel 10 includes pixels constituted by transistors (not shown) arranged in a matrix form, a gate bus line extends from the gate driver 12 in the horizontal direction and is connected to the gates of the pixel transistors, and a data bus line runs from the data driver IC 13 at extends vertically and connects to the pixel capacitor through a transistor. When data is displayed on the LCD panel 10, the gate driver 12 sequentially drives the gate bus lines one by one to turn on transistors on selected horizontal lines. The data driver IC 13 writes data into the pixels on the selected horizontal line through the turned-on transistors.

The control circuit 11 controls the gate driver 12 and the data driver IC 13 to display data on the LCD panel 10 . The control circuit 11 supplies clock signals, data signals, and various control signals to the data driver IC 13 , and supplies the clock signal and various control signals to the gate driver 12 .

In the liquid crystal display device according to the present invention, data driver ICs 13 are cascaded as shown in FIG. 1 . The signal supplied to the first data driver IC 13 is then transferred to the next data driver IC 13 through the first data driver IC 13 . Then, the signal is sequentially supplied from the data driver IC 13 at a given circuit stage to the data driver IC 13 at the next stage.

In the present invention, each data driver IC 13 is configured to invert the logic level of this signal. In FIG. 1 , the manner in which the signal logic is inverted is shown on the upper part of the signal line 15 connected between the data driver ICs 13 . In this manner, each data driver IC 13 logically inverts the signal, thereby canceling the duty cycle error due to the delay difference between the positive transition of the signal and the negative transition of the signal. Accordingly, even when the data driver ICs 13 are arranged to form a multi-stage cascade, accumulation of duty cycle errors caused by signal transmission can be eliminated.

FIG. 2 shows an example of the structure of the data driver IC 13 .

The data driver IC 13 of FIG. 2 includes input buffers 21 to 23, a signal inversion switch circuit 24, a clock control circuit 25, a data control circuit 26, an inverter 27, a signal inversion switch circuit 28, output buffers 29 and 30, and the core circuit 31 .

The structure shown in the example of FIG. 2 only inverts the logic of the clock signal CLK. One of the signal inversion switch circuit 24 or the signal inversion switch circuit 28 inverts the clock signal CLK. Which one of the signal inversion switch circuit 24 and the signal inversion switch circuit 28 is used to perform inversion processing is determined by an even/odd switch signal. Of the data driver ICs 13 connected in cascade, the odd data driver IC 13 gives a low level even/odd switching signal, for example, and the even data driver IC 13 gives a power supply potential VDD from the substrate, for example. As shown in FIG. 1 , a ground potential GND is supplied from the substrate to the odd data driver IC 13 as an even-odd switching signal, and a power supply potential VDD is supplied from the substrate to the odd data driver IC 13 .

When the input clock signal CLKin is expressed as a logic inverted from the normal logic, the signal inversion switch circuit 24 inverts the logic, thereby providing the clock signal CLK with normal logic for use in the clock control circuit 25 . There is no logic inversion at the signal inversion switch circuit 28 so that the output clock signal CLKout supplied to the subsequent stage has a logic inversion of the logic of the input clock signal CLKin.

When the input clock signal CLKin has normal logic, the signal inversion switch circuit 24 does not invert the logic, thereby providing the clock signal CLK with normal logic for use in the clock control circuit 25 . In this case, the signal inversion switch circuit 28 inverts the logic so that the clock signal CLKout output to the next stage has a logic inverting the logic of the input clock signal CLKin.

Hereinafter, the operation of the data driver IC 13 will be described in detail.

The input buffer 21 receives the clock signal CLKin from the previous-stage data driver IC 13 . If the data driver IC 13 is the first driver in the cascade, the clock signal CLKin is supplied from the control circuit 11 of FIG. 1 . The input buffer 21 supplies the clock signal CLK to the signal inversion switch circuit 24 . The signal inversion switch circuit 24 further receives the even/odd switch signal through the input buffer 23 .

The signal inversion switch circuit 24 includes an inverter 41 and a switch 42, and switches the connection of the switch 42 in response to the even/odd switch signal to select the clock signal CLK or the inversion of the clock signal CLK output from the inverter 41. Signal. The selected signal is supplied to the clock control circuit 25 . According to the received clock signal CLK, the clock control circuit 25 generates a timing control signal for providing to the data control circuit 26 and the core circuit 31 .

As shown in FIG. 1 , the input buffer 22 receives the data signal DATAin from the control circuit 11 or the data driver IC 13 of the preceding stage, and supplies the data signal DATA to the data control circuit 26 . In response to a control signal from the clock control circuit 25, the data control circuit 26 stores the data signal DATA sequentially supplied from the input buffer 22 in an internal resistor. In this way, the internal resistors of the data driver IC 13 store a portion of the horizontal period of display data corresponding to the display area covered by the data driver IC 13 .

The display data stored in the data control circuit 26 is supplied to the core circuit 31 . The core circuit 31 includes a latch circuit, gradation potential generation circuit, output buffer circuit and the like. The core circuit 31 operates according to the timing control signal from the clock control circuit 25, and when receiving the display data from the data control circuit 26, latches the display data in the latch circuit. The display data stored in the latch circuit is supplied to the gradation potential generation circuit. The gradation potential generation circuit is provided with a digital-to-analog conversion circuit for each data line, which converts received display data from digital to analog, thereby outputting an analog grayscale signal. The output buffer circuit receives the analog grayscale signal from the gradation potential generating circuit through each data line, and outputs the received analog grayscale signal to the LCD panel 10 as a driving signal for driving the data line.

The clock control circuit 25 receives the clock signal CLK or the inversion signal from the signal inversion switch circuit 24 and supplies this signal to the signal inversion switch circuit 28 as it is. The signal inversion switch circuit 28 further receives an inversion signal of the even/odd switch signal passed through the input buffer 23 and the inverter 27 . The signal inversion switch circuit 28 includes an inverter 43 and a switch 44, and switches the connection of the switch 44 in response to the inversion of the even/odd switch signal to select the output of the clock control circuit 25 or the inversion of the output of the clock control circuit 25 Signal. The selected signal is then provided to output buffer 29 . The output buffer 29 supplies the received signal to the data driver IC 13 at the subsequent stage as a clock signal CLKout.

The data signal DATA passed through the data control circuit 26 is output from the output buffer 30 as the data signal DATAout to the data driver IC 13 at the subsequent stage.

3A and 3B are schematic views of signal inversion processing for explaining the difference between even positions and odd positions.

FIG. 3A shows signal propagation paths provided in the data driver ICs 13 located in odd stages. FIG. 3B shows signal propagation paths provided in the data driver ICs 13 located in even stages. In FIG. 3 , only signal propagation paths for clock signals are shown, and circuits related to data signals are omitted.

In the data driver IC 13 provided in odd stages, the input signal has normal logic. Therefore, as shown in FIG. 3A, the signal inversion switch circuit 24 does not invert the logic, but the signal inversion switch circuit 28 inverts the logic. This makes it possible to control the signals in the clock control circuit 25 according to conventional logic signals, and to invert the phase between the input signal to the input buffer 21 and the output signal from the output buffer 29 .

In the data driver IC 13 provided in the even stage, this input signal is the inversion of normal logic. Therefore, as shown in FIG. 3B, the signal inversion switch circuit 24 inverts the logic, while the signal inversion switch circuit 28 does not invert the logic. This makes it possible to control the signals in the clock control circuit 25 according to conventional logic signals, and to invert the phase between the input signal to the input buffer 21 and the output signal from the output buffer 29 .

4A and 4B are schematic diagrams illustrating duty ratio errors observed when a clock signal is transmitted through multi-stage cascaded data driver ICs.

FIG. 4A shows a clock signal input to a first stage of an existing multi-stage data driver IC, and further shows clock signals output from each stage of a data driver IC. FIG. 4B shows clock signals input to the first stage of the multi-stage data driver IC according to the present invention, and further shows clock signals output from the respective stages of the data driver IC. In Figures 4A and 4B, an output buffer is used to introduce a longer delay in the negative transition of the signal than in the positive transition of the signal. Therefore, in each data driver IC, the output clock signal has a wider pulse width than the input clock signal.

As shown in FIG. 4A, where existing data driver ICs are connected in series to form multiple stages, duty ratio errors will accumulate in each stage. As a result, the data driver IC at the last stage generates a waveform having a greatly different waveform from the clock signal having a duty ratio of 50% input to the first stage.

As shown in FIG. 4B, the data driver ICs 13 of the present invention are connected in series to form multiple stages, and duty cycle errors are mutually canceled at each stage. Therefore, the output of the data driver IC at the last stage maintains a waveform similar to that of the clock signal having a duty ratio of 50% input to the first stage.

In the data driver IC 13 according to the invention, the logic of the output signal is inverted with respect to the logic of the input signal, which makes it possible to eliminate the duty cycle error due to the difference in delay between positive and negative signal transitions compared to offset. Therefore, even when the data driver ICs 13 are cascaded, duty cycle errors will not be accumulated through signal transmission. Logic inversion processing may be selectively performed in response to an even/odd switch signal at a circuit stage before core signal processing or at a circuit stage after core signal processing.

FIG. 5 is a circuit diagram showing another example of the structure of a data driving IC.

The data driver IC 13A of FIG. 5 is different from the data driver IC 13 of FIG. 2 in that a signal inversion switch circuit 32 and a signal inversion switch circuit 33 are provided for inverting the data signal DATA. Other configurations are the same as those of the data driver IC 13 in FIG. 2 .

In the example of FIG. 5, not only the clock signal CLK is logically inverted, but also the data signal DATA is also logically inverted. One of the signal inversion switch circuit 32 or the signal inversion switch circuit 33 inverts the data signal DATA. Which one of the signal inversion switch circuit 32 and the signal inversion switch circuit 33 is used for the inversion process is determined by the even/odd switch signal. In cascaded data driver ICs 13A, even data driver IC 13A is given a high-level even/odd switching signal, and odd data driver IC 13A is given a low-level even/odd switching signal, for example.

When data signal DATAin is represented in logic that is inverted to normal logic, signal inverting switch circuit 32 inverts the logic, thereby providing data signal DATA with normal logic for use in data control circuit 26 . In this case, there is no logic inversion in the signal inversion switch circuit 33, so that the output data signal DATAout supplied to the subsequent stage has an inverse logic to the input data signal DATAin.

When the input data signal DATAin has normal logic, the signal inversion switch circuit 32 does not invert the logic, thereby providing the data signal DATA with normal logic for use in the data control circuit 26 . In this case, the signal inversion switch circuit 33 inverts the logic so that the output data signal DATAout output to the next stage has the opposite logic to the input data signal DATAin.

The data driver IC 13A of FIG. 5 operates in the same manner as the data driver IC 13 of FIG. 2 except for the logical inversion of the data signal DATA, and thus its description is omitted.

As described above, in the data driver IC 13A of FIG. 5, the logic of the output signal is inverted relative to the logic of the input signal with respect to the data signal DATA of the clock signal CLK, thereby eliminating delays due to positive signal transitions and negative signal transitions. The duty cycle error is caused by the timing difference between the varying delays. Therefore, even when the data driver ICs 13A are arranged in multi-stage cascade, accumulation of duty cycle errors due to signal transmission can be avoided. In response to the even/odd switch signal, the signal stage before the internal signal processing or the signal stage after the internal signal processing performs this logical inversion, thereby ensuring that a signal with normal logic is provided for use by the internal signal processing.

FIG. 6 is a circuit diagram showing one embodiment of a signal inversion switching circuit according to the present invention. The signal inversion switch circuits shown in FIG. 6 can be used as the signal inversion switch circuits 24 and 28 in FIG. 2 and can be used as the signal inversion switch circuits 32 and 33 in FIG. 5 .

The signal inversion switch circuit of FIG. 6 includes inverters 51 and 52 and transmission gates 53 and 54 . A high-level even/odd switching signal (or the inversion of the even/odd switching signal) makes the transmission gate 54 conduction, and a low-level even/odd switching signal (or an inversion of the even/odd switching signal) makes the transmission Gate 53 conducts. With the conduction state of the transmission gate 54 , the signal IN passes through the transmission gate 54 and is output as the output signal OUT. With the conduction state of the transmission gate 53 , the input signal IN is inverted by the inverter 51 , and passed through the transmission gate 53 , and output as the output signal OUT.

FIG. 7 is a circuit diagram showing another embodiment of a signal inversion switch circuit according to the present invention. The signal inversion switch circuits shown in FIG. 7 can be used as the signal inversion switch circuits 24 and 28 in FIG. 2 and can be used as the signal inversion switch circuits 32 and 33 in FIG. 5 .

The signal inverting switch circuit of FIG. 7 includes inverters 61 and 62 and NAND gates 63 to 65 . When the even/odd switching signal (or the inversion of the even/odd switching signal) is high, the input signal IN is inverted by the NAND gate 64 and further inverted by the NAND gate 65 . Therefore, the output signal OUT has the same logic as the input signal IN in this case. When the even/odd switching signal (or the inversion of the even/odd switching signal) is at low level, the inverted signal of the input signal IN output from the inverter 61 is inverted by the NAND gate 63 and further inverted by the NAND gate 65. invert. Therefore, the output signal OUT has the opposite logic of the input signal IN in this case.

In this way, the signal inversion switch circuit used in the present invention can be easily realized as a selector circuit based on transmission gates or combinational logic circuits.

According to the present invention, the signal logic inversion in the cascaded signal transmission path is not limited to the data driver of the liquid crystal display device. The signal logic inversion of the present invention can also be applied to any system where multiple devices are cascaded such that signals are transmitted through the cascade. This avoids the accumulation of duty cycle errors in subsequent circuit stages. The devices used in such systems can be provided with two signal inversion switching circuits, one at the input and the other at the output, to obtain correct signal inversion.

In addition, the present invention is not limited to these embodiments, and various modifications can be made without departing from the present invention.

the scope of the invention.

This application is based on Japanese Priority Application No. 2002-019518 filed on January 29, 2002, the entire contents of which are hereby incorporated by reference.

Claims (8)

1. An integrated circuit comprising: A first signal inversion switch circuit that receives a signal supplied from the outside as a first input signal, then outputs the first input signal after logically inverting the input signal in response to a first state of the switch signal, and responds to the switch signal The second state of the first input signal is directly output without inverting its logic; a signal processing circuit that performs signal processing based on the output of the first signal inverting switch circuit; and A second signal inverting switch circuit, which receives the output of the first inverting switch circuit as a second input signal, and then outputs the first signal after logically inverting the input signal in response to a second state of the switch signal Two input signals, and directly outputting the second input signal in response to the first state of the switch signal without inverting its logic. 2. The integrated circuit of claim 1, wherein the first input signal is a clock signal, and the signal processing circuit comprises: a clock control circuit, which generates a timing control signal according to the output of the first signal inversion switch circuit; and A data control circuit that responds to the timing control signal to acquire a data signal provided from the outside. 3. The integrated circuit according to claim 2, wherein said signal processing circuit further includes a circuit for generating and outputting a driving signal for driving a liquid crystal display panel based on the data signal acquired by said data control circuit. 4. The integrated circuit of claim 2, further comprising: a third signal inverting switch circuit which receives a signal supplied from outside as a first input data signal and then outputs the first input data signal to said data control after inverting the signal in response to a first state of the switch signal circuit, and in response to the second state of the switch signal, directly outputs the first input data signal to the data control circuit without inverting its logic; A fourth signal inversion switch circuit, which receives the output of the third signal inversion switch circuit as a second input data signal, and then responds to the second state of the switch signal, and outputs the input data signal after logic inversion The second input data signal, and directly outputting the second input data signal in response to the first state of the switch signal without inverting its logic. 5. A liquid crystal display device, comprising: LCD panel; a gate driver, which drives the gate bus of the liquid crystal display panel; and a plurality of data drivers, which are arranged in cascade, and drive the data bus of the liquid crystal display panel, wherein each of the data drivers receives a signal provided by the preceding stage, and inverts the signal after logically inverting it sent to the subsequent stage, Each of these data drivers includes: A first signal inverting switch circuit which receives a signal supplied from a preceding stage as a first input signal, then outputs the first input signal after logically inverting the input signal in response to a first state of the switch signal, and responds to the switch signal The second state of the first input signal is directly output without inverting its logic; a signal processing circuit that performs signal processing based on the output of the first signal inverting switch circuit to generate a signal for driving the data bus; and The second signal inverting switch circuit receives the output of the first signal inverting switch circuit as a second input signal, and then outputs the input signal after logic inverting the input signal in response to the second state of the switch signal. The second input signal is to the subsequent stage, and the second input signal is directly output to the subsequent stage in response to the first state of the switch signal without inverting its logic. 6. The liquid crystal display device according to claim 5, wherein odd-numbered data drivers in the plurality of data drivers receive switching signals in the second state, and even-numbered data drivers in the plurality of data drivers receive switching signals in the first state switch signal. 7. A signal transmission system comprising: a plurality of integrated circuits arranged in cascade, wherein each of said integrated circuits receives a signal supplied from a previous stage, and after logically inverting it, transmits the signal to backstage, where each of said integrated circuits includes: A first signal inverting switch circuit which receives a signal supplied from a preceding stage as a first input signal, then outputs the first input signal after logically inverting the input signal in response to a first state of the switch signal, and responds to the switch signal The second state of the first input signal is directly output without inverting its logic; a signal processing circuit that performs signal processing based on the output of the first signal inverting switch circuit; and The second signal inverting switch circuit receives the output of the first signal inverting switch circuit as a second input signal, and then outputs the input signal after logic inverting the input signal in response to the second state of the switch signal. The second input signal is to the subsequent stage, and the second input signal is directly output to the subsequent stage in response to the first state of the switch signal without inverting its logic. 8. The signaling system according to claim 7 , wherein odd integrated circuits of the plurality of integrated circuits receive the switching signal in the second state, and even integrated circuits of the plurality of integrated circuits receive the switching signal in the first state. status switch signal.

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