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CN1828765A - Buffer assembly for memory module, memory module and memory system - Google Patents

Buffer assembly for memory module, memory module and memory system Download PDF

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Publication number
CN1828765A
CN1828765A CNA2006100550878A CN200610055087A CN1828765A CN 1828765 A CN1828765 A CN 1828765A CN A2006100550878 A CNA2006100550878 A CN A2006100550878A CN 200610055087 A CN200610055087 A CN 200610055087A CN 1828765 A CN1828765 A CN 1828765A
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China
Prior art keywords
memory
signal
signals
address
memory components
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CNA2006100550878A
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Chinese (zh)
Inventor
G·布劳恩
S·德约尔耶维克
A·亚各布斯
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN1828765A publication Critical patent/CN1828765A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/109—Control signal input circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

This invention relates to a buffer unit (3) for memory module (1) comprising a plurality of memory modules (2), and the buffer unit (3) comprises: the first data interface (4) for receiving and accessing info according to data transfer protocol, the second data interface (6) of a set of memory modules for transmitting clock signal of address signal and instruction signal to a plurality of memory modules and transmitting control signal to a plurality of memory modules, and a control unit (5) that brings the address signal and the instruction signal to the memory modules (2) during the first clock signal cycle, and when the address signal and instruction signal appear in the second clock signal cycle, the control unit (5) bring the control signal to the memory modules (2) for activate the memory modules (2) so that the appeared address signal and instruction signal are received by the memory modules (2).

Description

The Bunper assembly of memory module, memory module and accumulator system
Technical field
The present invention relates to a kind of Bunper assembly at memory module with a plurality of memory assemblies.In addition, the present invention relates to a kind of memory module with a plurality of memory assemblies and a Bunper assembly.In addition, the invention still further relates to a kind of accumulator system with two memory modules and a memory controller, this memory controller provides access information at this memory module.
Background technology
In novel memory module, promptly in so-called " full buffer internal memory module (Fully BufferedDIMM) ", position memory assembly thereon for example no longer directly is connected with the memory controller of computer system.Replace, between memory controller and memory assembly, arrange so-called Bunper assembly, this Bunper assembly carries out data transmission by the host-host protocol according to high-speed transfer between memory controller and memory module, and director data, control data, clock data and the address date that will be used to control, be comprised in wherein be applied to this memory assembly.Basically, the transmission between Bunper assembly and the memory assembly realizes that by the so-called bus (Fly-By-Bus) that leaps leaping bus by this can be applied to clock data, director data, address date and control data on the memory assembly.The bus line that leaps bus utilizes passive resistance to finish on the end away from Bunper assembly, so that suppress the reflection of electric signal.In contrast, the circuit by the separation between Bunper assembly and the single memory assembly separately transmits the data-signal that is used for transmitting control data.
This leaps bus and has a plurality of bus lines, transmits address signal, command signal and control signal on these bus lines.This command signal and address signal are connected with all memory assemblies on the memory module by corresponding signal lines respectively.Structure according to memory module, each group of memory assembly (being also referred to as " row (Rank) ") utilizes control signal to come addressing, so that for example in the DRAM memory circuit, chip select signal CS can only be activated at the storage stack assembly respectively, and the instruction that this group memory assembly receives and implements to provide by this command signal, and other memory assemblies that this command signal occurs are not thereon accepted this instruction.Following situation appears thus, promptly leap bus and have the unequally loaded of having bus line, because command signal and address signal are applied on all memory assemblies by corresponding bus line, and control signal only is applied on the storage stack assembly by corresponding bus line respectively, and this group memory assembly comprises a spot of memory assembly.Other effect also can cause the load difference on the bus line.
, based on the different loads on each bus line and differently propagating, speed and thereby comes across on this memory assembly by address signal, command signal and control signal that Bunper assembly provided in the different moment.Especially, this control signal earlier comes across on each memory assembly than address signal and command signal, and this control signal is set for address date and the director data of accepting in each memory assembly usually.Because, if the quantity of the employed storage component part on the memory module is variable, then signal is at the bus of address signal and command signal or do not knowing immediately at the different travel-time on the bus line of control signal, so eliminate the common behavior of this problem therefore be difficult by time-delay element is set.Can not predict exactly thus control signal appears and address signal appears and command signal between the amount of time delay.
Especially in memory module with multi-bank memory assembly, because at the high capacity on the bus line of address signal and command signal, no longer may be with full-time these signals of clock frequency transmission, because these signals are standing great interference from Bunper assembly to the path of corresponding memory assembly.
Summary of the invention
Task of the present invention is, a kind of Bunper assembly at memory module is provided, and wherein, based on the different signal propagation time on the bus line, minimizes or eliminate that command signal and address signal are received problem in the memory assembly reliably.
In addition, task of the present invention is, a kind of memory module with a plurality of memory assemblies and a Bunper assembly is provided, and wherein reduces or eliminate the problem of the different signal propagation time on the bus line of whole signal bus.
In addition, task of the present invention is, a kind of accumulator system with a plurality of memory modules and a memory controller is provided, and wherein avoids reducing the access speed of memory module based on the access speed that reduces.
In addition, task of the present invention is, a kind of method that is used for runtime buffer device assembly is provided, minimizes or eliminate that command signal and address signal are received problem in the memory assembly reliably by this method based on the different signal propagation time on the signal wire.
This task solves by Bunper assembly according to claim 1, memory module according to claim 6, accumulator system according to claim 10 and method according to claim 12.
Other favourable improvement projects of the present invention provide in the dependent claims.
According to a first aspect of the invention, setting is at the Bunper assembly of the memory module with a plurality of memory assemblies.This Bunper assembly has first data-interface that is used for receiving according to Data Transport Protocol access information.In addition, this Bunper assembly has and is used for according to signaling protocol clock signal and address signal and command signal being transmitted (treiben) and is sent to second data-interface from the storage stack assembly of these a plurality of memory assemblies to a plurality of memory assemblies with control signal.This group memory assembly can comprise these a plurality of memory assemblies of all or part.This address signal, clock signal and command signal depend on access information, and this access information is received by first data-interface.Being received in when control signal comes across on the corresponding memory assembly of activation of one of memory assembly and address signal and command signal is performed.In addition, control module is set, this control module was applied to address signal and command signal on these a plurality of memory assemblies during first clock period of clock signal, and, when address signal and command signal appear in the second clock of following of clock signal in the cycle, to be used to activate this control signal of organizing a plurality of memory assemblies and be applied to this group memory assembly, so that the address signal and the command signal that are occurred are accepted in this memory assembly of organizing a plurality of memory assemblies.
At first realize thus, this memory module, is organized on a plurality of memory assemblies because this control signal only is applied to this during following the second clock cycle of first clock period also only with half of data rate, also promptly move effectively with the double cycle by means of Bunper assembly.Thus, address signal and command signal at most also only are transferred to these memory assemblies at every second clock in the cycle, so that have reduced access speed.Realize thus, especially in the time of on have heavy load in that corresponding address signal and command signal the are applied to signal wire of (for example because a large amount of memory assemblies that is connected), ignore the caused thus interference in the input border area of corresponding signal, during the second clock cycle, just be applied in because be used to accept the control signal of corresponding address date and director data.
In preferred form of implementation, this control module so is set, so that this control module is according to the Configuration Values that is provided or during first clock period address signal and command signal are being applied on these a plurality of memory assemblies, and when command signal and address signal appear in the second clock of following in the cycle, the control signal that will be used to activate this group memory assembly is applied to this and organizes a plurality of memory assemblies, perhaps during the identical clock period, address signal and command signal are applied on the memory assembly, and this control signal is applied on this group a plurality of memory assemblies to be activated.By this way, the memory module that is equipped with such Bunper assembly can be according to the load on the signal wire, just for example dispose according to the load based on the quantity of memory assembly, so that the method for operation of the little load that has on the signal wire (just for example when a spot of memory assembly that connects) can be set and at the method for operation of the heavy load on signal wire when a large amount of memory assembly (just for example).
According to other form of implementation of the present invention, this Bunper assembly has the config memory that is used for the stored configuration value.
In addition, this control module can so be provided with, so that access information is converted into address signal, command signal and control signal at the DRAM memory assembly according to signaling protocol.
According to other aspects of the invention, setting has a plurality of memory assemblies and the memory module according to Bunper assembly of the present invention.A plurality of memory assemblies so are connected with second data-interface by first signal wire, so that are provided for each address signal and command signal are transferred to from this Bunper assembly each of first signal wire of a plurality of memory assemblies.The storage stack assembly, just all or the partial memory assembly from a plurality of memory assemblies is connected with second data-interface by the secondary signal line, consequently is provided for control signal is transferred to from Bunper assembly the secondary signal line of the memory assembly of this group memory assembly.
Be different from traditional memory module, memory module according to the present invention utilizes Bunper assembly to move, this Bunper assembly obtains access information by Data Transport Protocol, and these access informations are converted into corresponding address signal, clock signal and control signal and command signal and are provided for a plurality of memory assemblies by this Bunper assembly.For this reason, this memory assembly is connected with this Bunper assembly by corresponding signal lines, and these signal wires are connected from this Bunper assembly and with this group memory assembly or with the partial memory assembly or with all memory assemblies.This bus system is also referred to as and leaps bus.
The control module of Bunper assembly can so dispose, so that during first clock period, be applied on a plurality of memory assemblies in the memory assembly according to the Configuration Values that is provided or with this address signal and command signal, and when address signal and command signal appear in the second clock of following in the cycle, the control signal that will be used to activate this group memory assembly is applied to this group memory assembly, perhaps during the identical clock period address signal and command signal are being applied on a plurality of memory assemblies, and control signal is being applied on this group memory assembly to be activated.By this way, this memory module can be moved with the different methods of operation according to the load on the signal wire, and wherein this Configuration Values depends on the structure of memory module.
Can stipulate that this Configuration Values can be stored in the config memory.
This memory assembly is so arranged, so that receive or send data-signal with burst mode, Tu Fa the length Configuration Values that depends in Bunper assembly to be provided wherein, in this burst according to transmitting this data-signal by the activation of control signal corresponding.By this way, can change the length of burst mode according to the method for operation of memory module, so that increase burst-length when activating following during the second clock cycle of first clock period, even so that also can guarantee data volume waiting for transmission during with the data rate run memory module that reduces, wherein this control signal just was applied in during the second clock cycle.
According to other aspects of the invention, accumulator system is set, this accumulator system comprises a plurality of such memory modules and a memory controller, and this memory controller is connected with a plurality of memory modules.This memory controller provides access information to each of a plurality of memory modules, and consequently each control signal that is produced from the access information at a plurality of memory modules alternately is provided for each memory assembly from the Bunper assembly of a plurality of memory modules.
This accumulator system can by alternately to the memory assembly of a plurality of memory modules to carry out that addressing compensates owing to activate each memory assembly slack-off, to the access of memory assembly.For example this can realize thus, and promptly this memory controller is so arranged, so that this memory controller alternately sends to a plurality of memory modules with corresponding access information.
According to other aspects of the invention, a kind of method that is used to move at the Bunper assembly of the memory module with a plurality of memory assemblies is set.At this, receive access information by Data Transport Protocol, and clock signal, address signal and command signal are sent to a plurality of memory assemblies and send control signal to the storage stack assembly according to signaling protocol.This address signal, clock signal, control signal and command signal depend on access information, and wherein being received in when control signal occurring of the activation of memory assembly and address signal and command signal realized.This address signal and command signal are being applied to during first clock period on a plurality of memory assemblies, and when address signal and command signal appear in the second clock of following in the cycle, the control signal that is used to activate this group memory assembly is applied to this group a plurality of memory assemblies to be activated, so that the address signal that is occurred and command signal are accepted this and organize in a plurality of memory assemblies.
Description of drawings
Explain the preferred embodiment of the present invention according to accompanying drawing below.Wherein:
Fig. 1 illustrates the memory module according to first form of implementation of the present invention;
Fig. 2 illustrates the signal timing diagram that is used to illustrate according to the function of the memory module of the form of implementation of Fig. 1;
Fig. 3 illustrates the memory module according to other forms of implementation of the present invention; And
Fig. 4 illustrates accumulator system according to other aspects of the invention.
Embodiment
Figure 1 illustrates frame circuit diagram according to memory module 1 of the present invention.This memory module 1 comprises eight memory assemblies 2, and these memory assemblies 2 are connected with a Bunper assembly 3.This memory module 1 for example is constituted as the form of printed circuit board (PCB), and signal wire 7 is positioned on this printed circuit board (PCB), utilizes these signal wires, and these memory assemblies 2 are connected with this Bunper assembly 3.
Bunper assembly 3 has data transmission interface 4, and this memory module 1 obtains access information by this data transmission interface 4 from the outside, so as to write, sense data or so that implement other functions in this memory assembly 2.These access informations are fed to the control module of Bunper assembly 3, and are divided into and/or convert to suitable address signal, clock signal, control signal and the command signal that is used to control this memory assembly 2 there.
In the present embodiment, memory assembly 2 is the DRAM memory assembly preferably, also can be the memory assembly of other types, such as SRAM assembly or the like.
In addition, this Bunper assembly 3 has signaling interface 6, and clock signal, command signal and control signal that this signaling interface 6 will extract from access information or produce are applied on these memory assemblies 2 by corresponding signal lines.For this reason, each signal line of the signal wire 7 of memory module 1 and this Bunper assembly 3 corresponding be connected 6 and with each corresponding of memory assembly 2 under be connected and be connected.Just, if this Bunper assembly 3 is applied to corresponding signal on one of signal wire 7, then this signal is provided for each of memory assembly 2 by affiliated signal wire.In described embodiment, this is suitable for control signal, command signal, clock signal and address signal.Storage data in the storage data of being read from these memory assemblies 2 or these memory assemblies 2 to be written are travelled to and fro between each transmission of this memory assembly separately by data signal line 8, that is to say, the data of Bunper assembly connect 9 and each data of corresponding memory assembly 2 have so-called point-to-point connection between connecting.
Under the situation of DRAM memory assembly, address signal comprises all address signals that comprise the address, storehouse, and control signal comprises chip activation signal CS, and command signal comprises line activating signal RAS and row activation signal CAS and write signal WE.These signals are from by extracting the received access information of data transmission interface 4.In Fig. 1, according to embodiment, shown connecting line is understood that signal wire or a branch of a plurality of signal wire.For example, this address signal is transferred to these memory assemblies 2 by a plurality of signal wires from this Bunper assembly 3, and for simplicity, this illustrates by a connecting line.
The function of this memory module 1 further specifies by means of the signal timing diagram of Fig. 2.This signal timing diagram not only illustrate on this Bunper assembly 3 and also clock signal clk, address signal and command signal CA on the memory assembly 2 and control signal CS are shown (chip are selected: signal change procedure chip activation signal).Address signal and command signal CA comprise signal, line activating signal RAS and row activation signal CAS and the write signal WE of the address that is used to transmit the memory block for the treatment of addressing, the explanation of this write signal is write in the memory block for the treatment of addressing or should read from the memory block for the treatment of addressing.
Be clear that on the one hand signal change procedure in the connection of Bunper assembly 3 and the time-delay t that is connected of one of memory assembly 2 LeapSignal change procedure.Be clear that, especially in bigger group of the memory assembly 2 on the memory module 1, with respect to the duration that is applied by Bunper assembly 3 during command signal and the address signal, the duration that command signal and address signal CA come across on the memory assembly 2 effectively reduces significantly.Reason to this is at the heavy load on the signal wire 7 of command signal and address signal CA, this heavy load causes usually, the beginning of signal, just near the input edge time range greatly disturbed, so that during each signal is in this time range, can not guarantee to receive in the memory assembly reliably.This effect be moved this memory module 1 with this high clock frequency especially in very high transmission frequency, just occur during high clock frequency.
According to the present invention, so move this memory module now, so that during two clock period of clock signal clk, realize access memory assembly 2.At first, in first clock period, address signal and command signal are applied on the corresponding signal lines by this Bunper assembly 3.Only after first clock period finished, just so apply this control signal (being chip activation signal CS) in the cycle herein at the second clock of directly or indirectly following, so that in the corresponding input buffer (not shown) of the address signal that is therefore occurred and the command signal CA memory assembly 2 that is read into the addressing of one/a plurality of institute.Essential this chip activation signal is so that receive address signal and command signal in this memory assembly.Address signal and command signal CA be applied to for first clock period during, preferably when first clock period began in the example shown along with the trailing edge of clock signal clk along realization.Chip activation signal CS applies the trailing edge of following along with clock signal clk along realization.In this hypothesis, after the clock period end, the main signal that is directly occurred after the corresponding level translation of address signal and command signal disturbs basically no longer to command signal and address signal CA are received generation interference in the memory assembly 2.Under the situation that is subject to disturb of bigger clock frequency and command signal and address signal, also can be provided with, these signals were applied on the corresponding signal lines during first clock period, and only the 3rd or more late clock period during, the relevant chip activation signal CS that is used to accept address signal and command signal CA just is applied to corresponding memory assembly 2.
Because therefore the access to corresponding memory assembly 2 or a plurality of memory assemblies realizes during at least two clock period, so the burst-length that correspondingly doubles or continue to improve to the burst access of memory assembly suits, so that during two or more clock period, do not reduce or do not reduce basically access data speed by control corresponding.If this chip activation signal CS is applied in during directly following the second clock cycle of first clock period, then burst-length is preferably so selected, so that data are transferred to this memory assembly 2 or are transmitted by this memory assembly 2 during at least two clock period accordingly.
Other forms of implementation of memory module of the present invention have been described in Fig. 3.The element of components identical or same or similar function has identical reference symbol.Different with the form of implementation of Fig. 1, apply different control signals at first group 21 of memory assembly 2 with memory assembly second group 22.Be delivered to from this Bunper assembly 3 by corresponding signal lines 7 at command signal and address signal CA during each of the memory assembly that is disposed on the memory module, the signal wire that is used for transmission of control signals CS is correspondingly shorter, because these signal wires provide control signal corresponding CS only for the part of memory assembly 2.Owing to occur disturbing at the high capacity on the signal wire of address signal and command signal CA, as previously mentioned, these disturb scope input time that preferably greatly influences each signal eye (just directly after the signal edge), and the time that each signal is applied on the corresponding signal lines is long more, these interference reductions.Because obviously littler, so can not consider or only consider this interference on these signal wires among a small circle at the load on the signal wire 7 of control signal CS.The memory module 1 of the form of implementation of Fig. 3 is moved in the mode identical with the memory module of the form of implementation of Fig. 1 basically.Control signal CS produces according to the access information that is applied on this memory module 1 from the outside., according to address signal, in preferably two group 21 of an addressable memory assembly of particular moment, one of 22.
Bunper assembly 3 also can so dispose, so that the method for operation is regulated according to Configuration Values.This Configuration Values can be stored in the configuration register 12, and determine by its content: whether control signal, command signal and address signal are applied on the corresponding signal lines simultaneously, perhaps according to the above-mentioned method of operation, whether command signal and address signal at first are applied on the corresponding signal lines, and then control signal is applied on the corresponding signal lines at this group memory assembly 2.This Configuration Values can be conditioned on the one hand regularly, and is perhaps predetermined by memory controller at initial phase.Also may regulate this Configuration Values, and this Configuration Values is handed to memory controller according to pre-determined load on the signal wire or the quantity that is connected the memory assembly on the signal wire.
Accumulator system with two memory modules 1 and a memory controller 10 has been described in Fig. 4.This memory controller 10 is delivered to each of memory module 1 with access information, and transmits and receive data by data-interface 11.If this memory module 1 is in the operational mode, control signal is applied in second, during following the clock period that applies command signal and address signal in this operational mode, then this memory controller also only allowed to send to a certain memory module according to access information during every second clock cycle, that is to say, must reduce the data rate of access information according to the access speed that reduces of memory module 1., in this case, these two memory modules 1 can alternately receive access information, so that the first memory module is during a clock period and the second memory module obtains corresponding access information during the clock period subsequently.Especially, this memory controller 10 should so be controlled this control module 5, so that command signal, address signal and control signal so be applied on this memory assembly 2, so that is transferred to memory module 1 with storing the data time-delay.
In interchangeable form of implementation, these two memory modules can not be directly but be connected with memory controller by so-called link (daisy chain (Daisy Chain)) mutually.For this reason, this memory controller is connected with the first memory module, so that send access information and the corresponding data of transmission.This access information comprises the address, and in this address explanation memory module which should be addressed.Accordingly, the hub assembly that is set in the first memory module receives access information and decision, whether be provided in the first memory module of being distributed addressable storage district, be comprised in control signal, command signal and address signal in the access information, or therefore whether subsequently memory module should be addressed in this daisy chain.
If memory module subsequently should be addressed, then the corresponding output end of access information by the hub assembly of first memory module is output and is forwarded to second memory module subsequently.Redefine these access informations there and whether comprise control signal, command signal and address signal, these signals should carry out addressing to memory block corresponding, that exist on this memory module.If these access informations do not relate to the second memory module, then these access informations are exported to the output terminal of the second hub assembly etc. again.That is to say that these access informations are handed to memory module in this chain of memory module.Constitute so-called daisy chain by this way, this daisy chain is by between this memory controller and the first memory module or point-to-point the connecting and composing between a plurality of memory module.
List of numerals
1 memory module
2 memory assemblies
3 Bunper assemblies
4 data transmission interfaces
5 control modules
6 signals connect
7 signal wires
8 data signal lines
9 data connect
10 memory controllers
21 first groups of memory assemblies
22 second groups of memory assemblies

Claims (12)

1.针对具有多个存储器组件(2)的存储器模块(1)的缓冲器组件(3)，其包括：1. A buffer assembly (3) for a memory module (1) with a plurality of memory assemblies (2), comprising: -第一数据接口(4)，用于根据数据传输协议接收存取信息，其中地址信号、时钟信号、控制信号和指令信号取决于该存取信息，- a first data interface (4) for receiving access information according to a data transfer protocol, wherein address signals, clock signals, control signals and command signals depend on the access information, -第二数据接口(6)，用于根据信令协议将时钟信号和地址信号及指令信号传送到多个存储器组件并且将控制信号传送到来自多个存储器组件(2)的一组存储器组件，- a second data interface (6) for transferring clock signals and address signals and instruction signals to the plurality of memory components and control signals to a group of memory components from the plurality of memory components (2) according to a signaling protocol, 其中，存储器组件(2)的激活和地址信号及指令信号的接受根据所述控制信号来实现，Wherein, the activation of the memory component (2) and the acceptance of address signals and instruction signals are realized according to the control signals, -控制单元(5)，其将地址信号和指令信号在时钟信号的第一时钟周期期间施加到多个存储器组件(2)上，并且在时钟信号的接着的第二时钟周期中出现地址信号和指令信号时，将用于激活该组多个存储器组件的控制信号施加到该组待激活的多个存储器组件(2)上，以致所出现的地址信号和指令信号被接受到该组多个存储器组件(2)的存储器组件中。- a control unit (5) which applies address signals and command signals to the plurality of memory components (2) during a first clock cycle of the clock signal, and the address signals and command signals occur during a second clock cycle of the clock signal command signal, a control signal for activating the plurality of memory components of the group is applied to the plurality of memory components (2) to be activated, so that the address signal and command signal appearing are accepted to the plurality of memory components of the group In the memory component of component (2). 2.根据权利要求1所述的缓冲器组件(3)，其中，如此配置所述控制单元(5)，以致该控制单元(5)根据所提供的配置值或者将地址信号和指令信号在第一时钟周期期间施加到该组存储器组件上，并且在接着的第二时钟周期中出现地址信号和指令信号时，将用于激活该组多个存储器组件(2)的控制信号施加到该组多个存储器组件(2)上，或者在相同的时钟周期期间将地址信号和指令信号施加到存储器组件(2)上，而将控制信号施加到该组待激活的多个存储器组件上。2. The buffer assembly (3) according to claim 1, wherein the control unit (5) is configured such that the control unit (5) assigns the address signal and the command signal to the Applied to the group of memory components during one clock cycle, and a control signal for activating the group of multiple memory components (2) is applied to the group of multiple Each memory component (2), or the address signal and command signal are applied to the memory component (2) during the same clock cycle, and the control signal is applied to the multiple memory components to be activated in the group. 3.根据权利要求2所述的缓冲器组件(3)，具有用于存储所述配置值的配置存储器(12)。3. The buffer assembly (3) according to claim 2, having a configuration memory (12) for storing said configuration values. 4.根据权利要求1至3之一所述的缓冲器组件(3)，其中，所述控制单元(5)如此来设置，以致所述存取信息根据信令协议被转换成针对DRAM存储器组件的地址信号、指令信号和控制信号。4. The buffer assembly (3) according to one of claims 1 to 3, wherein the control unit (5) is arranged such that the access information is converted to a DRAM memory assembly according to a signaling protocol address signals, command signals and control signals. 5.根据权利要求1至4之一所述的缓冲器组件(3)，其中，所述控制单元(5)被设置，以便从所述存取信息中产生多个控制信号，其中，该多个控制信号中的每一个被分配给所述多个存储器组件(2)的相应组。5. The buffer assembly (3) according to any one of claims 1 to 4, wherein the control unit (5) is configured to generate a plurality of control signals from the access information, wherein the plurality Each of the control signals is assigned to a corresponding group of the plurality of memory components (2). 6.具有多个存储器组件和一个根据权利要求1所述的缓冲器组件的存储器模块(6)，6. A memory module (6) with a plurality of memory components and a buffer component according to claim 1, 其中，所述多个存储器组件(2)的组通过第一信号线与第二数据接口(6)如此连接，以致设置有用于将时钟信号以及指令信号和地址信号从该缓冲器组件传输到每个存储器组件的第一信号线的每一个，并且Wherein, the group of the plurality of memory components (2) is connected to the second data interface (6) via the first signal line in such a way that a device for transmitting the clock signal as well as the instruction signal and the address signal from the buffer component to each Each of the first signal lines of the memory components, and 其中，所述多个存储器组件(2)的组通过第二信号线与第二数据接口(6)如此连接，以致设置有用于将控制信号从该缓冲器组件(3)传输到来自该组存储器组件(2)的存储器组件(2)的每一个的第二信号线。Wherein, the group of the plurality of memory components (2) is connected to the second data interface (6) via the second signal line in such a way that a control signal is provided for transmitting the control signal from the buffer component (3) to the memory from the group A second signal line for each of the memory components (2) of the component (2). 7.根据权利要求6所述的存储器模块(1)，其中，所述缓冲器组件的控制单元(5)被如此配置，以致该控制单元(5)根据所提供的配置值或者在第一时钟周期期间将地址信号和指令信号施加到多个存储器组件上，并且在接着的第二时钟周期中出现地址信号和指令信号时，将用于激活该组存储器组件的控制信号(CS)施加到该组存储器组件(2)上，或者在相同的时钟周期期间将地址信号和指令信号施加到存储器组件上，而将该控制信号施加到该组待激活的多个存储器组件(2)上。7. The memory module (1) according to claim 6, wherein the control unit (5) of the buffer assembly is configured such that the control unit (5) according to the provided configuration value or at the first clock Address signals and command signals are applied to a plurality of memory components during a cycle, and when the address signals and command signals occur in the following second clock cycle, a control signal (CS) for activating the group of memory components is applied to the The address signal and command signal are applied to the memory components (2) of the group, or the address signal and the command signal are applied to the memory components during the same clock cycle, while the control signal is applied to the plurality of memory components (2) of the group to be activated. 8.根据权利要求7所述的存储器模块(1)，其中，所述缓冲器组件(3)具有用于存储所述配置值的配置存储器(12)。8. The memory module (1) according to claim 7, wherein the buffer component (3) has a configuration memory (12) for storing the configuration values. 9.根据权利要求7或8所述的存储器模块(1)，其中，多个存储器组件被如此设置，以便以突发模式接收或发送数据信号，其中，突发的长度取决于在所述缓冲器组件(3)中所提供的配置值，在该突发中根据通过相应的控制信号的激活来传输数据信号。9. A memory module (1) according to claim 7 or 8, wherein a plurality of memory components are arranged to receive or transmit data signals in burst mode, wherein the length of the burst depends on the The data signal is transmitted in the burst according to the activation by the corresponding control signal according to the configuration values provided in the converter component (3). 10.存储器系统，其具有根据权利要求6至9之一所述的多个存储器模块(1)和一个与这些存储器模块连接的存储控制器(10)，该存储控制器(10)将所述存取信息如此提供给多个存储器模块(1)中的每一个，以致从针对该多个存储器模块(1)的存取信息中所产生的各个控制信号从多个存储器模块(1)的缓冲器组件(3)交替地被提供给多个存储器组件的各个组。10. Memory system, it has a plurality of memory modules (1) according to one of claims 6 to 9 and a memory controller (10) connected to these memory modules, the memory controller (10) will The access information is provided to each of the plurality of memory modules (1) such that respective control signals generated from the access information for the plurality of memory modules (1) are received from buffers of the plurality of memory modules (1). Memory modules (3) are alternately provided to groups of a plurality of memory modules. 11.根据权利要求7所述的存储器系统，其中，所述存储控制器(10)被如此设置，以致该存储控制器(10)将各个存取信息交替地发送给所述多个存储器模块(1)。11. The memory system according to claim 7, wherein the memory controller (10) is configured such that the memory controller (10) alternately sends each access information to the plurality of memory modules ( 1). 12.用于运行针对具有多个存储器组件(2)的存储器模块(1)的缓冲器组件(3)的方法，12. A method for operating a buffer component (3) for a memory module (1) with a plurality of memory components (2), 其中，通过数据传输协议接收存取信息，Among them, the access information is received through the data transmission protocol, 其中，根据信令协议将地址信号、时钟信号和指令信号传送给多个存储器组件，并且将控制信号传送给多个存储器组件(2)的一组存储器组件，wherein address signals, clock signals and instruction signals are transmitted to a plurality of memory components according to a signaling protocol, and control signals are transmitted to a group of memory components of the plurality of memory components (2), 其中，该地址信号、时钟信号、控制信号和指令信号取决于该存取信息，Wherein, the address signal, clock signal, control signal and command signal depend on the access information, 其中，多个存储器组件的激活和地址信号及指令信号的接受根据控制信号来执行，wherein activation of a plurality of memory components and acceptance of address signals and command signals are performed according to control signals, 其中，该地址信号和指令信号在时钟信号的第一时钟周期期间被施加到该存储器组件上，并且在接着的第二时钟周期中出现地址信号和指令信号时，用于激活该组存储器组件的控制信号被施加到该组待激活的多个存储器组件上，以致所出现的地址信号和指令信号被接受到该组多个存储器组件中。Wherein, the address signal and the command signal are applied to the memory component during the first clock cycle of the clock signal, and when the address signal and the command signal appear in the next second clock cycle, are used to activate the group of memory components Control signals are applied to the plurality of memory components to be activated, so that address signals and command signals present are received in the plurality of memory components of the group.
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