CN1217342C - Multi-channel storage management system - Google Patents

Abstract

A multi-channel memory management system includes a plurality of memory channels, a request scheduler, and a read request recorder. The memory channel and the independent data bus form an independent data access bank in a mode of interleaving the addressing memory device, so as to provide an access path of an interleaving addressing area of the independent access memory device according to the system requirement. The demand dispatch device simultaneously sends the system demand to the memory channel. The read request recorder is coupled with the request scheduling device, and when the system requests to read data from the self-storage channel, the read request recorder records the original sequence required by the system so as to facilitate the storage channel to return the data in the original sequence to respond to the system request.

Description

Multi-channel storage management system

The present invention relates to a memory management system, in particular to a system with multiple memory channels (MultipleMemoryChannel) for addressing data stored in memory in an interleaved manner.

Storage devices, such as dynamic random access storage, can store digitized data in its storage unit (MemoryCell). In order to access these digitized data, many request initiators, such as various program software, will issue many system requests to read or write data for the physical location of the storage unit. In order to effectively manage storage resources, storage devices are usually divided into multiple pages (Pages) in a logical addressing manner. In this way, programmers can access the data in the storage device according to these logically addressed pages without having to trace their physical locations. When the system requires to read out the data stored in the page of the storage device, it will first copy all the data in the page into the sense amplifier (SenseAmplifier), and then take out the required data fragments from the sense amplifier, and It is sent to the required request activation device. It can therefore be understood that the boot device is required to access data located in the storage device through logically addressed pages.

Generally speaking, a storage device serves multiple request triggering devices, and these request triggering devices often send system requests to the storage device at the same time. As shown in FIG. 1 , in order to coordinate these system requirements, the storage controller 4, the storage device 2 and the required activation devices 6, 8, and 10 form a traditional single-channel memory management system (Single-Channel Memory Management System). The storage controller 4 receives the system requests issued by the request activation device-A, the request activation device-B and the request activation device-C, and transmits these system requests to the storage device 2 according to their priority order. When the system request is sent to the storage device 2, the storage device 2 will respond to the system request and use all the data bus bandwidth of the storage management system to serve the request to send the system request to activate the device. In other words, only after the previous system request is processed, the subsequent system request can enter and access the storage device 2 . For example, when the system request issued by the requesting device A is accessing the storage device 2, other system requests issued by the requesting device 6, 8, and 10 will enter a waiting state until the system request of the device A is requested. After the request processing is completed, continue to process other system requests.

A disadvantage of the above-mentioned conventional single-channel storage management system is that at a certain moment, the storage management system can only handle one system request, which will cause delays for other system requests that cannot be processed simultaneously. Another shortcoming of the traditional storage management system is that the storage access efficiency is slow. As mentioned above, when the system requires to read data from the storage device, the data will be copied to the sense amplifier (SenseAmplifier) first. If the data to be read out already exists in the sense amplifier, it will take very little time to read out the data at this time, and this state is called a page hit (Page-Hit). If the system requires that the data to be read does not exist in the sense amplifier, the data in the sense amplifier must first be written back to the storage device, and then the required page is copied from the memory device to the sense amplifier, and finally Then the required data fragments are taken out from the sense amplifier, and this state is called Page-Miss. Due to the state of page miss, it takes a lot of time to repeatedly read and write to the storage device. Generally speaking, the time spent on these repeated reading and writing actions is about nine times the time spent on processing the page hit status, thus making the entire data access process inefficient. Since the system requires that the data in the storage device be read out in a random manner, page misses cannot be avoided during this process, which causes the problem of low efficiency of the storage management system of the transfer system.

Figure 2 shows a traditional dual-channel memory management system (Dual-Channel Memory Management System). Wherein, the storage device is divided into a storage channel-112 and a storage channel-216, and is coupled with the required activation device 18, 20, 22 through the channel control device 14. The channel control device 14 is responsible for receiving the system requests sent by the request initiating devices 18 , 20 , 22 and sending these requests to the storage channels 12 , 16 . The storage channel-1 is individually served by the channel control device 14 in a one-to-one manner to the request activation device-A, while the storage channel-2 is served by all the remaining request activation devices 20 , 22 . Incidentally, the so-called storage channel refers to an independent data access library for transmitting data stored in a storage unit with a specific address through a set of independent data transmission lines. For example, in a traditional graphics chip, memory channel-1 often serves a single request enabling device-A, such as a texture buffer. The storage channel-2 will serve the remaining request enablers 20 , 22 .

Theoretically, the data transmission bandwidth of the dual-channel storage management system is equal to the sum of the data transmission bandwidth of storage channel-1 and the data transmission bandwidth of storage channel-2. However, in fact, since the data transmission line of memory channel-1 and the data transmission line of memory channel-2 often do not transmit data at the same time, even the data transmission frequency line of memory channel-1 will not always be in a busy state, so its actual The total data transmission bandwidth is usually smaller than the theoretical value. Therefore, when the data transmission lines of storage channel-1 and storage channel-2 are used unevenly, that is, one set of lines is busy and the other set of lines is idle, the resources of the storage management system are wasted. In addition, since the booting devices 20 and 22 are required to share the same set of storage channels-2, problems such as low efficiency and inability to perform parallel processing encountered in single-channel storage management systems are still encountered.

The object of the present invention is to provide a storage management system with storage channels to provide the capability required by the parallel processing system.

Another object of the present invention is to provide a storage management system with storage channels, which can make more effective use of the bandwidth of the storage management system.

To achieve the above object, the present invention provides a multi-channel storage management system for accessing storage devices in a parallel processing manner in response to system requirements. The feature is that the multi-channel storage management system includes at least: several storage channels , interleaving addressing the storage device and forming an independent data access library with an independent data bus, the storage channel provides an access path for independently accessing the interleaved addressing area of the storage device according to the system requirements; the scheduling device is required, which simultaneously sends said system request to said memory channel in response to said system request; and a read request recorder coupled to said request dispatcher which, when said system request is read from said memory channel When storing data, the readout requires the recorder to record the original sequence required by the system, so that the storage channel can return the data in the original sequence to respond to the system requirement.

The advantage of the storage management system of the present invention is that the probability of page misses is reduced by interleaving the addressing storage device. When the capacity of each interleaving addressing area of the storage device is smaller, the use of each storage channel will be more even , so in the storage management system of the present invention, almost all the bandwidth can be utilized at the same time; the capability required by the parallel processing system is provided.

In order to better understand the purpose, features and advantages of the present invention, preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 is a functional block diagram of a traditional single-channel storage management system;

Fig. 2 is a functional block diagram of a traditional dual-channel storage management system;

Fig. 3 is the functional block diagram of the first embodiment of the multi-channel storage management system of the present invention;

Fig. 4 is a schematic diagram showing how the storage channels of the present invention interleave addressing storage devices;

Figure 5 is a schematic diagram showing the original sequence of how the read request recorder of the present invention records system requests;

Fig. 6 is a schematic diagram showing how the request scheduling device of the present invention sends system requests to storage channels;

FIG. 7 is a schematic diagram showing how the read data sorting device of the present invention sorts the returned data according to the original order;

8 is a functional block diagram of a second embodiment of the multi-channel storage management system of the present invention;

FIG. 9 is a schematic diagram showing how the multi-channel storage management system of the present invention handles multiple system requirements simultaneously.

The invention discloses a storage management device with multiple storage channels, which is used to serve multiple request activation devices in a parallel processing manner and improve the efficiency of accessing the storage device. The spirit of the present invention is described below with several preferred embodiments.

Referring to FIG. 3 , the first embodiment of the multi-channel storage management system (hereinafter referred to as the storage management system) of the present invention is shown in the figure. The storage management system includes several request activation devices 40 , 42 , 44 , 46 , storage channels 32 , 34 , 36 , 38 , and a channel control device 30 . It should be mentioned here that the so-called storage channel refers to a data access bank that transmits specific address storage units through a set of independent data transmission lines to provide access paths for storage devices (such as DRAM). The storage channels 32 , 34 , 36 , and 38 address the storage devices in an interleaved manner, so the data stored therein will also be interleaved in the storage channels.

Please refer to FIG. 4 , which shows a schematic diagram of how to interleave addressing memory devices with memory channels. Taking three storage channels as an example, the channel-1, channel-2, and channel-3 interleaved addressing storage device 47, its linear address relative to the interleaved addressing area of the storage channel is as follows: (C×I~C×i +1)×N, (C×j+1~C×i+2)×N, (C×i+2~C×i+3)×N. N represents the capacity of the interleaved addressing area, and C represents the number of storage channels, which is three in this example. In addition, M represents the total capacity of the storage device 47, and i is the sequence 0, 1, 2, . . . , [M/(C×N)]−1. Incidentally, the size of the capacity N of the interleaved addressing area can be controlled in a programmable manner through the driver program of the storage management system.

Continuing to refer to FIG. 3 , the requesting device 40 , 42 , 44 , 46 represents any software program that requires access to the memory channel 32 , 34 , 36 , 38 . The address marked in the system request generated by the requesting device 40, 42, 44, 46 is a linear address (Linear Address). When the request scheduling device 50 receives these system requests, it will decode its linear addresses into channel addresses (Channel Address), and deliver the system requests to the storage channels 32, 34, 36, 38 according to these channel addresses, and the storage channels The server will request activation of the device in response to these system requests. Generally speaking, system requirements can be divided into writing requirements and reading requirements, and the processing methods for these two types of system requirements are described later.

The channel control device 30 includes a request scheduling device 50 and channel queues 58, 56, 54, 52, wherein the request scheduling device 50 is used to send system requests to its target storage channels, and the channel queues 58, 56, 54, 52 are used to to wait for system requests to be sent to the memory channel. When the system requires data to be written in the storage channel, the system request will be accompanied by the data to be written, and will be transmitted to the storage channel 32, 34, 36, 38. When the storage channel 32, 34, 36, 38 receives the system request, it will directly write data into itself, and complete the program of writing data.

Since the order in which data is written to the memory channels 32, 34, 36, 38 is insignificant, this makes handling write requests relatively simple. However, for the read request, whether the order of the data returned by the memory channels 32, 34, 36, 38 is correct or not is related to the success or failure of the data read by the enabling devices 40, 42, 44, 46. When the system requests to read out the data in the memory channels 32, 34, 36, 38, the request scheduling device 50 will send these system requests to its target memory channels 32, 34, 36, 38, and the read request recorder 60 will The original order of these system requirements is noted. Then the storage channels 32 , 34 , 36 , 38 respond to these system requirements, and send the data to be read to the read data sorting device 62 . At this time, the read data sorting device 62 will sort the received data according to the original order recorded by the read request recorder 60, and send back the corresponding request starting devices 40, 42, 44, 46 in sequence. , to ensure the correctness of its data order.

5 to 7 show how the storage management system of the present invention ensures that the sequence of data read by the boot device is correct. Referring first to Fig. 5, a list of read requests is shown, wherein the first read request comes from the request activation device-A, and its identification number is O, and the second read request also comes from the request activation device-A, and its identification number is O. The number is 1, and so on for the rest. As for the starter-A, a total of 0A, 1A, 4A, and 6A have been issued, and their identification numbers are 0, 1, 4, and 6 respectively. The so-called identification numbers represent the order of the readout requests issued, and these identification numbers are also All are recorded by the read request recorder 60 (see FIG. 3). Similarly, the read request recorder also records the identification numbers of the read requests issued by the initiating device-B, initiating device-C, and initiating device-D.

Referring next to FIG. 6 , the request scheduling device 50 divides the read requests into two groups 57 and 55 , and transmits them to the storage channel-1 and the storage channel-2 through the channel queue-1 and the channel queue-2 respectively. The first set of read requests 57 includes 0A, 2B, 4A, and 7D, while the second set of read requests 55 includes 1A, 3C, 5B, and 1A.

Referring again to FIG. 7 , the storage channel-1 transmits the data to be read out by the first set of readout requests 57 to the readout data sorting device 62 through the data readout queue-1 located in the data readout sorting device 62 . Similarly, the storage channel-2 transmits the data to be read out by the second group of readout requests 55 to the readout data sorting device 62 through the data readout bit column-2 located in the data readout sorting device 62 . The read data sorting device 62 will sort the data according to the identification numbers, and then send back to the corresponding request activation device according to the original order.

Fig. 8 shows a second embodiment of the multi-channel storage management system (hereinafter referred to as the storage management system) of the present invention. The storage management system includes several request initiation devices 72 , 74 , 76 , 78 , storage channels 80 , 82 , 84 , 86 , and a channel control device 70 . The channel control device 70 delivers the system request to the memory channels 80 , 82 , 84 , and 86 by decoding the linear address of the system request into a channel address.

The channel control device 70 includes a request scheduling device 88, a read request recorder 90, and channel queues 98, 96, 94, 92, wherein the read request recorder 90 is electrically connected to the request schedule device 88, and is used for recording The original sequence of system requests issued by the request initiators 72 , 74 , 76 , 78 . The request scheduling device 70 is used to send system requests to its own storage channel, and the channel queues 98, 96, 94, 92 are used to wait for system requests sent to the storage channel.

When the system requires data to be written in the storage channel 80, 82, 84, 86, the system request will be accompanied by the data to be written, through the request scheduling device 90, through the channel queue 98, 96, 94, 92, and Transfer to storage channels 80,82,84,86. When the storage channel 80, 82, 84, 86 receives the system request, it will directly write the data into itself, and complete the procedure of writing the data. When the system requests to read the data in the storage channels 80, 82, 84, 86, the read request recorder 90 will record the original sequence of these system requests by adding identification numbers to the system requests. Since the read request recorder 90 only allows the system request with the earliest identification number to pass through to the memory channel, it can be ensured that the data returned by the memory channel will be in its original order.

An advantage of the memory management system of the present invention is that the probability of page misses is reduced by interleaving addressing of memory devices. As mentioned above, page misses will consume a lot of processing time of the traditional single-channel memory management system, or dual-channel memory management system. When the number of storage channels is larger, the probability of page misses is smaller. When the capacity of each interleaved addressing area of the storage device is smaller, the use of each storage channel will be more even. Therefore, in the storage management system of the present invention, almost all the bandwidth can be utilized simultaneously.

Another advantage of the storage management system of the present invention is that it provides the capability of parallel processing system requirements. Taking the storage management system with three storage channels shown in Figure 9 as an example, at time 1, channel-1, channel-2, and channel-3 will be able to simultaneously process requests from the requesting device-A and the requesting device -D, system request issued by requesting device-E. Similarly, at time 2, channel-1, channel-2, and channel-3 can simultaneously process the system requests issued by the request activation device-C, request activation device-B, and request activation device-F.

The present invention is described above with a preferred embodiment, which is only used to help understand the implementation of the present invention, and is not intended to limit the spirit of the present invention, and those familiar with the technical field will not depart from the present invention after comprehending the spirit of the present invention. Within the scope of the spirit, various equivalent modifications and equivalent replacements can also be made, and the following equivalent modifications and replacements are all within the scope of patent protection of the present invention.

Claims (18)

1. multichannel memory management system requires and with the mode accessing storage devices of parallel processing, it is characterized in that described multichannel memory management system comprises at least in order to responding system:

Several memory channels, the staggered described memory storage of addressing is also formed independently data access storehouse with the independent data bus, and described memory channel provides the access path in the staggered addressing district of the described memory storage of independent access by described system requirements;

Require dispatching device, it sends described system requirements simultaneously to described memory channel in response to described system requirements; And

Read and require register, it and the described dispatching device that requires are coupled, when described system requirements from described memory channel during sense data, the described original order that requires the described system requirements of recorder trace of reading is beneficial to described memory channel described data is passed back to respond described system requirements by described original order.

2. multichannel memory management system as claimed in claim 1, it is characterized in that, also comprise a plurality of in described memory channel and the described channel queue that requires between the dispatching device, in order to wait the described system requirements that requires dispatching device to be issued to described memory channel by described.

3. multichannel memory management system as claimed in claim 1, it is characterized in that, also comprise and the described sense data collator that requires register and described memory channel to be coupled of reading, in order to wait and to sort from the described data that described memory channel sent according to described original order.

4. multichannel memory management system as claimed in claim 3 is characterized in that, also comprises a plurality of starter gears that require, in order to send described system requirements to the described dispatching device that requires.

5. multichannel memory management system as claimed in claim 4 is characterized in that, described reading requires register to write down the original order that described system requires by the identification number that produces corresponding described system requirement.

6. multichannel memory management system as claimed in claim 5 is characterized in that, described sense data collator sorts and described data are sent to the described starter gear that requires described data according to described identification number.

7. multichannel memory management system as claimed in claim 1 is characterized in that, also comprises system driver, determines the memory capacity in described staggered addressing district to utilize programmable method.

8. multichannel memory management system as claimed in claim 1, it is characterized in that, the described starter gear that requires produces the linear address of described system requirements corresponding to physical storage areas in the described memory storage, describedly require dispatching device then to receive and the described linear address of decoding, to produce channel address and then to send described system requirements to described memory channel.

9. multichannel memory management system requires and with the mode accessing storage devices of parallel processing, it is characterized in that described multichannel memory management system comprises at least in order to responding system:

Several require starter gear, in order to produce described system requirements;

Several memory channels, the staggered described memory storage of addressing is also formed independently data access storehouse with the independent data bus, and described memory channel provides the access path in the staggered addressing district of the described memory storage of independent access by described system requirements;

Require dispatching device, send described system requirements simultaneously in response to described system requirements to described memory channel; And

Read and require register, form electric connection with the described dispatching device that requires, when described system requirements in described memory channel during sense data, the described original order that requires register to write down described system requirements by the mode of the identification number that produces corresponding described system requirements of reading, described reading requires register only to allow to read order described system requirements the earliest by being passed to described memory channel at every turn, and, can be sent to the described starter gear that requires according to described original order with these described data of guaranteeing the described system requirements of response passed back by described memory channel.

10. multichannel memory management system as claimed in claim 9, it is characterized in that, also comprise a plurality of in described memory channel and the described channel queue that requires between the dispatching device, in order to wait the described system requirements that requires dispatching device to be issued to described memory channel by described.

11. multichannel memory management system as claimed in claim 9 is characterized in that, also comprises system driver, determines the memory capacity in described staggered addressing district to utilize programmable method.

12. multichannel memory management system as claimed in claim 9, it is characterized in that, the described starter gear that requires produces described system requirements, linear address corresponding to physical storage areas in the described memory storage, describedly require dispatching device then to receive and the described linear address of decoding, to produce the passage address and then to send described system requirements to described memory channel.

13. a multichannel memory management system with the mode accessing storage devices of parallel processing, is characterized in that described multichannel memory management system comprises at least in order to the responding system requirement:

Several require starter gear, in order to produce described system requirements:

Several memory channels, the staggered described memory storage of addressing is also formed independently data access storehouse with the independent data bus, and described memory channel provides an access path in the staggered addressing district of the described memory storage of independent access in response to described system requirements:

Channel controller, it comprises:

Require dispatching device, send described system requirements simultaneously in response to described system requirements to described memory channel,

Read and require register, it and the described dispatching device that requires are coupled, when described system requirements in described memory channel during sense data, the described original order that requires the described system requirements of recorder trace of reading, and

The sense data collator, require register and described memory channel to be coupled with described reading, sort from the described data that described memory channel sent in order to wait and to comply with described original order, and described data are sent to the described starter gear that requires according to described original order.

14. multichannel memory management system as claim 13, it is characterized in that, also inclusion is a plurality of in described memory channel and the described channel queue that requires between the dispatching device, in order to wait the described system requirements that requires dispatching device to be issued to described memory channel by described.

15. the multichannel memory management system as claim 13 is characterized in that, the described original order that requires register to write down described system requirements by the identification number that produces corresponding described system requirements of reading.

16. the multichannel memory management system as claim 15 is characterized in that, described sense data collator sorts and described data is sent to the described starter gear that requires described data according to described identification number.

17. the multichannel memory management system as claim 13 is characterized in that, also comprises system driver, determines the memory capacity in described staggered addressing district to utilize programmable method.

18. multichannel memory management system as claim 13, it is characterized in that, the described starter gear that requires produces described system requirements, linear address corresponding to physical storage areas in the described memory storage, describedly require dispatching device then to receive and the described linear address of decoding, to produce channel address and then to send described system requirements to described memory channel.

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