CN1879070A - Hybrid switched mode/linear power amplifier power supply for use in polar transmitter - Google Patents

Abstract

In one aspect, the present invention provides a DC-DC converter having a switching-mode section coupled between a DC source and a load, the switching-mode section providing an output power of amount x; and it further having a linear-mode section coupled in parallel with the switching-mode section between the DC source and the load, the linear-mode section providing an output power of amount y. x is preferably greater than y, and the ratio of x to y can be optimized for specific application constraints. In another aspect, the present invention provides an RF transmitter (TX) coupled to an antenna. The TX has a polarized structure and includes an amplitude modulation (AM) path coupled to a power amplifier (PA) supply and a phase modulation (PM) path coupled to the PA input.

Description

Hybrid Switching/Linear Power Amplifier Power Supplies for Polar Transmitters

technical field

The present invention relates generally to DC-DC converter power supplies, and more particularly to switched-mode power supplies (SMPS) suitable for use in radio frequency (RF) transmitters, such as those used in cellular mobile stations implementing envelope recovery ( ER) RF transmitters RF transmitters, also known as polar transmitters, in which the sign is represented using phase and magnitude components, rather than complex in-phase/quadrature-phase (I/Q) components.

Background technique

Figure 1A is a simplified block diagram showing the structure of an ER transmitter (TX) 1 including an amplitude modulation (AM) chain and a phase modulation (PM) chain. The bits to be transmitted are input to a bit-to-polarity converter 2, which outputs an amplitude signal via a propagation delay (PD) 3 to an amplitude modulator (AM) 4 . AM4 (after digital-to-analog conversion) provides a signal for controlling the output level of a TX power amplifier (PA) 6 by using a controllable power supply 5 . The bit-to-polarity converter 2 also outputs the phase signal via a propagation delay 3 to a frequency modulator (FM) 7 which in turn outputs the signal via a phase locked loop (PLL) 8 to the input of PA6. The transmitted signal at the antenna 9 is thus generated by using both phase and amplitude components. Advantages obtainable using ER emitter structures include smaller size and improved efficiency.

It can be understood that the power supply voltage of PA6 should be amplitude modulated with high efficiency and wide bandwidth.

Now discussing the power supply 5 and PA6 in more detail, high-efficiency TX structures such as polar-loop modulated TX generally rely on efficient but non-linear power amplifiers such as switched-mode power amplifiers (SMPAs), such as Class E SMPAs, or they typically rely on For linear power amplifiers driven into saturation, such as saturated class B power amplifiers. In these configurations, amplitude information is provided by modulating the supply voltage of PA6 by means of a power regulator connected between a DC supply or power source, usually a battery, and PA6, as shown in more detail in FIG. 1B .

In FIG. 1B , the output V _pa of the power supply 5 should be able to track the rapidly changing reference voltage V _m . Thus, the power supply 5 must comply with certain bandwidth specifications. The required bandwidth depends on the system using transmitter 1. For example, the required bandwidth exceeds 1 MHz (~17 dB dynamic range for a given power level) for EDGE systems (8PSK modulation), and exceeds 15 MHz (for a given power level) for WCDMA (Wideband Code Division Multiple Access) systems. flat, dynamic range ~ 47dB). Understandably, these are extremely challenging requirements. Figure 2 shows a typical waveform that must be tracked (the RF envelope in an EDGE system), where the modulation voltage (V _m ) is shown varying from minimum to peak (typical rms and average values are also shown).

Note that in the GSM system the modulation is GMSK with a constant RF envelope, so there is no special constraint on the power supply 5 in terms of bandwidth for a given power level.

In general, there are two main techniques for implementing power supply 5 . The first technique shown in FIG. 3 uses a linear regulator implemented with a summing junction 10 , a driver 12 and a power device 14 . Although high bandwidth is available, the efficiency is low due to the voltage drop (V _drop ) across the power device 14 .

The second technique shown in Figure 4 would use a switching regulator. This technique has not previously allowed use in polar or ER transmitters, in which step-down switching regulator 16 would comprise a buck or similar converter 18 and voltage-mode control circuit 20 . PA6 is shown represented by its equivalent resistance _Rpa . While the efficiency of switching regulator 16 can be very high, the required bandwidth will be difficult or impossible to obtain. More specifically, if one were to attempt to use a switching regulator 16, a very high switching frequency would be required (eg at least about 5 times the required bandwidth or 5-10 MHz or more for EDGE and over 80 MHz for WCDMA). While a switching frequency of 5-10MHz would be technically very challenging (typical commercial DC-DC converters operate at a maximum switching frequency in the range of about 1-2MHz), for example a DC-DC converter with a switching frequency of 100MHz would be This is currently impractical to implement, especially in low-cost, mass-produced devices such as cellular telephones and personal communication terminals.

In US 6,377,784B2, Earl McCune (Tropian, Inc.), "High-Efficiency Modulation RF Amplifier" (High-Efficiency Modulation RF Amplifier), there is a high-efficiency (e.g. hard-limited or switched-mode) power amplifier purportedly described Efficient power control, thereby achieving the desired modulation. In one embodiment, the spread between the desired modulation maximum frequency and the switching DC-DC converter operating frequency is said to be reduced by using an active linear regulator after the switching converter. Linear regulators are said to be designed to control the operating voltage of a power amplifier with sufficient bandwidth to reliably reproduce the desired AM waveform. Linear regulators are also said to be designed to reject changes in their input voltage even when the output voltage changes in response to an applied control signal. Suppression is said to occur even if changes in the input voltage are of comparable or even lower frequency than the frequency of changes in the controlled output. AM is also said to be achievable by directly or effectively varying the operating voltage across the power amplifier while achieving high efficiency in the conversion of the main DC source to the AM output signal. The high efficiency is said to be enhanced by allowing the switching DC-DC converter to also vary its output voltage so that the voltage drop across the linear regulator remains at a low and relatively constant level. Time Division Multiple Access (TDMA) burst capability is said to be combined with effective amplitude modulation, under the control of these combined functions, and average output power level variation as commanded by the communication system is also combined within the same structure.

Contents of the invention

The above and other problems are overcome, and other advantages are realized, in accordance with presently preferred embodiments of the teachings herein.

In one aspect, the present invention provides a DC-DC converter having a switch-mode portion coupled between a DC source and a load, the switch-mode portion providing x amount of output power; and having a connection between the DC source and the load The linear mode section coupled in parallel with the switched mode section provides y amount of output power. In a preferred embodiment, x is preferably greater than y, and the ratio of x to y can be optimized for particular application constraints. Additionally, linear-mode parts exhibit faster response times to desired changes in output voltage than switch-mode parts. In one embodiment, the linear mode section includes at least one power operational amplifier operating as a variable voltage source, while in another embodiment the linear mode section includes at least one power operational transconductance amplifier operating as a variable current source.

In yet another aspect, the present invention provides an RF transmitter (TX) coupled to an antenna. The TX has a polar structure and includes an amplitude modulation (AM) path coupled to a power amplifier (PA) supply and a phase modulation (PM) path coupled to the PA input. The power supply is constructed with a switch mode section coupled between the battery and the PA, the switch mode section providing x amount of output power, and a linear mode section coupled in parallel with the switch mode section between the battery and the PA. The linear mode section provides y amounts of output power, where x is preferably greater than y, and the ratio of x to y can be optimized for specific application constraints. Preferably, the linear mode part exhibits a faster response time to a desired change in output voltage than the switch mode part.

In yet another aspect, the present invention provides a method of operating an RF TX having a polar structure comprising an AM path coupled to a PA power supply and a PM path coupled to a PA input, the method comprising: providing a power supply To include a switch-mode section coupled between a power source and the PA, the switch-mode section providing x amount of output power; coupling a linear-mode section in parallel with the switch-mode section between the power source and the PA, the linear-mode section Provides y amount of output power, where x is preferably greater than y, and where the ratio of x to y can be optimized for specific application constraints, and where the linear mode part exhibits a faster response time to desired changes in output voltage than the switch mode part.

In operation, the power supply provides higher power conversion efficiency than pure linear voltage regulator based power supplies, while also providing a wider operating bandwidth than pure switching mode based power supplies.

Description of drawings

The foregoing and other aspects of these teachings will become more apparent from the following detailed description of the preferred embodiments when read in conjunction with the accompanying drawings, in which:

Figure 1A is a block diagram of a conventional ER RF transmitter;

Figure 1B is a block diagram of a conventional SMPA provided with a mains amplitude modulated voltage;

Figure 2 is a waveform diagram showing a typical example of the reference voltage V _m that the Figures 1A and 1B power supplies must track;

Figures 3A and 3B show a conventional example of a linear voltage regulator providing a PA;

Figures 4A and 4B show an example of a switching regulator providing a PA;

Figure 5 is a block diagram of a PA provided by a hybrid voltage regulator in accordance with the present invention; where the linear portion of the hybrid voltage regulator preferably handles only a small fraction of the required output power and provides the necessary bandwidth, while the switch-mode portion preferably operates at high efficiency Provides most of the output power.

6A-6F show simplified diagrams of embodiments of the hybrid voltage regulator shown in FIG. 5;

Figures 7A and 7B are collectively referred to as Figure 7 and are related to the circuit shown in Figure 6A, wherein Figure 7A shows the general circuit concept and Figure 7B shows the switch section in more detail;

Figure 8 shows waveforms corresponding to the operation of the circuit of Figure 7;

Figure 9 also shows waveforms corresponding to the operation of the circuit of Figure 7;

Figures 10A and 10B are collectively referred to as Figure 10, and relate to the circuit shown in Figure 6B, wherein Figure 10A shows the general circuit concept, while Figure 10B shows the switch section in more detail;

Figure 11 shows waveforms corresponding to the operation of the circuit of Figure 10;

Figure 12 also shows waveforms corresponding to the operation of the circuit of Figure 10;

Figures 13A and 13B are collectively referred to as Figure 13, and relate to the circuits shown in Figures 6C and 6D, wherein Figure 13A shows the general circuit concept, while Figure 13B shows the switch section in more detail;

Figure 14 shows waveforms corresponding to the operation of the circuit of Figure 13;

Figure 15 also shows waveforms corresponding to the operation of the circuit of Figure 13;

Figures 16A and 16B are collectively referred to as Figure 16 and relate to the circuits shown in Figures 6E and 6F, where Figure 16A shows the general circuit concept and Figure 16B shows the switch section in more detail;

Figure 17 shows waveforms corresponding to the operation of the circuit of Figure 16;

Figure 18 also shows waveforms corresponding to the operation of the circuit of Figure 16;

FIGS. 19A and 19B, collectively referred to as FIG. 19, show an equivalent circuit diagram of a voltage-controlled voltage source (VCVS) and a VCVS circuit implemented as a power operational amplifier (POA), respectively;

20A and 20B, collectively referred to as FIG. 20 , respectively show an equivalent circuit diagram of a voltage-controlled current source (VCCS) and a VCCS circuit implemented as an operational transconductance amplifier (OTA);

Fig. 21 shows a first control configuration in which both the switching part and the linear part operate in closed loop and the modulating signal _Vm is used as a reference;

Figure 22 shows a second control configuration in which both the switching section and the linear section operate in a closed loop, wherein the linear section references the modulating signal _Vm and the switching section references the output of the linear section;

Fig. 23 shows a third control configuration in which only the linear section operates in closed loop with the modulating signal _V as reference, and in which the switching section operates in open loop and only the modulating signal _V information is used to generate the duty cycle of the switching section;

Figure 24 also shows the parallel connection of a switching regulator and a linear regulator via an auxiliary inductor _L1 and (optionally) an auxiliary capacitor _C1 according to an embodiment of the present invention;

25A and 25B are collectively referred to as FIG. 25, showing a control block diagram according to the embodiment shown in FIG. 24, wherein in FIG. 25A, both the switching regulator and the linear regulator are masters, and in FIG. master, switching regulator as slave;

26A and 26B, collectively referred to as FIG. 26, show a first multi-mode (multi-PA) control block diagram according to the embodiment shown in FIG. , the switching regulator and the linear regulator are both masters, and in Figure 26B, the linear regulator is the master and the switching regulator is the slave;

Figures 27A and 27B, collectively referred to as Figure 27, show a second multi-mode control block diagram according to the embodiment shown in Figure 24, wherein the GSM/EDGE PA is connected at the output of the switching regulator and the WCDMA PA is connected at the output of the linear regulator terminal, where in Figure 27A both the switching regulator and the linear regulator are masters, and in Figure 27B the linear regulator is the master and the switching regulator is the slave (in WCDMA mode only);

Figure 28 shows the SMPA as (a) a block diagram representation, (b) modeled by its equivalent DC resistance _Rpa , and ₍ c) represented by its equivalent DC resistance _Rpa in parallel with a capacitance Cpa used for PA stability simulation;

Figures 29A and 29B, collectively referred to as Figure 29, show a third multi-mode control block diagram according to the embodiment shown in Figure 24; wherein the GSM/EDGE PA and the WCDMA PA are respectively connected to separate power lines associated with the two linear regulators, where in FIG. 29A the switching regulator and each linear regulator are masters, and in FIG. 28B the linear regulators are each masters and the switching regulators are slaves (in WCDMA mode only); and

30A and 30B, collectively referred to as FIG. 30, show a fourth multi-mode control block diagram according to the embodiment shown in FIG. independent power lines associated with each linear regulator, where in Figure 30A the switching regulator and each linear regulator are masters, and in Figure 30B the linear regulators are both masters and the switching regulators are slaves ( only in WCDMA and CDMA mode).

Detailed ways

Referring to FIG. 5, the present invention provides a hybrid voltage regulator or power supply 30 that combines a switching section 32 that preferably handles most of the power with high efficiency but low bandwidth and a smaller portion that is best handled with low efficiency but high bandwidth. The linear part 34 of the required power. The resulting power supply has the required bandwidth and efficiency slightly lower than that of a pure switching power supply but still much higher than that of a pure linear regulator. The resulting hybrid power supply 30 provides an improved output voltage quality since the linear section 34 can be used to compensate for the output voltage ripple typically associated with a pure switching power supply. This is an important advantage since excess output voltage ripple can adversely affect the output spectrum of the PA 6.

It is to be noted that in principle the amount of power (x) handled by the switching section 32 is greater than the amount of power (y) handled by the linear section 34 . This is usually an ideal situation, and in practice, x is much larger than y in many embodiments. However, this relationship between the power handled by the switching section 32 and the linear section 34 is not to be considered a limitation of the preferred embodiment of the present invention. In principle, it is desirable to maximize the ratio of x to the total power: the larger this ratio, the higher the efficiency. However, the actual ratio achieved in a given application may be a function of one or more of the following factors and considerations:

(a) intended application (RF system details such as spectrum of RF envelope, amplitude of high frequency AC components, etc.); and

(b) An implementation in which the amount of power handled by the switching section 32 and the amount of power handled by the linear section 34 can be decided to some extent. For example, in EDGE, by using a 6-7 MHz switching frequency, almost all the power can be handled by the switching section 32, or by using a lower switching converter operating eg at 1 MHz, less power can be handled. In some cases, for example at very low power, it is also possible to disable the switching part 32 and use only the linear part 34, in which case the relationship x>y does not apply at all.

(c) Also to be considered may be a tradeoff between efficiency and implementation complexity, since it is usually simpler to implement a slow switching converter, but then reduces efficiency due to the larger portion of the power that needs to be handled by the linear section 34 .

(d) Also to be considered are tradeoffs that may be to optimize overall efficiency. For example, a switch section 32 with a very high switching frequency and high bandwidth can handle most of the power in a given application (x is much larger than y), but the processing in the switch section 32 may become overwhelmed by the extremely high switching frequency low efficiency. Therefore, it may be more beneficial to try to optimize the overall efficiency by using a lower switching frequency in the switching section 32 to achieve better efficiency as a trade-off between handling a lower amount of energy in the switching section 32 .

Therefore, in general, the power fraction x handled by the switch section 32 is preferably greater than the power fraction y handled by the linear section 34, and is also preferred by a given application and possibly also by a particular mode of operation (such as in the above-mentioned low power mode, where all The constraints imposed by the power can be handled by the linear part 34) optimize the ratio of x to y. Combinations can also be considered so that x is preferably greater than y, and the ratio of x to y can also be optimized for application constraints.

In fact, the invention can be realized by using a part topology of a switching converter (called "switching part" in Fig. 5) and connecting it in parallel with a voltage or current source (called "linear part" in Fig. 5). The output capacitor (C) of the buck (step-down) converter 18 of FIG. 4A is removed. In the buck converter 18, a capacitor acts as a voltage source to keep the output voltage constant. When the voltage at the output needs to increase, a large current must be supplied through the inductor (L) to meet the increased load and charge the capacitor (C) to the new higher voltage level. This operation slows down the switching regulator 16 and limits the bandwidth. However, if the capacitor (C) is replaced by a voltage source, the increased (or decreased) voltage level can be provided very quickly via the parallel voltage source of the linear section 34, while the slower switching section readjusts its operating point.

Referring again to FIG. 2, the switching section 32 provides the average level V _{m_av} and the linear section 34 provides the AC component superimposed on the average level.

An alternative embodiment based on the same concept uses a current source instead of a voltage source in the linear section 34 .

The voltage source of the linear section 34 can be implemented using a power operational amplifier (POA), while the current source of the linear section 34 can be implemented using a power operational transconductance amplifier (OTA). The operational amplifier of the linear section 34 can be supplied by the battery voltage (V _bat ) as shown in FIG. 5 . In an alternative presently more preferred embodiment (from an efficiency point of view), the operational amplifier of the linear section 34 is provided with the voltage V _{m_pk} of FIG. 2 , ie a voltage corresponding to the reference signal amplitude, where V _{m_pk} is always lower than V _bat . In practice, it is preferable to provide the operational amplifier of the linear section 34 with the voltage V _{m_pk} plus some margin (eg 0.2V) required to obtain correct operation of the linear stage.

6A-6F show various embodiments of the hybrid voltage regulator 30 shown in FIG. and 6F show the use of a variable current source 34B such as the power operational transconductance amplifier described above. Note that in FIG. 6C two variable voltage sources 34A and 34A' are used, and in FIG. 6D two variable voltage sources 34A and 34A' are capacitively coupled to the output power rail of switching section 32 via C1. Also note that in FIG. 6E, two variable current sources 34B and 34B' are used, and in FIG. 6F, two variable current sources 34B and 34B' are capacitively coupled via C1 to the output power rail.

Based on the above description, it can be appreciated that the use of the present invention allows the realization of an efficient PA power supply 30 for TX configurations, where the PA supply voltage needs to be amplitude modulated. Currently, this is only achievable by using inefficient linear regulators (see Figures 3A and 3B) as there are no commercial switching regulators known to the inventors that can provide the required bandwidth.

The above and other embodiments of the invention will now be described in further detail.

The circuit shown in Figure 7 is related to the circuit shown in Figure 6A, where Figure 7A shows the general circuit concept, and where Figure 7B shows the switch section 32 in more detail. The switching section 32 is obtained from a buck converter, which is a step-down switching DC-DC converter consisting of two switching devices and an LC filter. The switching devices shown as complementary MOS transistors (PMOS/NMOS) in FIG. 7B are alternately turned on with a duty cycle d (d=ratio of the time t _{on_PMOS} the upper switch is on to the switching period _TS ). The control signal having a duty cycle d can be obtained from an analog pulse width modulator (PWM) block 32A which converts the control voltage V _{ctrl_sw} to have a duty cycle d by comparing V _{ctrl_sw} with a sawtooth signal having a period T _s the PWM signal. The PWM signal fed to transistor driver stage 32B may also be generated by other methods, such as in a digital PWM block.

Conventional buck converters typically include an L-C output filter, where C is large enough so that the buck converter behaves like a voltage source. However, in presently preferred embodiments of the present invention, the filter capacitor is removed, or is retained, but with a very small capacitance. As such, component 32 is referred to herein as a "switching section" as opposed to a "switching converter". In reality, the physical circuit will have some filter capacitance, for example, the amount needed to ensure stability of the RFPA6. However, for the purposes of illustrating the invention, it is assumed that the capacitance (C) is much smaller than would be found in a conventional buck converter, such that the characteristics of the switching section 32 are primarily those of a current source rather than a voltage source.

More specifically, due to the inductor (L) (and no/very small capacitance C), the switching section 32 has the characteristics of a current source rather than a true voltage controlled current source (VCCS). An increase in the control voltage V _{ctrl_sw} determines an increase in the duty cycle d, which determines an increase in the average output voltage V _pa which in turn determines an increase in the PA6 current I _pa and thus the DC component of the inductor current _IL Increase. However, the absolute value of the PA6 current I _pa is not completely determined by the control voltage V _{ctrl_sw} , and is also determined by R _pa when I _pa =V _pa /R _pa . Thus, while this technique may operate "VCCS-like", it does not directly control the current flow, and is therefore referred to as "VCCS-like".

Linear section 34 operates as a voltage controlled voltage source (VCVS) 34A, and its output voltage V _o is controlled by differential voltage V _d through differential amplification _Ad .

More specifically, FIG. 7A shows this embodiment of the invention by assuming an ideal source: where the switch portion 32 acts like a current source, and the AND acts like a bidirectional (i.e., it can source and sink current) voltage-controlled voltage source. The linear sections 34 of 34A are connected in parallel. The linear section 34 acting as a voltage source sets the PA 6 voltage V _pa . The current i _sw of the switch part 32 is added to the current i _lin of the linear part 34 to form the PA6 current i _pa (R _pa represents the effective impedance of PA6). An optional DC blocking decoupling capacitor _Cd can be connected to ensure that the linear section 34 provides only the AC component.

Figure 7 shows that the switching section 32 is implemented by a step-down buck converter from which the output filter capacitor C has been eliminated or greatly reduced. The current i _sw of the switching part 32 is thus actually the inductor current i _L , resulting in a behavior substantially like a current source (the inductor L can be likened to a current source).

It is worth noting that the linear section 34 fixes the voltage level V _pa applied to the PA due to its nature as a voltage source, and there are means to control this voltage level. In addition, the linear section 34 is fast (wide bandwidth), thus making it possible to provide fast modulation of V _pa . Note also that VCVS 34A of linear section 34 is bi-directional, meaning that it can source and sink current.

As shown in Figure 19B, VCVS 34A may be implemented as a power operational amplifier (POA). The POA includes an operational amplifier (OPAMP) with a class A(B) stage capable of sinking/sourcing the required current. Figure 19B shows a Class B power stage consisting of transistors _Q1 and _Q2 , but the output stage design can be changed to improve performance. For example, the power stages can actually be implemented as Class AB stages to reduce crossover distortion.

As mentioned, an optional decoupling capacitor C _d may be introduced to ensure that only the AC current component is provided by the linear section 34 . However, in some cases it would be advantageous to allow the linear section 34 to also provide a DC component although this would result in more complex control. For example, where the switch section 32 may be disabled and where the PA6 current will only be provided by the linear section 34, it is expected that a DC component may be provided from the linear section 34 at a low power level. As another example, when _{Vpa_peak} is very close to a low battery voltage level such as 2.9V, such as 2.7V, and the switch section 32 cannot provide it, it is desirable to provide a DC component from the linear section 34 of this low battery voltage level . In such cases, the optional _Cd will be removed.

The operation of the circuit shown in FIG. 7A is illustrated by the simulated waveforms shown in FIG. 8 , and the operation of the circuit shown in FIG. 7B is illustrated by the simulated waveforms shown in FIG. 9 .

The top waveform in Fig. 8 shows the resulting PA6 voltage V _pa . The PA6 voltage V _pa is set by a linear stage 34 with voltage source characteristics. In this example, V _pa has a DC component (2V) plus an AC component shown as a 15MHz voltage sine wave representing a fast modulation. The second waveform from the top shows the current component of the switching section 32, the constant current i _sw . The third waveform from the top shows the current component of the linear portion, the AC component i _lin (15MHz sine wave). As mentioned, the linear section 34 operates as a bi-directional voltage source, ie, it can both source and sink current. The bottom waveform shows that the resulting PA6 current i _pa has a DC component from the switching section 32 and an AC component from the linear section 34 .

Note that in FIG. 8, one set of waveforms is for a sine wave of zero amplitude (no component from the linear portion 34, labeled "A"), and another set is for a sine wave of non-zero amplitude (to show the sine wave from Components of the linear order, denoted as "B"). The same convention is used in the waveform diagrams of Figures 9, 11, 12, 14, 15, 17, and 18.

Figure 9 shows simulated waveforms to illustrate the operation of the circuit shown in Figure 7B. For this non-limiting example, assume that switching stage 32 has a switching frequency of 5 MHz and a duty cycle of 0.5. The top waveform shows the PWM 32A voltage applied across inductor L at node pwm. The second waveform from the top shows the resulting PA6 voltage V _pa . The PA6 voltage V _pa is set by a linear stage 34 with voltage source characteristics. In this example, V _pa has a DC component (2V) plus a 15MHz AC component (voltage sine wave) representing fast modulation. The third waveform from the top shows the current component of the switching section 32, that is, the inductor current i _L =i _sw . In this case, the current is not ideally a constant current as shown in Figure 8, but has the specific triangular shape encountered in switching converters. The switching section 32 provides a DC component and a triangular AC component (inductor current ripple). The fourth waveform from the top shows the current component of the linear portion 34, the AC component i _lin (15 MHz sine wave plus inductor current ripple compensation). Note that the linear section 34 provides not only a 15MHz sinusoidal component but also an AC component to compensate for the inductor current ripple (clearly seen from the lower waveform labeled AC _rip ). This is due to the voltage source nature of linear section 34, which acts as a bi-directional voltage source, sourcing and sinking current. The bottom waveform shows that the resulting PA6 current i _pa has a DC component from the switching section 32 and an AC component from the linear section 34 where the AC triangular component of the inductor current (third curve) is compensated by the linear stage 34 .

FIG. 10 shows an embodiment in which a voltage controlled current source (VCCS) 34B is used to form the linear section 34 . In general, the same considerations apply as in the Figure 7 embodiment, the only substantial difference being that VCCS itself cannot fix the PA6 voltage level. Instead, the PA6 voltage is determined by the total current injected into _Rpa . The linear section 34 may be implemented as an operational transconductance amplifier (OTA) as shown in FIG. 20B. In this simplified view, the collector current (Ic ₁ ) of Q ₁ in the differential pair is mirrored to I ₅ , while the collector current (Ic ₂ ) of Q ₂ is mirrored to I ₃ and subsequently to I ₄ . The output current is I _o =I ₅ -I ₄ and is proportional to the difference between the collector currents IC ₁ -IC ₂ which in turn is proportional to the differential voltage V _d . As mentioned, Figure 20B shows a simplified representation of the OTA. In practice, the purpose of circuit implementation will be to optimize the accuracy of the current mirror and obtain the linear characteristic I _o =gV _d .

The operation of the circuit shown in FIG. 10A is exemplified by the simulated waveforms shown in FIG. 11 , and the operation of the circuit shown in FIG. 10B is exemplified by the simulated waveforms shown in FIG. 12 .

In Fig. 11, the uppermost waveform shows the resulting PA6 voltage _Vpa . Assume that PA6 acts like a resistive load from a power supply point of view. Therefore, V _pa =R _pa (i _sw +i _lin ), ie, the PA6 voltage is set by the sum of the currents provided by the switching section 32 and the linear section 34 . In this example, R _pa is assumed to be equal to 2 ohms. Switching section 32 provides a DC component i _sw (eg, 1 amp), and linear section 34 provides an AC component i _lin , representing a rapidly modulated 15 MHz current sine wave. The second waveform from the top shows the current component of the switch section 32, that is, a constant current i _sw of 1 ampere. The third waveform from the top shows the current component of the linear portion 34, ie, the AC component i _lin (15 MHz current sine wave). The bottom waveform shows that the resulting PA6 current i _pa has a DC component from the switching section 32 and an AC component from the linear section 34 .

In Fig. 12, it is assumed that the switching stage 32 has a switching frequency = 5 MHz and a duty cycle = 0.5. The top waveform shows the PWM 32A voltage applied across inductor L at node pwm. The second waveform from the top shows the resulting PA6 voltage V _pa . As above, it is assumed that PA6 acts like a resistive load, and thus V _pa =R _pa (i _sw +i _lin ), ie the PA6 voltage is set by the sum of the currents provided by the switching section 32 and the linear section 34 . As mentioned above, R _pa is assumed to be equal to 2 ohms. The switching section provides a DC component i _sw (1 ampere) with a triangular AC component. The linear section provides the AC component i _lin , such as a 15MHz current sine wave representing a fast modulation. The third waveform from the top shows the current component of the switching section 32, that is, the inductor current i _L =i _sw . In this case, the current is not ideally a constant current as shown in Figure 11, but has a triangular shape as encountered in switching converters. The switching section 32 provides a DC component and a triangular AC component (inductor current ripple). The fourth waveform from the top shows the current component of the linear portion 34, ie, the AC component i _lin (15 MHz sinusoidal component). Note that in this case the linear section 34 provides only a 15MHz sinusoidal component, unlike the corresponding waveform of Figure 9 where an AC component compensating for the inductor current ripple is also seen. The bottom waveform shows that the resulting PA6 current i _pa has a DC component from the switch section 32 and an AC triangular component (as can be seen from the lower waveform labeled AC _rip ) and an AC component from the linear section 34 . Note that in this embodiment the AC delta component is not compensated by the linear stage 34 due to the current source characteristics of the linear stage 34, but it can be compensated by properly controlling VCCS.

The circuits shown in Figures 13 and 16 show a linear section 34 consisting of two VCCSs 34A and 34A' or two VCCSs 34B and 34B', respectively, sourcing current from V _bat and sinking current to ground. The operation is shown in the waveform diagrams of Figures 14 and 15 and Figures 17 and 18, respectively.

The circuit representations in Figures 13 and 16 and their corresponding waveforms show the source/sink behavior of the VCVS34A and VCCS 34B, respectively, and simulate the behavior of a power operational amplifier and a power transconductance amplifier, respectively. Note that the two VCVS 34A in Figure 13 are not active at the same time and are preferably placed in a high impedance state when not active.

More specifically, Figures 13A and 13B show this embodiment with ideal sources, and the explanations made above for the circuit of Figure 7 apply here as well. The difference between the circuits is that voltage sources VCVS 34A and 34A' are unidirectional (one sources current, the other sinks current) in the embodiment of FIG. 13, whereas voltage source 34A in FIG. 7 is bidirectional (sources and sinks) . A decoupling capacitor C _d may be included to ensure that the linear section 34 provides only an AC component.

For the analog waveform diagrams of FIGS. 14 and 15 , similar explanations as given above for FIGS. 8 and 9 apply, except that the component i _lin of the linear portion 34 is divided into i _aux1 (supply) and i _aux2 (sink). It should also be noted that the two voltage sources 34A and 34A' (source and sink) are preferably placed in a high impedance state when their respective currents are zero (ie, they are not active).

Figures 16A and 16B show this embodiment of the invention with ideal sources, and the explanations made above for the circuit of Figure 10 apply here as well. The difference between the circuits is that current sources VCCS 34B and 34B' are unidirectional (one sources current and the other sinks current) in the embodiment of FIG. ). A decoupling capacitor C _d may be included to ensure that the linear section 34 provides only an AC component.

For the analog waveform diagrams of FIGS. 17 and 18 , similar explanations as above for FIGS. 11 and 12 apply, except that the component i _lin of the linear portion 34 is divided into i _aux1 (supply) and i _aux2 (sink).

Note that Figures 7 and 10 are only representations of the power supply stage (switching section 32 and linear section 34) interconnections, without control being considered. The switching section 32 is shown as a component controlled by the control voltage V _ctrl . The linear portion 34 is shown as a component controlled by the differential voltage _Vd . Figures 21, 22 and 23 show three non-limiting examples of control techniques for closed control loops.

In FIG. 21, the switching section 32 operates by voltage mode control. The controller consists of a control part 36A which generates an error signal V _e1 and a part 36B having a frequency dependent characteristic G _c1 (s), which has as its input the error signal V _e1 and which will be used for the control voltage of the switching part 32 V _{ctrl_sw} as its output. The error voltage V _e1 is the difference between the reference voltage V _{ref_sw} as the modulation signal V _m and the feedback signal V _{feedback_sw} as the output voltage V _pa . In this case, the controller (components 36A, 36B) may be physically implemented as an operational amplifier with an RC compensation network to obtain the characteristic G _c1 (s).

The linear section 34 uses the modulation signal V _m as a reference V _{ref — lin} . The feedback voltage V _{feedback_lin} is the output voltage V _pa . The feedback voltage _{Vfeeaback_lin} can also be obtained before the decoupling capacitor _Cd (if present) as shown by the dashed line. The controller in this case is similar to the switching section 32, consisting of a part 38A generating an error signal V _e2 and a part 38B having a frequency-dependent characteristic G _c2 (s). Since the linear section 34A is actually best implemented with a power operational amplifier, as in FIG. 19B, it is therefore possible to obtain the characteristic _Gc2 (s) around it by adding an RC compensation network, as will be appreciated by those skilled in the art. Close the control loop. Note that VCVS 34A is included only to show the voltage source characteristics of linear stage 34, which is different from VCVS shown in FIG. The part labeled "Linear Section with Feedback" is actually a representation of a power op amp with an RC compensation network.

Note that when linear stage 34 is built with VCCS 34B (e.g., FIG. 10) and OTA as shown in FIG. 20B, the same considerations as above apply for closing the loop.

In Fig. 22, the only substantial difference compared to Fig. 21 is that the reference signal for the switching section 32 is taken from the output of the linear section 34 (before it if a decoupling capacitor is present). The same considerations apply when linear stage 34 uses VCCS 34B and OTA. In this embodiment, it is clear that the linear section 34 has as its reference the modulating signal V _m AM signal, while the switch section 32 has as its reference the output of the linear section 34 (ie it "slaves" to the linear section 34 ).

In the embodiment of Fig. 23, the switching section 32 operates in open loop, which means that only the modulation signal _Vm is used to generate the PWM duty cycle d, without the error signal _Ve1 = _Vm - _Vpa . This exemplary embodiment may be particularly useful when a dual loop control system as shown in FIGS. 21 and 22 may have stability issues. As noted above, the same considerations apply when linear stage 34 uses VCCS 34B and OTA.

The above description of the embodiment of the present invention provides a solution for realizing the fast modulation of the PA6 power supply, wherein the fast modulation is mainly provided by the linear part 34, and a buck converter with no or very small filter capacitor is used. It should be noted, however, that the concept of connecting a switching stage in parallel with a linear stage can be applied and is also useful in cases where a buck converter is used in conventional form, i.e. with a rather large output filter capacitance C and thus Voltage source characteristics. For example, an RF transmitter for the GSM/EDGE case could be based on a buck converter with voltage mode control, addressed by a fast switching converter. In this exemplary case, the necessary bandwidth can be achieved, however, the dynamics are not ideal (ie, the reference to output transfer function is not flat, but instead may exhibit peaking), and thus the reference tracking is not optimal. In addition, spurious RF signals are created by the output voltage ripple due to the switching action of the converter. Thus, the linear stage 34 connected in parallel with the buck converter can be used to compensate for the less than ideal dynamic characteristics of the switching converter by "helping" it and improving its tracking performance. In fact, the linear section 34 can also be used to improve (broaden) the bandwidth, but its main role is to correct the reference-to-output characteristic already provided by the switching section 32 . In addition, the linear section 34 can also compensate for the output voltage switching ripple (at least in a manner sufficient to satisfy RF spurious requirements) by injecting current to compensate for the inductor current ripple.

For the above reasons, it should be understood that the embodiment outlined in FIG. 5 can be extended to include circuit configurations in which the switching section 32 is a "normal" buck converter, i.e., the output filter capacitor C is sufficiently large so that the buck A converter acts like a voltage source.

Based on the above, it can be understood that the above-described embodiments of the present invention include circuit configurations based on a buck switching converter with no or very small filter capacitor C, i.e., where the output filter capacitor C is sufficiently small (or does not exist) , so the buck converter essentially acts like a current source, where the linear part 34 alone is able to determine the bandwidth of the PA6 power supply, i.e., even with a very slow switching part 32, the linear part 34 is also due to the absence/minimal buck conversion where the linear part 34 also provides the triangular AC component of the inductor current; and where the linear part 34 compensates for switching ripple.

Based on the foregoing, it will be appreciated that the above-described embodiments of the invention also include circuit configurations preferably based on a buck switching converter with a relatively large filter capacitance C, i.e., where the output filter capacitance C is sufficiently large that the buck conversion A converter essentially acts like a voltage source. Embodiments of the invention therefore also include circuit configurations based on "normal" buck converter circuit topologies with filter capacitors; where the bandwidth is primarily determined by the switching converter. In this case, the linear part 34 can be used to improve the bandwidth, but in a more limited way, since the bandwidth is actually limited by the filter capacitor C of the switching regulator. An important role of the linear section 34 in these embodiments is to assist and correct the dynamic characteristics of the switching section 32 (buck converter). In this embodiment, the linear portion 34 also compensates for switching ripple.

Aspects of the invention are based on the observation that in the exemplary EDGE and WCDMA envelopes the high frequency components have very low amplitude, while most of the energy is in the DC and low frequency components. The low bandwidth switching section 32 handles most of the power (DC and low frequency components) with high efficiency, while the wider bandwidth linear section 34 handles only a small portion of the power (corresponding to the high frequency components) with lower efficiency. Therefore, it is possible to achieve the required bandwidth and still provide good efficiency. Typically, the achievable efficiency is lower than that achieved with a purely switching power supply, but still much greater than that achieved with a purely linear regulator-based power supply.

The principles of the present invention are applicable regardless of the actual implementation of the switching section 32 and/or linear section 34, and are generally applicable to transmitter configurations where the PA6 supply voltage needs to be amplitude modulated. The teachings of the present invention are not limited to GSM/EDGE and WCDMA systems, but can also be extended to other systems (eg to CDMA systems). The teachings of the present invention are not limited to systems using class E PA6, but are also applicable to systems using other types of saturated PAs.

Other aspects of the invention described in more detail below are directed to coupling and feeding several PA6's in a multimode transmitter and control for the same.

Referring now to FIG. 24, there is shown an embodiment in which switching regulator 100 and linear regulator 102 are coupled via an additional inductor _L1 (i.e., in addition to conventional switching section 32 inductor L such as shown in FIG. 7B) and An (optional) capacitor C ₁ is coupled in parallel to the SMPA 104 (eg, Class E PA). The PA 104 supply voltage V _pa is programmed by the linear regulator 102 with high precision. However, due to low bandwidth, switching ripple and noise, the instantaneous output voltage V ₁ of the switching regulator 100 cannot be precisely fixed at the same value. Therefore, an additional inductor L ₁ is introduced to adjust the instantaneous voltage difference V _pa -V ₁ . The average voltage across _L1 must be zero, so the average value of _V1 is equal to _Vpa .

If decoupling capacitor _C1 is present, linear regulator 102 can provide only the AC component over a certain frequency range, which preferably compensates for the lower bandwidth of switching regulator 100 to obtain the desired overall bandwidth.

If C ₁ is not present, linear regulator 102 may also provide DC and low frequency components. This may be particularly advantageous under certain conditions, for example when the PA 104 voltage _Vpa should be as close as possible to the battery voltage _Vbat . One such case is the GSM case at maximum RF output power (the PA 104 requires a very small voltage, such as 2.7V) when using a low battery voltage (eg, 2.9V). In this case, the difference between the input voltage and the output voltage of any regulator inserted between the battery and PA 104 is extremely low (only 0.2V in this example). This is an extremely difficult value to obtain with switching regulator 100 (assuming a voltage drop across one power device plus two inductors L and L ₁ , duty cycle less than 100%). In this particular case, linear regulator 102 can be used to provide a supply voltage closer to the battery voltage, and thus linear regulator 102 provides all the power (DC component, and no capacitor C ₁ ). While in this particular case (GSM, maximum output power, low battery voltage) efficiency will not be affected due to the small voltage drop across linear regulator 102, at lower GSM power levels (i.e., linear regulator 102 greater pressure drop across 102), the efficiency will decrease. Therefore, at lower power levels, it is more advantageous to use the switching regulator 100 to provide all the power (DC component).

In FIG. 24 , the supply voltage for the linear regulator 102 is V _bat , the same voltage used for the switching regulator 100 . While this may be optimal from an implementation perspective, it may not be optimal from an efficiency perspective. At lower power levels, where V _{m_pk} is much lower than V _bat , the voltage drop across linear regulator 102 is large and its efficiency is low. Therefore, a more efficient technique (with high efficiency) is to pre-regulate the supply voltage of the linear regulator 102 at a certain level, for example 200-300 mV above the peak of the envelope V _{m_pk} (see FIG. 2 ).

From Figures 3 and 4 it can be seen that the two components of the hybrid regulator (switching and linear) have their own control loops. The overall control must be configured such that the two components complement each other. Figure 25 shows two possible control schemes.

In FIG. 25A, both regulators 100, 102 are "masters" in that each regulator takes the modulating signal _Vm as a reference and each regulator 100, 102 receives its feedback from its own output Signals (V _{feedback_sw} , V _{feedback_lin} ).

In Fig. 25B, the linear regulator 102 is "master", ie it takes the modulating signal _Vm as a reference and its own output as a feedback signal. The switching regulator 100 is "slave", which means it takes the voltage applied by the linear regulator 102 to the SMPA 104 as a reference signal, and tries to follow it as precisely as possible.

As described below, these embodiments of the invention are particularly suited for multi-mode transmitter applications.

As a first non-limiting example, in GSM the RF envelope is constant and therefore the voltage supplied to the PA 104 is constant and its level adjusted according to the required power level. The main function of the SMPA 104 power supply in this case is power control. In principle it will be sufficient to use only the switching regulator 100 . However, the switching action generates output voltage ripple and noise, which are seen as artifacts in the RF spectrum of the SMPA 104 output. In this mode, the linear regulator 102 can be used to compensate the output voltage ripple of the switching regulator 100 when needed. In this way, the specification of the output voltage ripple of the switching regulator 100 can also be relaxed. For example, if a typical voltage ripple specification of 5mV is assumed for switching regulator 100, this specification can also be relaxed to 50mV when ripple compensation is provided by linear regulator 102, allowing a smaller LC component in switching regulator 100 and/or faster dynamic characteristics of the switching regulator 100 . In this case, the switching regulator 100 handles almost all the required SMPA power, while the linear regulator 102 handles very little (only the processing required for ripple compensation).

In an EDGE system, or generally any system that includes a variable RF envelope with moderately high dynamics (eg, desired BW > 1 MHz), the main functions of the SMPA 104 power supply are power control and envelope tracking. It can be seen that a purely switching regulator with a switching frequency of 6-7MHz is able to track the EDGE RF envelope with relatively good accuracy. However, when using a pure switching regulator, the system is not robust and may exhibit, for example, peaking in the reference-to-output transfer function to the switching regulator 100 and SMPA 104 load variation with supply voltage (typically as the supply voltage decreases SMPA resistance increases) sensitive. In addition, as mentioned above, there is also the problem of output voltage ripple. In accordance with this aspect of the invention, the linear regulator 102 can be used to compensate for non-optimal dynamic characteristics of the switching regulator 100, SMPA 104 load variations and switching ripple, if desired. Most of the power is handled by the switching regulator 100 if the switching frequency of the switching regulator 100 is high enough to achieve good tracking performance. However, it is also possible to use a switching regulator 100 with a lower switching frequency and thus a lower bandwidth, in which case the proportion of power handled by the linear regulator 102 would increase to compensate for the reduction in handling by the switching regulator 100 .

In a WCDMA system, or any system that typically exhibits a variable RF envelope with high dynamics (eg, required BW > 15 MHz), the main functions of the SMPA 104 power supply are power control and envelope tracking. However, since the required bandwidth is much higher than that used for EDGE systems, it is not sufficient to use only the switching regulator 100 (in CMOS technology), and it becomes important to use the linear regulator 100 to provide the required bandwidth. As in the EDGE case, the linear regulator 102 can also compensate for switching ripple and SMPA 104 load variations.

Yet another utility gained from using embodiments of the present invention is the ability to provide multiple PAs for multi-mode operation. A non-limiting example is the Class E GSM/EDGE PA 104A and the Class E WCDMA PA 104B shown in Figure 26. In this case, all PAs 104A, 104B are connected to the same power supply line at the output of the linear regulator 102. This embodiment, like the embodiments of Figures 27, 29, and 30, assumes that there is a mechanism (e.g., a switch) that only activates one PA 104A or 104B at a time.

Note that PAs 104A and 104B are not limited to being Class E PAs, these are shown for convenience only. The same applies to the embodiments shown in FIGS. 27 , 29 and 30 .

In Fig. 26A, both regulators 100, 102 can be considered "masters", ie both have modulation signal _Vm as their reference, and both have their own corresponding output voltages to provide their feedback information. In FIG. 2B , linear regulator 102 is "master" and switching regulator 100 is "slave", meaning that its reference signal is the output V _pa of the linear regulator.

FIG. 27 shows an additional multimode configuration where the GSM/EDGE PA 104A is connected at the output of the switching regulator 100 (between the output and L ₁ ), and the WCDMA PA 104B is connected at the output of the linear regulator 102 . This configuration is useful as, as mentioned above, in GSM/EDGE the required performance can be achieved with a purely switching regulator 100 . With this assumption, in GSM/EDGE, only the switching regulator 100 can be used and the linear regulator 102 can be disabled. This has a positive effect on efficiency because the losses introduced by inductor _L1 are eliminated. It also allows to obtain the maximum GSM/EDGE PA supply voltage _V1 closer to the battery voltage _Vbat since the voltage drop across _L1 is eliminated. Inductor _L1 can be smaller since it has to handle less PA 104B current in the WCDMA mode of operation. In this embodiment, linear regulator 102 is only enabled in WCDMA mode.

Note, as shown in Figure 26, if all PAs 104A and 104B are connected to the same power line, the total decoupling capacitance may be too large. As shown in FIG. 28 , PA 104 (a class E PA as a non-limiting example) can be modeled by its equivalent DC resistance _Rpa in first approximation and from a regulator perspective. In practice, and for PA stability reasons, at least one decoupling capacitor C _pa must be connected in parallel with PA 104 in general. If several PAs 104 are connected on the same power line, it is possible to use one or more common (shared) decoupling capacitors. In this case, the connection shown in Fig. 26 is possible. However, if each PA 104 has to have its own decoupling capacitor, e.g. because the capacitors have to be placed inside the PA module, the total decoupling capacitance can become too large, making it impossible to achieve the required e.g. wide bandwidth.

One solution to this problem is to use a switch to disconnect the inactive PA from the power line, or at least disconnect its decoupling capacitors. Another possible solution is to connect the PAs 104A, 104B on separate power lines, eg as shown in Figure 27.

In Figure 27A, regulators 104A, 104B are both connected as "masters". In GSM/EDGE, and assuming acceptable performance is available, linear regulator 102 can be disabled and only switching regulator 100 used. However, it is possible to also use the linear regulator 102, bypassing _L1, to achieve (some) ripple compensation and dynamic performance improvement. In this case, if linear regulator 102 is also enabled and its feedback information is V ₁ applied through switch 1 (SW1 ) in GSM/EDGE position. In WCDMA mode, both regulators 100, 102 are enabled and the feedback information for the linear regulator is V _pa (SW1 is in WCDMA position).

In the embodiment shown in Figure 27B, the switching regulator 100 is connected as a "slave" for the WCDMA case (both SW1 and SW2 are in the WCDMA position) and receives its V _ref from the output of the linear regulator 102 via SW2 _-sw signal. When in GSM/EDGE mode (both SW1 and SW2 are in the GSM/EDGE position), configuration and operational considerations are as described above for Figure 27A.

Figure 29 shows an additional multi-mode configuration where the PAs 104A, 104B are connected to separate power lines at the output of individual linear regulators 102A, 102B. This configuration is an extension of the multi-mode configuration shown in Figure 26. There is only one switching regulator 100, and the PAs 104A, 104B are connected on separate power lines, each assisted by an associated linear regulator 102A, 102B, respectively, and separated by associated inductors _L1 and _L2 respectively. open. This configuration helps to overcome the problem of excessive decoupling capacitance C _pa described above with reference to FIG. 28 .

In Fig. 29A, the switching regulator 100 and the two linear regulators 102A, 102B are connected as a "master", while in Fig. 29B, the switching regulator 100 is connected as a "slave", where its reference voltage is as S1 according to the current The output of the linear regulator 102A or 102B selected by the active system (GSM/EDGE or WCDMA).

Figure 30 shows an additional multimode configuration where the GSM/EDGE PA 104A is connected at the output of the switching regulator 100 (between the output and _L1 ), and where the WCDMA PA 104B and CDMA PA 104C are connected on separate linear Separate power supply lines for the output terminals of the regulators 102A, 102B. This embodiment can be viewed as an extension of the multimodal embodiment shown in FIGS. 27 and 29 . This embodiment is particularly useful when the GSM/EDGE PA 104A can be connected directly to the output of the switching regulator 100, and at least two other PAs require fast supply voltage modulation and can be placed on separate supply lines.

In Fig. 30A, the switching regulator 100 and the two linear regulators 102A, 102B are both connected as "master", while in Fig. 30B, the switching regulator 100 is only connected as "slave" in the WCDMA and CDMA modes of operation, Wherein its reference voltage is the output of the linear regulator 102A or 102B as selected by the three-pole switch S1 according to the currently active system (WCDMA or CDMA). In GSM/EDGE mode, the switching regulator 100 receives its V _{ref_sw} input from the V _m input via S1 and thus functions as in FIG. 30A .

It should be understood that Figure 21 shows a configuration in which both the switch section 32 and linear section 34 are "masters"; Figure 22 shows a configuration in which the linear section 34 is the "master" and the switch section 32 is the "slave". Configuration; and Figure 23 shows a configuration in which both the switch section 32 and the linear section 34 are "master" and the switch section 32 operates in open loop. In yet another embodiment of the invention, the switch section 32 may function as a "master" and the linear section 34 as a "slave".

Since the switching section 32 is relatively slow, it is also best not to use its output V _pa as a reference signal to "slave" the linear section. Referring to FIG. 21 , the signal V _{ctrl_sw} is directly related to the duty cycle d of the PWM voltage applied to the LC filter at the pulse width modulator 32 node. In steady state (constant V _{ref_sw} ), V _ctrl is proportional to output voltage V _pa . However, in a dynamic state (undetermined V _{ref_sw} ), the situation is different. For example, if V _pa is commanded to increase rapidly by V _{ref_sw} , the result is a rapid increase in error signal V _e1 causing V _{ctrl_sw} to increase rapidly, which in turn commands duty cycle d to increase. Due to the increased duty cycle, V _pa will eventually (slowly) increase to a new higher level. Due to the LC filter, the response of the switching converter is much slower in increasing V _pa than in increasing V _ctrl-sw and the associated duty cycle d. In other words, V _{ctrl_sw} contains information about what is going to happen with respect to the output voltage V _pa . An increase of V _{ctrl_sw} implies an increase of the duty cycle d, thus it indicates that the output voltage V _pa must increase. This information can be used to signal the supply current to the linear section 34 to help increase V _pa . Relatedly, a decrease in V _{ctrl_sw} implies a decrease in the duty cycle d, and thus it means that the output voltage V _pa must decrease. This can be used to signal the linear section 34 to sink current in order to help lower V _pa . Therefore, V _{ctrl_sw} contains valuable information that can be used to make linear stage 34 "slave".

Referring to the above, this aspect of the invention provides yet another control mechanism where, as in FIG. 21 , instead of V _{ref_lin} = V _m , there is a relationship V _{ref_lin} = G _c3 *V _{ctrl_sw} , where G _c3 (s) Represents a voltage scaling amount in the simplest case, and also has frequency-dependent properties in more complex cases. Assume, as a non-limiting example, G _c3 (s)=1. As mentioned above, in steady state (in constant V _{ref_sw} ), V _{ctrl_sw} is proportional to the output voltage V _pa . Assume further, for this non-limiting example, that the constant of proportionality is the identity element such that V _pa =V _{ctrl_sw} , and thus also V _{ref_lin} =V _{ctrl_sw} , so V _pa =V _{ref_lin} =>V _e2 =0 =>no linearity Part 34 ingredients. If a rapid increase of V _{ref_sw} is provided, as described above, this results in a rapid increase of V _{ctrl_sw} and thus also of V _e2 , generating a command to the linear section 34 to supply additional current. Likewise, if a rapid decrease in V _{ref_sw} is provided, this results in a rapid decrease in V _{ctrl_sw} , causing a rapid decrease in _Ve2 , and the linear section 32 is thus commanded to sink current. Thus, the linear portion 34 is basically set to “slave” to the switch portion 32 .

Similar considerations apply with respect to the embodiment of FIG. 23 in which the switch portion 32 operates in an open loop, and also apply to the embodiment of FIG. 25A and related FIGS. 26 , 27 , 29 and 30 . Referring specifically to Fig. 25A, the above control configuration implies that instead of V _{ref_lin} = V _m , there is a V _{ref_lin} = V _{ctrl_sw} relationship. Note that although V _{ctrl_sw} is not shown in FIG. 25 , V _{ctrl_sw} is assumed to be an internal signal to the switching regulator 100 components having a structure such as that shown in FIG. 21 , ie, except control 36A and There is also a switch portion 32 outside 36B.

It will be appreciated that these various embodiments of the present invention allow efficient PA power supply for multi-mode transmitter architectures that can amplitude modulate the PA supply voltage. Some advantages of using these embodiments include: improved efficiency resulting in longer talk time and improved thermal management; and/or the ability to achieve desired bandwidth; GSM/EDGE and WCDMA cases shall be provided with separate units).

The use of embodiments of the present invention provides several advantages, including high power conversion efficiency. Relatedly, in battery powered communication devices, longer talk times are provided. Thermal management issues are also managed more efficiently than with purely linear DC-DC converters, and there is also the potential to eliminate or at least reduce the size of at least one power supply filtering capacitor (e.g., capacitor C in Figure 4A) all together sex.

It is noted that the switching performed in the switching section 32 or switching regulator 100 is described as falling and having voltage mode control, which is the presently preferred embodiment. However, it should be appreciated that the transition could be of the rising/falling type. An ascending/declining pattern is advantageous, but it is more difficult to achieve. The ramp-up/fall type allows lowering of the cut-off voltage in mobile stations such as cellular phones, since the battery voltage drops when its charge is depleted, and the cut-off voltage is the lowest voltage to keep the mobile station operating. When the voltage is too low, the PA6 cannot produce full output power, and the rise/fall type solves this problem. For example, by using a rising/falling type switching section 32, V _bat can be adjusted below V _{m_pk} (Fig. 2), whereas with falling only type, V _bat must be at least equal to V _{m_pk} plus a certain margin, such as V _{m_pk} +0.2V. With fast AM modulation as shown in Figure 2, the transition is controlled between rising and falling characteristics such that this transition does not cause distortion of the output voltage _Vpa . Furthermore, with a rising/falling type switching section or converter, and when _{Vm_pk} > _Vbat , the linear section 34 must be powered from a DC source greater than _{Vm_pk} , and therefore greater than _Vbat , in order to be able to supply current.

It can also be noted that in voltage mode control only voltage information (eg the output voltage of the converter) is used to generate the control signal. However, it is also possible to also use current mode control, where in addition to voltage, current information (eg inductor current) is also used. In current mode control, there are two control loops, one for current and one for voltage. Of course, other more complex types of controls may also be used.

In view of the above description of the preferred embodiment of the present invention, it should be appreciated that these teachings are not limited to use in GSM/EDGE, WCDMA and/or CDMA systems only, but can be used in any type of system having a variable amplitude envelope , where the PA supply voltage should be modulated with high efficiency and high bandwidth.

In view of the above description of the preferred embodiment of the present invention, it should be appreciated that these teachings are not limited to application to Class E PAs only, but are generally applicable to a variety of SMPAs as well as general linear PAs operating in saturation, such as saturated Class B pa.

In view of the foregoing description of the preferred embodiment of the present invention, it should be appreciated that the teachings are not limited to use with any particular type of switching converter topology (e.g., not only buck, drop, but also boost/drop ), and not only for voltage-mode control.

In view of the foregoing description of the preferred embodiment of the invention, it should be appreciated that these teachings are not limited to switching sections providing DC and linear sections providing AC. In practice, it is desirable that the switching part also provide AC as much as possible (while it is trying to follow the reference), and the linear part provide the missing AC part (or missing bandwidth). In this way, embodiments of the invention enhance the overall efficiency as much as possible, since in principle, the greater the contribution from the switching section or converter, the higher the efficiency.

In view of the above description of the preferred embodiment of the present invention, it should be recognized that although the non-ideal dynamics of the switching stage are compensated by the linear stage, the non-ideal dynamics are also caused to some extent by non-ideal PA behavior such as load variations, That is, R _pa varies with V _pa (ie, increases as V _pa decreases) and is in a mismatch condition. Thus, the linear stage 34, 102 at least compensates for non-ideal dynamic characteristics of the switching converter (eg, insufficient bandwidth and/or reference to peaking in the output characteristics). Furthermore, in this respect, the linear stage 34, 102 and the switching stage 32, 100 complement each other to obtain a specific desired reference-to-output transfer function (not only a specific bandwidth, but also a specific shape of the transfer function). For example, the linear stage 34, 102 may have such a reference-to-output transfer function that the resulting reference-to-output transfer function of a hybrid (switching/linear) power supply is of or close to a planar second order Butterworth filter type. Thus, the linear stage 34, 102 can be used to shape the resulting overall reference-to-output transfer function in order to obtain the desired characteristics. The linear stage 34, 102 also helps to track the reference signal and can be used to achieve a certain desired tracking performance of the reference signal _Vm .

The linear stage 34, 102 can also at least compensate for switching ripple, and can also at least compensate for non-ideal PA behavior, such as variations in R _pa with operating conditions.

It should also be understood that the auxiliary inductor _L1 introduced in Fig. 24 actually has a similar effect to the converter inductor L shown in Fig. 6, resulting in a current source characteristic. One difference is that in the embodiment of FIG. 6 and those that follow, a PWM rectangular voltage is applied to the input of the inductor L, while in the embodiment of FIG. 24 and those that follow, a smoothed The voltage of (the output of the switching converter 100) is applied to the input terminal of the auxiliary inductor _L1 .

In view of the above description of the preferred embodiment of the invention, it should be appreciated that in the case of GSM/GMSK modulation, the hybrid power supply performs a "power control" function whereby the power level is adjusted by adjusting the voltage level with the power supply. Thus, it can be understood that, unlike AM control, "step control" is used. Note that the goal can be to improve PA6 efficiency, especially when using linear PAs. When using a linear PA there will generally be another mechanism for regulating the power level, even at a constant supply voltage V _bat , but then the efficiency will decrease at lower power levels and the DC level can be reduced to Improve efficiency. However, when using an SMPA, the output power is (mainly) controlled by the supply voltage. Thus, it is preferable to use the PA power supply 30 to control the power.

Anyway, for a fast hybrid power supply 30 according to the preferred embodiment of the invention, and for the GSM case: a) in the TX configuration, the PA power supply is used to control the power; b) the PA power supply does not have to be very fast (although there is some /ramp-down related requirements, but they are lower than in the EDGE case); and c) advantageously, the switching ripple is compensated by the hybrid power supply 30, just as in the EDGE case.

The foregoing description has provided by way of exemplary and non-limiting examples a complete and informative description of the best method and apparatus presently contemplated by the inventors for carrying out the invention. However, various changes and modifications may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. For example, although the power supply of the present invention has been described above in the context of polar or ER emitter embodiments, the invention is applicable to other applications where the power supply must meet stringent dynamic requirements while also exhibiting high efficiency. Furthermore, the different embodiments of FIGS. 6-30 are not to be construed as limiting the number of possible embodiments that a hybrid voltage regulator can assume, or the number of RF power amplifier and RF communication system types that embodiments of the invention can be used with. In general, all such and similar modifications of the teachings of this invention will still fall within the scope of the embodiments of this invention.

Furthermore, some of the features of the invention may be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as illustrative of the principles of the invention, not in limitation thereof.

Claims (91)

1. A DC-DC converter comprising: a switch-mode portion for coupling between a DC source and a load, the switch-mode portion providing x amount of output power; and a linear mode section coupled in parallel with said switch mode section between the same or a different DC source and said load, said linear mode section providing an amount of output power of y, where x is preferably greater than y, and may be application specific constrained optimization of the ratio of x to y, wherein the linear mode part exhibits a faster response time to a desired change in output voltage than the switch mode part. 2. The DC-DC converter of claim 1, wherein the linear mode section includes at least one power operational amplifier operating as a variable voltage source. 3. The DC-DC converter of claim 1, wherein the linear mode section includes at least one power operational transconductance amplifier operating as a variable current source. 4. The DC-DC converter according to claim 1, wherein the linear mode section supplies only an AC component to the load. 5. The DC-DC converter of claim 1, wherein the linear mode section provides a DC component and an AC component to the load. 6. The DC-DC converter of claim 1, wherein the output of the linear mode section compensates for the AC ripple output from the switch mode section. 7. The DC-DC converter of claim 1, wherein the linear mode section comprises a bidirectional voltage controlled voltage source. 8. The DC-DC converter of claim 1, wherein the linear mode section comprises a bidirectional voltage controlled voltage source (VCVS), and comprises two VCVS circuits, wherein in operation, one operates as a sink and one operates as a sink for the source. 9. The DC-DC converter of claim 1, wherein the linear mode section comprises a bidirectional voltage controlled current source. 10. The DC-DC converter of claim 1, wherein the linear mode section comprises a bidirectional voltage controlled current source (VCCS), and comprises two VCCS circuits, one operating as a sink and one operating as a source. 11. The DC-DC converter of claim 1, wherein the switch mode section and the linear mode section are jointly controlled by a control signal in a closed loop manner. 12. The DC-DC converter of claim 1, wherein the switch mode section is controlled in a closed loop manner by an output from the linear mode section, and wherein the linear mode section is controlled in a closed loop manner by a control signal. 13. The DC-DC converter of claim 1, wherein the switch mode portion operates in an open loop, and wherein the linear mode portion is controlled by a control signal in a closed loop manner. 14. The DC-DC converter of claim 1, wherein the linear mode portion is effectively subordinate to operation of the switch mode portion to source or sink current. 15. A DC-DC converter as claimed in claim 1, wherein the switch mode part is provided with little or no output filter capacitance to function substantially as a current source. 16. A DC-DC converter as claimed in claim 1, wherein the switch mode part is provided with an output filter capacitance and functions substantially as a voltage source. 17. The DC-DC converter of claim 1, wherein the switch mode section is coupled to the load and is inductively coupled to the output of the linear mode section. 18. The DC-DC converter of claim 1, wherein the load comprises at least one radio frequency power amplifier. 19. The DC-DC converter of claim 11, wherein the load comprises at least one radio frequency (RF) power amplifier, and wherein the control signal comprises an RF carrier modulation signal. 20. The DC-DC converter of claim 12, wherein the load comprises at least one radio frequency (RF) power amplifier, and wherein the control signal comprises an RF carrier modulation signal. 21. The DC-DC converter of claim 13, wherein the load comprises at least one radio frequency (RF) power amplifier, and wherein the control signal comprises an RF carrier modulation signal. 22. The DC-DC converter of claim 1, wherein the linear mode section is coupled to an output of the switch mode section and capacitively coupled to the load. 23. The DC-DC converter of claim 1, wherein the switch-mode section is coupled to the load and is inductively coupled to the output of the linear-mode section, and wherein the linear-mode section is coupled via the Inductively coupled to the output of the switch mode section and capacitively coupled to the load. 24. The DC-DC converter of claim 1, wherein the linear mode section compensates for load variations at least to some extent. 25. The DC-DC converter of claim 1, wherein the linear mode section compensates, at least to some extent, non-ideal dynamic characteristics of the switch mode section. 26. A radio frequency (RF) transmitter (TX) for coupling to an antenna, the TX having an amplitude modulation (AM) path coupled to a power amplifier (PA) supply and a phase modulation (AM) path coupled to an input of the PA PM) paths, wherein the power supply includes a switch mode section for coupling between the power source and the PA, the switch mode section provides x amount of output power, the power supply also includes a A linear mode section coupled in parallel with the switched mode section between the power source and the PA, the linear mode section provides y amount of output power, where x is preferably greater than y, and x and y, and wherein the linear mode part exhibits a faster response time to a desired change in output voltage than the switch mode part. 27. The RF TX of claim 26, wherein the linear mode section includes at least one power operational amplifier operating as a variable voltage source. 28. The RF TX of claim 26, wherein the linear mode portion includes at least one power operational transconductance amplifier operating as a variable current source. 29. The RF TX of claim 26, wherein the linear mode section provides only an AC component to the PA. 30. The RF TX of claim 26, wherein the linear mode section provides a DC component and an AC component to the PA. 31. The RF TX of claim 26, wherein the output of the linear mode section compensates for the AC ripple output from the switch mode section. 32. The RF TX of claim 26, wherein the linear mode portion includes a bidirectional voltage controlled voltage source. 33. The RF TX of claim 26, wherein the linear mode portion comprises a bidirectional voltage controlled voltage source (VCVS), and comprises two VCVS circuits, wherein in operation one operates as a sink and one operates as a source. 34. The RF TX of claim 26, wherein the linear mode portion includes a bidirectional voltage controlled current source. 35. The RF TX of claim 26, wherein the linear mode portion comprises a bidirectional voltage controlled current source (VCCS), and comprises two VCCS circuits, one operating as a sink and one operating as a source. 36. The RF TX of claim 26, wherein the switch-mode portion and the linear-mode portion are collectively controlled in a closed-loop manner by a control signal, wherein the control signal comprises an AM signal. 37. The RF TX of claim 26, wherein the switch-mode portion is controlled in a closed-loop manner by an output from the linear-mode portion, and wherein the linear-mode portion is controlled in a closed-loop manner by a control signal, wherein the The control signals include AM signals. 38. The RF TX of claim 26, wherein the switch mode portion operates in an open loop, and wherein the linear mode portion is controlled in a closed loop manner by a control signal, wherein the control signal comprises an AM signal. 39. The RF TX of claim 26, wherein the linear mode portion is effectively subordinate to operation of the switch mode portion to source or sink current. 40. The RF TX of claim 26, wherein the switch mode portion is provided with little or no output filter capacitance so as to function substantially as a current source. 41. The RF TX of claim 26, wherein the switch mode part is provided with an output filter capacitance and functions substantially as a voltage source. 42. The RF TX of claim 26, wherein the switch mode section is coupled to the PA and is inductively coupled to the output of the linear mode section. 43. The RF TX of claim 26, wherein the switch-mode section is coupled to the PA and is inductively coupled to the output of the linear-mode section, and wherein the linear-mode section is coupled via the inductance to output of the switch-mode section and is capacitively coupled to the PA. 44. The RF TX of claim 26, wherein the power supply provides greater power conversion efficiency than a purely linear voltage regulator based power supply, while also providing a wider operating bandwidth than a purely switch mode based power supply. 45. The RFTX of claim 26, wherein the linear mode section is coupled to the output of the switch mode section and capacitively coupled to the load. 46. The RF TX of claim 26, wherein said linear mode portion compensates at least to some extent for said load variation exhibited by said PA. 47. The RF TX of claim 26, wherein the linear-mode portion compensates, at least to some extent, non-ideal dynamics of the switch-mode portion. 48. A radio frequency (RF) transmitter (TX) for coupling to an antenna, the TX having an amplitude modulation (AM) path coupled to a power amplifier (PA) supply and a phase modulation (AM) path coupled to an input of the PA PM) paths, wherein the power supply includes a switch-mode stage for coupling between the power source and the PA, the switch-mode stage provides x amount of output power, the power supply also includes a at least one linear mode stage coupled in parallel with said switched mode stage between said power source and said PA, said linear mode stage providing y amount of output power, where x is preferably greater than y, and can be optimized for particular application constraints The ratio of x to y, the power supply also includes at least one auxiliary inductor coupled between the output of the switch mode stage and the output of the at least one linear mode stage. 49. The RF TX of claim 48, wherein said PA is coupled to an output of said switch-mode stage before said auxiliary inductor, and further comprises at least one of said output of said switch-mode stage coupled to said auxiliary inductor One additional PA. 50. The RF TX of claim 48, wherein said PA is coupled to an output of said switch-mode stage after said auxiliary inductance, and further comprising an output terminal also coupled to said output of said switch-mode stage after said auxiliary inductance. At least one additional PA. 51. The RF TX of claim 48, wherein said PA is coupled to the output of said switch-mode stage before a first auxiliary inductor and a second auxiliary inductor, and further comprising said switch coupled to said first auxiliary inductor A second PA at the output of the mode stage and a third PA at the output of the switched mode stage coupled to the second auxiliary inductor. 52. The RF TX of claim 51 , wherein the second PA is also coupled to the output of the first linear power stage, and the third PA is coupled to the output of the second linear power stage. 53. The RF TX of claim 48, wherein the PA is coupled to an output of the switch-mode stage after a first auxiliary inductor, and further comprises a second output coupled to an output of the switch-mode stage after a second auxiliary inductor. Two PAs, wherein the PA is also coupled to the output of the first linear power stage and the second PA is coupled to the output of the second linear power stage. 54. The RF TX of claim 48, wherein said at least one linear mode stage comprises at least one power operational amplifier operating as a variable voltage source. 55. The RF TX of claim 48, wherein said at least one linear mode stage comprises at least one power operational transconductance amplifier operating as a variable current source. 56. The RF TX of claim 48, wherein said at least one linear mode stage provides only an AC component to said PA. 57. The RF TX of claim 48, wherein said at least one linear mode stage provides a DC component and an AC component to said PA. 58. The RF TX of claim 48, wherein the output of the at least one linear mode stage compensates for the AC ripple output from the switch mode stage. 59. The RF TX of claim 48, wherein the switch-mode stage and the at least one linear-mode stage are collectively controlled in a closed-loop manner by a control signal, wherein the control signal comprises an AM signal. 60. The RF TX of claim 48, wherein the switch-mode stage is controlled in a closed-loop manner by an output from the at least one linear-mode stage, and wherein the at least one linear-mode stage is controlled in a closed-loop manner by a control signal , wherein the control signal includes an AM signal. 61. The RF TX of claim 48, wherein the switch-mode stages operate in an open loop, and wherein the at least one linear-mode stage is controlled in a closed-loop manner by a control signal, wherein the control signal comprises an AM signal. 62. The RF TX of claim 48, wherein said at least one linear mode stage is effectively subordinated to operation of said switch mode stage to source or sink current. 63. The RF TX of claim 48, wherein said switch mode stage is provided with an output filter capacitor and functions substantially as a voltage source and provides a smoothed voltage signal to said auxiliary inductor. 64. The RF TX of claim 48, wherein said at least one linear-mode stage is coupled to an output of said switch-mode stage and capacitively coupled to said PA. 65. The RF TX of claim 48, wherein said at least one linear mode stage compensates, at least to some extent, for changes in said load exhibited by said PA. 66. The RF TX of claim 48, wherein said at least one linear-mode stage compensates, at least to some extent, non-ideal dynamics of said switch-mode stage. 67. The RF TX of claim 48, further comprising a switch coupled to the reference input of the switch-mode stage to selectively apply different reference signals to the switch-mode stage as a function of mode of operation. 68. The RF TX of claim 67, wherein one mode of operation comprises a GSM mode. 69. The RF TX of claim 67, wherein one mode of operation comprises an EDGE mode. 70. The RF TX of claim 67, wherein one mode of operation comprises a CDMA mode. 71. The RF TX of claim 67, wherein one mode of operation comprises a WCDMA mode. 72. The RF TX of claim 48, further comprising a switch coupled to the feedback input of the at least one linear mode stage to selectively apply different feedback signals to the at least one linear mode stage as a function of the mode of operation. mode level. 73. The RF TX of claim 72, wherein one mode of operation comprises a GSM mode. 74. The RF TX of claim 72, wherein one mode of operation comprises an EDGE mode. 75. The RF TX of claim 72, wherein one mode of operation comprises a CDMA mode. 76. The RF TX of claim 72, wherein one mode of operation comprises a WCDMA mode. 77. A method of operating a radio frequency (RF) transmitter (TX), wherein the TX has an amplitude modulation (AM) path coupled to a power amplifier (PA) supply and a phase modulation (PM) path coupled to an input of the PA The path consists of a polar structure, the method comprising: providing the power supply to include a switch-mode portion coupled between a power source and the PA, the switch-mode portion providing x amount of output power; and coupling a linear mode section in parallel with said switched mode section between said power source and said PA, said linear mode section providing y amount of output power, where x is preferably greater than y and can be optimized for particular application constraints The ratio of x to y, and wherein the linear mode part exhibits a faster response time to a desired change in output voltage than the switch mode part. 78. The method of claim 77, wherein said linear mode portion comprises at least one power operational amplifier operating as a variable voltage source or at least one power operational transconductance amplifier operating as a variable current source. 79. The method of claim 77, wherein the linear mode section provides only an AC component to the PA. 80. The method of claim 77, wherein the linear mode section provides a DC component and an AC component to the PA. 81. The method of claim 77, further comprising operating the linear-mode section to compensate for AC ripple output from the switch-mode section, the load variation exhibited by the PA, and non-linearity of the switch-mode section. At least one of the ideal dynamic characteristics. 82. The method of claim 77, wherein the linear mode portion includes one of a bidirectional voltage controlled voltage source and a bidirectional voltage controlled current source. 83. The method of claim 77, further comprising collectively controlling the switched mode portion and the linear mode portion with a control signal in a closed loop manner, wherein the control signal comprises an AM signal. 84. The method of claim 77, further comprising controlling the switch mode section in a closed loop with an output from the linear mode section, and controlling the linear mode section in a closed loop with a control signal comprising an AM signal. 85. The method of claim 77, further comprising operating the switch mode portion in an open loop and controlling the linear mode portion in a closed loop with a control signal comprising an AM signal. 86. The method of claim 77, further comprising operating the linear mode portion to effectively slave to operation of the switch mode portion to source or sink current. 87. The method of claim 77 including operating the switch mode portion to function substantially as a current source. 88. The method of claim 77 including operating the switch mode portion to function substantially as a voltage source. 89. The method of claim 77, further comprising coupling the switch-mode section to the PA and inductively to an output of the linear-mode section. 90. The method of claim 77, further comprising coupling the switch-mode portion to the PA and to an output of the linear-mode portion through an inductance, and wherein the linear-mode portion is coupled via the inductor coupled to the output of the switch-mode section and capacitively coupled to the PA. 91. The method of claim 77, further comprising coupling the linear mode section to an output of the switch mode section and capacitively coupled to the PA.

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