HK1096463B - Hybrid switched mode/linear power amplifier power supply for use in polar transmitter - Google Patents

Description

Hybrid switched mode/linear power amplifier power supply for use in polar transmitter

Technical Field

The present invention relates generally to DC-DC converter power supplies, and more particularly to a Switched Mode Power Supply (SMPS) suitable for use in a Radio Frequency (RF) transmitter, such as an RF transmitter implemented as an Envelope Recovery (ER) RF transmitter for cellular mobile stations, also known as a polar transmitter, in which symbols are represented using phase and amplitude components rather than complex in-phase/quadrature-phase (I/Q) components.

Background

Fig. 1A is a simplified block diagram showing an ER Transmitter (TX)1 architecture including an Amplitude Modulation (AM) chain and a Phase Modulation (PM) chain. The bit to be transmitted is input to a bit-to-polar converter 2 which outputs an amplitude signal via a Propagation Delay (PD)3 to an Amplitude Modulator (AM) 4. The AM 4 provides a signal (after digital to analog conversion) for controlling the output level of the TX Power Amplifier (PA)6 by using a controllable power supply 5. The bit-to-polar converter 2 also outputs a phase signal via a propagation delay 3 to a Frequency Modulator (FM)7, which in turn outputs a signal via a Phase Locked Loop (PLL)8 to the input of PA 6. The transmit signal at the antenna 9 is thus generated by using both phase and amplitude components. Advantages obtainable with the ER emitter structure include smaller size and improved efficiency.

It is understood that the supply voltage of PA6 should be amplitude modulated with high efficiency and wide bandwidth.

Turning now to power supply 5 and PA6 in more detail, high efficiency TX architectures such as polar-loop modulation TX generally rely on high efficiency but non-linear power amplifiers, such as Switched Mode Power Amplifiers (SMPAs), e.g., class E SMPAs, or they generally rely on linear power amplifiers driven into saturation, such as saturated class B power amplifiers. In these configurations, the amplitude information is provided by modulating the supply voltage of the PA6 by means of a power regulator connected between the DC supply or power source, typically a battery, and the PA6, as shown in more detail in fig. 1B.

In FIG. 1B, the output V of the power supply 5_paShould be able to track a rapidly changing reference voltage V_m. Thus, the power supply 5 must comply with certain bandwidth specifications. The required bandwidth depends on the system in which the transmitter 1 is used. E.g. required bandwidthExceeding 1MHz for EDGE systems (8PSK modulation (-17 dB dynamic range for a given power level) and 15MHz for WCDMA (wideband code division multiple access) systems (47 dB dynamic range for a given power level). As can be appreciated, these are very challenging requirements. Fig. 2 shows a typical waveform (RF envelope in an EDGE system) that has to be tracked, where the voltage (V) is modulated_m) Shown as varying between a minimum and a peak (typical rms and mean values are also shown).

It is noted that in the GSM system the modulation is GMSK with a constant RF envelope, so there is no special constraint on the power supply 5 in terms of bandwidth for a given power level.

In general, there are two main techniques for implementing the power supply 5. The first technique shown in fig. 3 uses a linear regulator implemented by a summing junction 10, a driver 12 and a power device 14. Although a high bandwidth can be achieved, it is due to the voltage drop (V) across the power device 14_drop) The reason for (2) is that the efficiency is very low.

A second technique, shown in figure 4, would be to use a switching regulator. This technique has not previously been allowed for use in polar or ER transmitters, in which the buck switching regulator 16 would include a buck or similar converter 18 and a voltage mode control circuit 20. PA6 is shown by its equivalent resistance R_paAnd (4) showing. While the efficiency of the switching regulator 16 can be very high, the required bandwidth will be difficult or impossible to obtain. More specifically, if the use of the switching regulator 16 is attempted, a very high switching frequency will be required (e.g., at least about 5 times the required bandwidth or 5-10MHz or more for EDGE, and more than 80MHz for WCDMA). While switching frequencies of 5-10MHz will be technically very challenging (typical commercial DC-DC converters operate at maximum switching frequencies in the range of about 1-2 MHz), DC-DC converters with, for example, 100MHz switching frequencies are not currently practical to implement, particularly in low cost, mass-produced devices such as cellular telephones and personal communication terminals.

In US 6,377,784B2, an "High-Efficiency Modulation RF Amplifier" of Earl mccube (Tropian, Inc.), there is a High-Efficiency power control of the High-Efficiency (e.g., hard-limiting or switching) power Amplifier purportedly described, thereby achieving the desired Modulation. In one embodiment, the spread between the required modulation maximum frequency and the switching DC-DC converter operating frequency is said to be reduced by using an active linear regulator after the switching converter. The linear regulator is said to be designed to control the operating voltage of the power amplifier with sufficient bandwidth to reliably reproduce the desired amplitude modulated waveform. Linear regulators are also said to be designed to suppress variations in their input voltage even when the output voltage changes in response to an applied control signal. The suppression is said to occur even if the variation of the input voltage has a comparable or even lower frequency compared to the frequency of the controlled output variation. Amplitude modulation is also said to be achieved by directly or effectively varying the operating voltage across the power amplifier while achieving high efficiency in the conversion of the main DC source to an amplitude modulated output signal. It is said that high efficiency can be enhanced by allowing the switched mode DC-DC converter to also vary its output voltage so that the voltage drop across the linear regulator remains at a low and relatively constant level. It is stated that Time Division Multiple Access (TDMA) burst performance can be combined with efficient amplitude modulation, and that variations in the average output power level according to the commands of the communication system, under the control of these combined functions, can also be combined within the same structure.

Disclosure of Invention

The foregoing and other problems are overcome, and other advantages are realized, in accordance with the presently preferred embodiments of these teachings herein.

In one aspect, the present invention provides a DC-DC converter having a switch-mode portion coupled between a DC source and a load, the switch-mode portion providing an x amount of output power; and it also has a linear mode portion coupled in parallel with the switch mode portion between the DC source and the load, the linear mode portion providing an output power of y amount. In a preferred embodiment, x is preferably greater than y, and the ratio of x to y may be optimized for the particular application constraints. Furthermore, the linear mode part exhibits a faster response time to a required change in output voltage than the switching mode part. In one embodiment, the linear mode portion includes at least one power operational amplifier operating as a variable voltage source, while in another embodiment, the linear mode portion includes at least one power operational transconductance amplifier operating as a variable current source.

In yet another aspect, the present invention provides an RF Transmitter (TX) coupled to an antenna. The TX has a polar architecture and includes an Amplitude Modulation (AM) path coupled to a Power Amplifier (PA) supply and a Phase Modulation (PM) path coupled to a PA input. The power supply is constructed with a switch-mode portion coupled between the battery and the PA, the switch-mode portion providing x amount of output power, and also with a linear-mode portion coupled in parallel with the switch-mode portion between the battery and the PA. The linear mode portion provides an output power of y, where x is preferably greater than y, and the ratio of x to y may be optimized for the particular application constraints. Preferably, the linear mode part exhibits a faster response time to a required change in output voltage than the switch mode part.

In yet another aspect, the present invention provides a method of operating an RF TX having a polar architecture, the architecture including an AM path coupled to a PA supply and a PM path coupled to a PA input, the method comprising: providing a power supply (power supply) to include a switch-mode portion coupled between a power source (power source) and a PA, the switch-mode portion providing an amount x of output power; the linear mode portion is coupled in parallel with the switch mode portion between the power source and the PA, the linear mode portion providing an output power of an amount y, where x is preferably greater than y, and the ratio of x to y can be optimized for a particular application constraint, and where the linear mode portion exhibits a faster response time to a desired change in output voltage than the switch mode portion.

In operation, the power supply provides higher power conversion efficiency than a purely linear voltage regulator based power supply, while also providing a wider operating bandwidth than a purely switched mode based power supply.

Drawings

The foregoing and other aspects of these teachings are made more evident in the following detailed description of the preferred embodiments, when read in conjunction with the attached drawing figures, wherein:

FIG. 1A is a block diagram of a conventional ER RF transmitter;

FIG. 1B is a block diagram of a conventional SMPA supplied with a supply amplitude modulated voltage;

FIG. 2 shows the reference voltage V that the power supply of FIGS. 1A and 1B must track_mWaveform diagrams of typical examples of (1);

FIGS. 3A and 3B show a conventional example of a linear voltage regulator providing a PA;

fig. 4A and 4B show an example of a switching regulator providing a PA;

FIG. 5 is a block diagram of a PA provided by a hybrid voltage regulator according to the present invention; wherein the linear part of the hybrid voltage regulator preferably only processes a small fraction of the required output power and provides the necessary bandwidth, and the switch-mode part preferably provides the majority of the output power with high efficiency.

FIGS. 6A-6F show simplified diagrams of an embodiment of the hybrid voltage regulator of FIG. 5;

FIGS. 7A and 7B, collectively referred to as FIG. 7, relate to the circuit shown in FIG. 6A, where FIG. 7A shows a general circuit concept and FIG. 7B shows the switch portion in greater detail;

FIG. 8 shows waveforms corresponding to the operation of the circuit of FIG. 7;

FIG. 9 also shows waveforms corresponding to the operation of the circuit of FIG. 7;

FIGS. 10A and 10B, collectively referred to as FIG. 10, relate to the circuit shown in FIG. 6B, where FIG. 10A shows a general circuit concept and FIG. 10B shows the switch portion in more detail;

FIG. 11 shows waveforms corresponding to the operation of the circuit of FIG. 10;

FIG. 12 also shows waveforms corresponding to the operation of the circuit of FIG. 10;

FIGS. 13A and 13B, collectively referred to as FIG. 13, relate to the circuits shown in FIGS. 6C and 6D, where FIG. 13A shows a general circuit concept and FIG. 13B shows the switch portion in greater detail;

FIG. 14 shows waveforms corresponding to the operation of the circuit of FIG. 13;

FIG. 15 also shows waveforms corresponding to the operation of the circuit of FIG. 13;

fig. 16A and 16B, collectively referred to as fig. 16, relate to the circuits shown in fig. 6E and 6F, wherein fig. 16A shows a general circuit concept and fig. 16B shows the switch portion in more detail;

FIG. 17 shows waveforms corresponding to the operation of the circuit of FIG. 16;

FIG. 18 also shows waveforms corresponding to the operation of the circuit of FIG. 16;

FIGS. 19A and 19B, collectively referred to as FIG. 19, show an equivalent circuit diagram of a Voltage Controlled Voltage Source (VCVS) and a VCVS circuit implemented as a Power Operational Amplifier (POA), respectively;

FIGS. 20A and 20B, collectively referred to as FIG. 20, show an equivalent circuit diagram of a Voltage Controlled Current Source (VCCS) and a VCCS circuit implemented as an Operational Transconductance Amplifier (OTA), respectively;

FIG. 21 shows a first control configuration in which both the switching and linear sections operate in closed loop and modulate signal V_mFor reference;

FIG. 22 shows a second control configuration in which both the switching and linear portions operate in a closed loop, in which the linear portion modulates the signal V_mAs a reference, and the switching section takes the output of the linear section as a reference;

FIG. 23 shows a third control configuration in which only the linear part operates in closed loop and modulates the signal V_mFor reference, and in which the switching section operates in open loopAnd only the modulated signal V_mThe information is used to generate a duty cycle of the switching section;

FIG. 24 also shows a switching regulator and a linear regulator via an auxiliary inductor L in accordance with embodiments of the present invention₁And (optional) an auxiliary capacitor C₁Are connected in parallel;

FIGS. 25A and 25B, collectively referred to as FIG. 25, show a control block diagram according to the embodiment shown in FIG. 24, where in FIG. 25A both the switching regulator and the linear regulator are masters, and in FIG. 25 the linear regulator is a master and the switching regulator is a slave;

fig. 26A and 26B, collectively referred to as fig. 26, show a first multi-mode (multi-PA) control block diagram according to the embodiment shown in fig. 24, where all PAs are connected on the same power line at the output of the linear regulator, and where in fig. 26A both the switching regulator and the linear regulator are masters, and in fig. 26B the linear regulator is a master and the switching regulator is a slave;

fig. 27A and 27B, collectively referred to as fig. 27, show a second multi-mode control block diagram according to the embodiment shown in fig. 24, in which a GSM/EDGE PA is connected at the output of a switching regulator and a WCDMA PA is connected at the output of a linear regulator, wherein in fig. 27A both the switching regulator and the linear regulator are masters, and in fig. 27B the linear regulator is a master and the switching regulator is a slave (in WCDMA mode only);

FIG. 28 shows SMPA as (a) represented in a block diagram and (b) represented by its equivalent DC resistance R_paSimulation, and (C) stabilization of PA by a capacitor C_paParallel connection of its equivalent DC resistance R_paSimulating;

FIGS. 29A and 29B, collectively referred to as FIG. 29, show a third multi-mode control block diagram in accordance with the embodiment shown in FIG. 24; wherein the GSM/EDGE PA and WCDMA PA are connected to separate power lines associated with the two linear regulators, respectively, wherein in fig. 29A the switching regulator and each linear regulator are masters, and in fig. 28B the linear regulators are each masters and the switching regulators are slaves (only in WCDMA mode); and

fig. 30A and 30B, collectively referred to as fig. 30, show a fourth multi-mode control block diagram according to the embodiment shown in fig. 24, where a GSM/EDGE PA is connected to the output of a switching regulator, where a WCDMA PA and a CDMA PA are respectively connected to separate power lines associated with two linear regulators, where in fig. 30A the switching regulator and each linear regulator are masters, and in fig. 30B the linear regulators are masters and the switching regulators are slaves (only in WCDMA and CDMA modes).

Detailed Description

Referring to fig. 5, the present invention provides a hybrid voltage regulator or power supply 30 that combines a switching section 32 that preferably handles most of the power through a high efficiency but low bandwidth and a linear section 34 that preferably handles a smaller portion of the required power through a low efficiency but high bandwidth. The resulting power supply has the required bandwidth and efficiency slightly lower than that of a purely switching power supply but still much higher than that of a purely linear regulator. The resulting hybrid power supply 30 provides an improved output voltage quality since the linear portion 34 can be used to compensate for the output voltage ripple typically associated with pure switched mode power supplies. This is an important advantage, since excessive output voltage ripple will adversely affect the output spectrum of PA 6.

It is to be noted that in principle the amount of power (x) handled by the switching section 32 is larger than the amount of power (y) handled by the linear section 34. This is often an ideal case, and in fact, in many embodiments, x is much larger than y. However, this relationship between the power handled by the switching section 32 and the linear section 34 is not considered a limitation of the preferred embodiment of the present invention. In principle, it is desirable to maximize the ratio of x to total power: the greater this ratio, the higher the efficiency. However, the actual ratio achieved in a given application may be a function of one or more of the following factors and considerations:

(a) the intended application (RF system details, such as the spectrum of the RF envelope, the magnitude of the high frequency AC components, etc.); and

(b) implementation, wherein the amount of power handled by the switching section 32 and the amount of power handled by the linear section 34 to some extent may be determined. For example, in EDGE, nearly all of the power can be handled by the switching section 32 by using a 6-7MHz switching frequency, or less power can be handled by using a lower switching converter operating at 1MHz, for example. In some cases, for example at very low power, it is also possible to disable the switching section 32 and use only the linear section 34, in which case the relation x > y does not apply at all.

(c) Also considered may be a trade-off between efficiency and implementation complexity, since implementing a slow switching converter is generally simpler, but then reduces efficiency due to the larger portion of power that needs to be handled by the linear part 34.

(d) Also considered may be a compromise to optimize overall efficiency. For example, a switching section 32 with a very high switching frequency and high bandwidth may handle most of the power in a given application (x is much larger than y), but the processing in the switching section 32 may become inefficient due to the extremely high switching frequency. It may therefore be more advantageous to attempt to optimize the overall efficiency by a compromise between using a lower switching frequency in the switching section 32 to achieve better efficiency and handling a smaller amount of energy in the switching section 32.

Thus, in general, the power portion x handled by the switching section 32 is preferably larger than the power portion y handled by the linear section 34, and the ratio of x to y is also preferably optimized for the constraints imposed by a given application and possibly also by a particular mode of operation (e.g., in the low power mode described above, where all power may be handled by the linear section 34). Combinations are also contemplated such that x is preferably greater than y, and the ratio of x to y may also be optimized for application constraints.

In practice, the invention can be implemented by using a partial topology of the switching converter (called "switching section" in fig. 5) and connecting it in parallel with a voltage or current source (called "linear section" in fig. 5). The output capacitor (C) of the buck (down-type) converter 18 of fig. 4A is removed. In the buck converter 18, the capacitor acts as a voltage source to keep the output voltage constant. When the voltage at the output needs to be increased, a large current must be supplied through the inductor (L) to meet the increased demand of the load and to charge the capacitor (C) to a new higher voltage level. This operation slows down the switching regulator 16 and limits the bandwidth. However, if capacitor (C) is replaced with a voltage source, the increased (or decreased) voltage level may be provided very quickly by the parallel voltage source of linear section 34, while the slower switching section readjusts its operating point.

Referring again to fig. 2, the switching section 32 provides an average level V_{m_av}Whereas the linear part 34 provides an AC component superimposed on the average level.

An alternative embodiment based on the same concept uses a current source instead of a voltage source in the linear part 34.

The voltage source of the linear part 34 may be implemented using a Power Operational Amplifier (POA), while the current source of the linear part 34 may be implemented using a power Operational Transconductance Amplifier (OTA). The operational amplifier of the linear section 34 may be powered by the battery voltage (V) as shown in FIG. 5_bat) Provided is a method. In an alternative, currently more preferred embodiment (from an efficiency point of view), the operational amplifier of the linear part 34 is supplied with the voltage V of fig. 2_{m_pk}I.e. a voltage corresponding to the amplitude of the reference signal, where V_{m_pk}Is always lower than V_bat. In practice, it is preferable to supply the voltage V to the operational amplifier of the linear part 34_{m_pk}Plus some margin (e.g., 0.2V) required to obtain proper operation of the linear stage.

Fig. 6A-6F illustrate various embodiments of the hybrid voltage regulator 30 of fig. 5, wherein fig. 6A, 6C, and 6D illustrate the use of a variable voltage source 34A (e.g., the power operational amplifier described above), and wherein fig. 6B, 6E, and 6F illustrate the use of a variable current source 34B (e.g., the power operational transconductance amplifier described above). Note that in fig. 6C two variable voltage sources 34A and 34A 'are used, and in fig. 6D two variable voltage sources 34A and 34A' are capacitively coupled to the output supply rail of the switching section 32 via C1. Note also that in fig. 6E, two variable current sources 34B and 34B 'are used, and in fig. 6F, the two variable current sources 34B and 34B' are capacitively coupled to the output power rail of the switching section 32 via C1.

Based on the above description, it can be appreciated that the use of the present invention allows for an efficient PA supply 30 to be implemented for TX architectures, where the PA supply voltage needs to be amplitude modulated. Currently, this can only be achieved by using inefficient linear regulators (see fig. 3A and 3B) since there are no commercial switching regulators known to the present inventors to provide the required bandwidth.

The above and other embodiments of the invention will now be described in further detail.

The circuit shown in fig. 7 is related to the circuit shown in fig. 6A, wherein fig. 7A shows a general circuit concept, and wherein fig. 7B shows the switch section 32 in more detail. The switching section 32 is obtained from a buck converter, which is a buck-type switching DC-DC converter composed of two switching devices and one L-C filter. The switching device shown in fig. 7B as a complementary MOS transistor (PMOS/NMOS) is turned on at a duty cycle d (d ═ time t when the upper switch is on_{on_PMOS}And a switching period T_SRatio) alternately turned on. The control signal having a duty cycle d may be obtained from an analog Pulse Width Modulator (PWM) component 32A by comparing V_{ctrl_sw}And has a period T_sWill control the voltage V_{ctr_sw}To a PWM signal having a duty cycle d. The PWM signal fed to the transistor drive stage 32B may also be generated by other methods, such as in a digital PWM component.

Conventional buck converters typically include an L-C output filter, where C is large enough so that the buck converter is characterized by a voltage source. However, in the presently preferred embodiment of the invention, the filter capacitor is eliminated, or retained, but with very little capacitance. As such, the component 32 is referred to herein as a "switching portion" as opposed to a "switching converter". In practice, the physical circuit will have some filtering capacitance, e.g., an amount necessary to ensure stability of the RFPA 6. However, for the purpose of illustrating the invention, it is assumed that the capacitance value (C) is much smaller than that present in a conventional buck converter, so that the characteristics of the switching section 32 are mainly those of a current source, not of a voltage source.

More specifically, the switching section 32 has the characteristics of a current source, rather than an actual Voltage Controlled Current Source (VCCS), due to the inductor (L) (and the no/very small capacitance C). Control voltage V_{ctrl_sw}Determines an increase in the duty cycle d, which determines the average output voltage V_paWhich in turn determines the PA6 current I_paAnd thus determines the inductor current I_LAn increase in the DC component. However, PA6 Current I_paIs not completely controlled by the control voltage V_{ctrl_sw}Is determined and is in I_pa＝V_pa/R_paWhen also represented by R_paAnd (4) determining. Thus, while this technique may operate like "VCCS," it does not directly control current and is therefore referred to as "VCCS-like.

The linear section 34 operates as a Voltage Controlled Voltage Source (VCVS)34A, and its output voltage V_oBy differential amplification of A_dFrom a differential voltage V_dAnd (5) controlling.

More specifically, FIG. 7A shows this embodiment of the invention by assuming an ideal source: in which the switching section 32 acts like a current source and is connected in parallel with a linear section 34 that acts like a bi-directional (i.e. it can supply and sink current) voltage controlled voltage source 34A. The linear part 34 as a voltage source sets the PA6 voltage V_pa. Current i of the switching section 32_swPlus the current i of the linear part 34_linForming a PA6 current i_pa(R_paRepresenting the effective impedance of PA 6). Connectable optional DC blocking decoupling capacitor C_dTo ensure that the linear portion 34 only provides an AC component.

FIG. 7 shows the switching section 32 passing through the drop-down typeA voltage converter implementation from which the output filter capacitance C has been eliminated or greatly reduced. Current i of the switching section 32_swAnd is therefore effectively the inductor current i_LResulting in a substantially current source-like behavior (the inductor L may be compared to a current source).

It is worth noting that since the linear part 34 has the characteristics of a voltage source, it can fix the voltage level V applied to the PA_paAnd there are means to control this voltage level. In addition, the linear portion 34 is fast (wide bandwidth), and therefore it is possible to provide V_paFast modulation of (2). It is also noted that VCVS34A of linear section 34 is bi-directional, indicating that current can be sourced and sunk.

As shown in fig. 19B, VCVS34A may be implemented as a Power Operational Amplifier (POA). The POA includes an operational amplifier (OPAMP) having a class a (b) stage capable of sinking/supplying the required current. FIG. 19B shows a transistor Q₁And Q₂Constituent class B power stages, but the output stage design can be changed to improve performance. For example, the power stage may actually be implemented as a class AB stage to reduce crossover distortion.

As mentioned, an optional decoupling capacitor C may be introduced_dTo ensure that the linear part 34 only supplies the AC current component. However, in some cases it may be advantageous to allow the linear part 34 to also provide a DC component, although this may lead to more complex control. For example, it may be desirable to provide a DC component from the linear portion 34 at a low power level, in the case where the switching portion 32 may be disabled and the PA6 current will be provided only by the linear portion 34. As another example, at V_{pa_peak}Very close to a low battery voltage level of, for example, 2.9V, for example, 2.7V, and the switching section 32 cannot provide it, it is desirable to provide a DC component from the linear section 34 of the low battery voltage level. In such cases, optional C will be removed_d。

The circuit operation shown in fig. 7A is illustrated by the analog waveforms shown in fig. 8, and the circuit operation shown in fig. 7B is illustrated by the analog waveforms shown in fig. 9.

The uppermost waveform in fig. 8 shows the resulting PA6 voltage V_pa. PA6 Voltage V_paSet by a linear stage 34 having a voltage source characteristic. In this example, V_paWith a DC component (2V) plus an AC component shown as a 15MHz voltage sine wave representing fast modulation. The second waveform from the top shows the current component of the switching section 32, constant current i_sw. The third waveform from the top shows the current component of the linear part, the AC component i_lin(15MHz sine wave). As mentioned, the linear portion 34 operates as a bi-directional voltage source, i.e., it can both supply and sink current. The lowest waveform shows the resulting PA6 current i_paWith a DC component from the switching section 32 and an AC component from the linear section 34.

Note that in fig. 8, one set of waveforms is for a sine wave of zero amplitude (no contribution from the linear portion 34, labeled "a") and another set is for a sine wave of non-zero amplitude (to show contributions from the linear stages, labeled "B"). The same convention is used in the waveform diagrams of fig. 9, 11, 12, 14, 15, 17 and 18.

Fig. 9 shows analog waveforms to illustrate the operation of the circuit shown in fig. 7B. For this non-limiting example, assume that the switching stage 32 has a switching frequency of 5MHz and a duty cycle of 0.5. The uppermost waveform shows the PWM 32A voltage applied across the inductor L at node PWM. The resulting PA6 voltage V is shown from the second waveform from the top_pa. PA6 Voltage V_paSet by a linear stage 34 having a voltage source characteristic. In this example, V_paWith a DC component (2V) plus a 15MHz AC component (voltage sine wave) representing fast modulation. The third waveform from the top shows the current component of the switching section 32, i.e., the inductor current i_L＝i_sw. In this case, the current is not a constant current as in the ideal case shown in fig. 8, but has a certain triangular shape as encountered in a switching converter. The switching section 32 provides a DC component and a triangular AC component (inductor current ripple). The fourth waveform from the top shows the current component, the AC component i, of the linear section 34_lin(15MHz sine wave plus inductor current ripple compensation). Note that the linear portion 34 provides not only a 15MHz sinusoidal component, but also an AC component to compensate for the inductor current ripple (denoted AC from scratch)_ripThe following waveforms can be clearly seen). This is due to the voltage source characteristic of the linear part 34, which acts as a bi-directional voltage source, supplying and sinking current. The lowest waveform shows the resulting PA6 current i_paWith a DC component from the switching section 32 and an AC component from the linear section 34, wherein the AC triangular component of the inductor current (third curve) is compensated by the linear stage 34.

Fig. 10 shows an embodiment in which a Voltage Controlled Current Source (VCCS)34B is used to form the linear part 34. Generally, the same considerations apply as for the embodiment of fig. 7, the only significant difference being that VCCS itself cannot fix the PA6 voltage level. In contrast, the PA6 voltage is injected into R_paIs determined. The linear portion 34 may be implemented as an Operational Transconductance Amplifier (OTA) as shown in fig. 20B. In this simplified view, the differential pair Q₁Collector current (Ic)₁) Mirror image as I₅And Q is₂Collector current (Ic)₂) Mirror image as I₃And then mirrored as I₄. Output current of I_o＝I₅-I₄And with collector current IC₁-IC₂Is proportional to the difference between them, which in turn is proportional to the differential voltage V_dAnd (4) in proportion. As noted, fig. 20B shows a simplified representation of an OTA. In practice, the circuit will achieve the aim of optimizing the accuracy of the current mirror and obtaining the linear characteristic I_o＝gV_d。

The circuit operation shown in fig. 10A is illustrated by the analog waveforms shown in fig. 11, and the circuit operation shown in fig. 10B is illustrated by the analog waveforms shown in fig. 12.

In fig. 11, the uppermost waveform shows the resultant PA6 voltage V_pa. It is assumed that PA6 acts like a resistive load from the power supply perspective. Thus, V_pa＝R_pa(i_sw+i_lin) That is, the PA6 voltage is set by the sum of the currents supplied by the switching section 32 and the linear section 34. In this example, R_paAssumed to be equal to 2 ohms. The switching section 32 supplies a DC component i_sw(e.g., 1 amp) and the linear portion 34 provides an AC component i_linA fast modulated 15MHz current sine wave is shown. The second waveform from the top shows the current component of the switching section 32, i.e., a constant current i of 1 ampere_sw. The third waveform from the top shows the current component of the linear portion 34, i.e., the AC component i_lin(15MHz current sine wave). The lowest waveform shows the resulting PA6 current i_paWith a DC component from the switching section 32 and an AC component from the linear section 34.

In fig. 12, it is assumed that the switching stage 32 has a switching frequency of 5MHz and a duty ratio of 0.5. The uppermost waveform shows the PWM 32A voltage applied across the inductor L at node PWM. The second waveform from the top shows the resulting PA6 voltage V_pa. As described above, assume that PA6 acts like a resistive load, and thus V_pa＝R_pa(i_sw+i_lin) That is, the PA6 voltage is set by the sum of the currents supplied by the switching section 32 and the linear section 34. As mentioned above, R_paAssumed to be equal to 2 ohms. The switching section provides a DC component i having a triangular AC component_sw(1 amp). The linear part providing an AC component i_linSuch as a 15MHz current sine wave representing fast modulation. The third waveform from the top shows the current component of the switching section 32, i.e., the inductor current i_L＝i_sw. In this case, the current is not a constant current as in the ideal case shown in fig. 11, but has a triangular shape encountered in the switching converter. The switching section 32 provides a DC component and a triangular AC component (inductor current ripple). The fourth waveform from the top shows the current component of the linear section 34, i.e., the AC component i_lin(15MHz sinusoidal component). Note that in this case the linear part 34 provides only a 15MHz sinusoidal component, unlike the corresponding waveform of fig. 9, in which the AC component of the compensating inductor current ripple is also seen. The lowest waveform shows the resulting PA6 current i_paHaving a DC component from the switching section 32 and an AC delta component (which may be designated AC from the list of_ripSee below waveform) and the AC component from the linear portion 34. Note that in this embodiment the AC triangle component is not compensated by the linear stage 34 due to the current source characteristics of the linear stage 34, but it can be compensated by appropriately controlling VCCS.

The circuits shown in fig. 13 and 16 show that the linear portion 34, which is made up of two VCCS 34A and 34A 'or two VCCS 34B and 34B', respectively, runs from V_batSupplying current and sinking current to ground. The operation is shown in the waveform diagrams of fig. 14 and 15 and fig. 17 and 18, respectively.

The circuit representations in fig. 13 and 16 and their corresponding waveforms show the source/sink behavior of VCVS34A and VCCS 34B, respectively, and simulate the behavior of a power operational amplifier and a power transconductance amplifier, respectively. Note that the two VCVS34A in fig. 13 are not activated at the same time and are preferably placed in a high impedance state when not activated.

More specifically, fig. 13A and 13B show this embodiment with an ideal source, and the explanation above for the circuit of fig. 7 also applies here. The difference between the circuits is that the voltage sources VCVS34A and 34A' are unidirectional (one supplying current and the other sinking current) in the embodiment of fig. 13, whereas the voltage source 34A is bidirectional (supplying and sinking) in fig. 7. May include a decoupling capacitor C_dTo ensure that the linear portion 34 only provides an AC component.

For the simulated waveform diagrams of fig. 14 and 15, similar explanations as given above for fig. 8 and 9 apply, except for the component i of the linear portion 34_linIs divided into i_aux1(supply) and i_aux2(absorption). It should also be noted that the two voltage sources 34A and 34A' (source and sink) are preferably placed in a high impedance state when their respective currents are zero (i.e., they are inactive).

Fig. 16A and 16B show this embodiment of the invention with an ideal source, and the explanation above for the circuit of fig. 10 is also applicable here. Difference between circuitsThe difference is that the current sources VCCS 34B and 34B' are unidirectional (one supplying current and the other sinking current) in the embodiment of fig. 16, whereas the current source 34B is bidirectional (supplying and sinking) in fig. 10. May include a decoupling capacitor C_dTo ensure that the linear portion 34 only provides an AC component.

For the simulated waveform diagrams of fig. 17 and 18, similar explanations as made above for fig. 11 and 12 apply, except for the component i of the linear portion 34_linIs divided into i_aux1(supply) and i_aux2(absorption).

Note that fig. 7 and 10 are merely representations of the interconnection of the power supply stages (the switching section 32 and the linear section 34), and control is not considered. The switching section 32 is represented by a control voltage V_ctrlA component of control. The linear portion 34 is represented by a differential voltage V_dA component of control. Fig. 21, 22 and 23 show three non-limiting embodiments of control techniques for a closed control loop.

In fig. 21, the switching section 32 is operated by voltage mode control. The controller is composed of a control part 36A and a frequency dependent characteristic G_c1(s) section 36B, control section 36A generating an error signal V_e1And the part 36B applies the error signal V_e1As its input and to be used for the control voltage V of the switching section 32_{ctrl_sw}As its output. Error voltage V_e1As a modulated signal V_mReference voltage V of_{ref_sw}And as the output voltage V_paIs fed back to_{feedback_sw}The difference between them. In this case, the controller (components 36A, 36B) may be physically implemented as an operational amplifier with an R-C compensation network to obtain the characteristic G_c1(s)。

The linear part 34 uses the modulation signal V_mAs reference V_{ref_lin}. Feedback voltage V_{feedback_lin}Is an output voltage V_pa. Feedback voltage V_{feeaback_lin}Also shown in dashed lines in the figure as decoupling capacitors C_dObtained before (if present). The controller in this case is similar to the switching section 32 by generating the error signal V_e2Component 38A and G having a frequency-dependent characteristic_c2Component 38B of(s). Since the linear portion 34A is preferably implemented with a power op-amp in practice, as in fig. 19B, the characteristic G is obtained by adding an R-C compensation network, as will be appreciated by those skilled in the art_c2(s) around which the control loop can be closed. Note that the inclusion of VCVS34A merely shows the voltage source characteristics of linear stage 34, which is different from the VCVS shown in fig. 7. The component labeled "linear with feedback" is actually a representation of a power operational amplifier with an R-C compensation network.

Note that the same considerations as described above apply to closing the loop when the linear stage 34 is constructed with VCCS 34B (e.g., fig. 10) and the OTA shown in fig. 20B.

In fig. 22, the only substantial difference compared to fig. 21 is that the reference signal of the switching section 32 is the output taken from the linear section 34 (before which the decoupling capacitor, if present), is present. The same considerations apply when the linear stage 34 uses VCCS 34B and OTA. In this embodiment, it is apparent that the linear part 34 will modulate the signal V_mThe AM signal serves as its reference, while the switching section 32 takes the output of the linear section 34 as its reference (i.e., it "slaves" to the linear section 34).

In the embodiment of fig. 23, the switching section 32 operates in an open loop, which means that only the modulation signal V is present_mFor generating a PWM duty cycle d without an error signal V_e1＝V_m-V_pa. This exemplary embodiment may be particularly useful when the dual loop control system as shown in fig. 21 and 22 may have stability problems. As described above, the same considerations apply when the linear stage 34 uses VCCS 34B and OTA.

The above description of embodiments of the invention provides a solution for achieving fast modulation of the PA6 power supply, where the fast modulation is mainly provided by the linear part 34 and uses a buck converter with no or very little filter capacitance. It should be noted, however, that the concept of connecting a switching stage in parallel with a linear stage can be applied and is also useful in case the buck converter is used in a conventional fashion, i.e. with a rather large output filter capacitance C and thus with a voltage source characteristic. For example, an RF transmitter for GSM/EDGE case can be addressed by a fast switching converter based on a buck converter with voltage mode control. In this exemplary case, the necessary bandwidth may be achieved, however, the dynamics are not ideal (i.e., the reference-to-output transfer function is not flat, but instead may exhibit peaking) and thus the reference tracking is not optimal. In addition, output voltage ripple due to converter switching action forms a spurious RF signal. Thus, a linear stage 34 connected in parallel with the buck converter can be used to compensate for its undesirable dynamics by "helping" the switching converter and improving its tracking performance. In fact, the linear section 34 can also be used to improve (widen) the bandwidth, but its main role is to correct the reference-to-output characteristic already provided by the switching section 32. In addition, the linear section 34 may also compensate for the output voltage switching ripple (at least in a manner sufficient to meet RF spurious needs) by injecting current to compensate for the inductor current ripple.

For the reasons stated above, it should be understood that the embodiment outlined in FIG. 5 may be extended to include the following circuit structure: where the switching section 32 is a "normal" buck converter, i.e. the output filter capacitance C is large enough to make the buck converter act like a voltage source.

Based on the above, it can be appreciated that the above described embodiments of the invention comprise a circuit configuration based on a buck switching converter without or with a very small filter capacitance C, i.e. where the output filter capacitance C is sufficiently small (or not present) so that the buck converter behaves essentially like a current source, where the linear part 34 alone is able to determine the bandwidth of the PA6 power supply, i.e. even with a very slow switching part 32, the linear part 34 is able to modulate due to the absence/very small buck converter filter capacitance; where the linear part 34 also provides the triangular AC component of the inductor current; and wherein the linear part 34 compensates for the switching ripple.

Based on the above, it can be appreciated that the above described embodiments of the invention also include circuit configurations that are preferably based on buck switched-mode converters having a relatively large filter capacitance C, i.e. wherein the output filter capacitance C is sufficiently large that the buck converter essentially acts like a voltage source. Accordingly, embodiments of the present invention also include circuit configurations based on a "normal" buck converter circuit topology with a filter capacitor; where the bandwidth is mainly determined by the switching converter. In this case, the linear portion 34 may be used to improve the bandwidth, but in a more limited manner, since the bandwidth is actually limited by the filter capacitor C of the switching regulator. The important role of the linear part 34 in these embodiments is to assist and correct the dynamics of the switching part 32 (buck converter). In this embodiment, the linear part 34 may also compensate for the switching ripple.

Aspects of the invention are based on the following observations: the high frequency components in the exemplary EDGE and WCDMA envelopes have very low amplitudes, while most of the energy is in the DC and low frequency components. The low bandwidth switching section 32 handles most of the power (DC and low frequency components) with high efficiency, while the wider bandwidth linear section 34 handles only a small portion of the power (corresponding to the power of the high frequency components) with lower efficiency. It is therefore possible to achieve the required bandwidth and still provide good efficiency. Typically, the obtainable efficiency is lower than that achieved with a purely switching power supply, but still much greater than that achieved with a purely linear regulator-based power supply.

The principles of the present invention may be applied regardless of the actual implementation of the switching section 32 and/or the linear section 34, and are generally applicable to transmitter architectures where the PA6 supply voltage needs to be amplitude modulated. The teachings of the present invention are not limited to GSM/EDGE and WCDMA systems but can also be extended to other systems (e.g., to CDMA systems). The teachings of the present invention are not limited to systems using class E PA6, but are also applicable to systems using other types of saturated PAs.

Other aspects of the invention, described in more detail below, are directed to coupling and provisioning several PAs 6 in a multimode transmitter and control for the same method.

Reference is now made to24, an embodiment is shown in which the switching regulator 100 and the linear regulator 102 are connected through an additional inductor L₁(i.e. in addition to the conventional switching section 32 inductor L as shown, for example, in fig. 7B) and an (optional) capacitor C₁Coupled in parallel to the SMPA104 (e.g., a class E PA). PA104 supply voltage V_paIs scribed with high precision by the linear regulator 102. However, due to low bandwidth, switching ripple and noise, the instantaneous output voltage V of the switching regulator 100₁Cannot be fixed exactly to the same value. Thus, an additional inductor L is introduced₁To adjust the instantaneous voltage difference V_pa-V₁。L₁The average voltage on must be zero, thus V₁Is equal to V_pa。

If a decoupling capacitor C is present₁Then the linear regulator 102 may provide only an AC component over a range of frequencies, which preferably compensates for the lower bandwidth of the switching regulator 100 to achieve the desired overall bandwidth.

If C is present₁Absent, linear regulator 102 may also provide DC and low frequency components. Under certain conditions, e.g. at PA104 voltage V_paShould be as close as possible to the battery voltage V_batThis may be particularly advantageous. One such case is the GSM case at maximum RF output power (very small voltage, e.g., 2.7V, is required for the PA 104) when low battery voltage (e.g., 2.9V) is used. In this case, the difference between the input voltage and the output voltage of any regulator interposed between the battery and the PA104 is extremely low (only 0.2V in this example). This is a value that is extremely difficult to obtain with switching regulator 100 (assuming a voltage drop across one power device plus two inductors L and L₁Duty cycle less than 100%). In this particular case, the linear regulator 102 may be used to provide a supply voltage closer to the battery voltage, and thus the linear regulator 102 provides all the power (DC component, and no capacitor C)₁). While in this particular case (GSM, maximum output power, low battery voltage) efficiency will not be affected due to the small voltage drop across the linear regulator 102, at lower GSM power levels (i.e., greater voltage drop across the linear regulator 102), efficiency will be affectedWill be reduced. Therefore, at lower power levels, it is more advantageous to use the switching regulator 100 to provide all the power (DC component).

In fig. 24, the supply voltage of the linear regulator 102 is V_batThe same as the voltage for the switching regulator 100. While this may be optimal from an implementation standpoint, it may not be optimal from an efficiency standpoint. At a lower power level, where V_{m_pk}Ratio V_batAt much lower, the pressure drop across the linear regulator 102 is large and its efficiency is low. Thus, a more efficient technique (with high efficiency) pre-conditions the supply voltage of the linear regulator 102 at a certain level, e.g., above the envelope V_{m_pk}The peak value is 200 mV and 300mV (see FIG. 2).

As can be seen from fig. 3 and 4, the two component parts (switching and linear) of the hybrid regulator have their own control loops. The overall control must be configured such that the two components complement each other. Fig. 25 shows two possible control schemes.

In fig. 25A, both regulators 100, 102 are "master" because each regulator will modulate signal V_mFor reference, and each regulator 100, 102 receives its feedback signal (V) from its own output_{feedback_sw}、V_{feedback_lin})。

In FIG. 25B, the linear regulator 102 is "master", i.e., it will modulate the signal V_mFor reference and its own output as a feedback signal. Switching regulator 100 is "slave," meaning that it takes the voltage that linear regulator 102 applies to SMPA104 as a reference signal and attempts to follow it as accurately as possible.

As described below, these embodiments of the present invention are particularly well suited for multi-mode transmitter applications.

As a first non-limiting example, in GSM, the RF envelope is constant, so the voltage provided to the PA104 is constant, and its level is adjusted according to the required power level. The primary function of the SMPA104 power supply in this case is power control. In principle it would be sufficient to use only the switching regulator 100. However, the switching action generates output voltage ripple and noise, which is seen as a spurious signal in the RF spectrum output by the SMPA 104. In this mode, the linear regulator 102 can be used to compensate for the output voltage ripple of the switching regulator 100 when needed. In this way, the specification of the output voltage ripple of the switching regulator 100 can also be relaxed. For example, if a typical voltage ripple specification of 5mV is assumed for the switching regulator 100, the specification may also be relaxed to 50mV when ripple compensation is provided by the linear regulator 102, allowing for smaller LC components in the switching regulator 100 and/or faster dynamics of the switching regulator 100. In this case, the switching regulator 100 handles almost all of the required SMPA power, while the linear regulator 102 handles very little (only the processing required for ripple compensation).

In an EDGE system, or generally any system that includes a variable RF envelope with moderately high dynamics (e.g., required BW > 1MHz), the primary functions of the SMPA104 power supply are power control and envelope tracking. It can be seen that a pure switching regulator with a switching frequency of 6-7MHz is able to track the EDGE RF envelope with relatively good accuracy. However, when using a pure switching regulator, the system is not robust and may appear sensitive to, for example, peaking in the reference-to-output transfer function of the switching regulator 100 and variations in the SMPA104 load with supply voltage (typically the resistance of the SMPA increases as the supply voltage decreases). In addition, as described above, there is also a problem of output voltage ripple. In accordance with this aspect of the invention, the linear regulator 102 may be used to compensate for non-optimal dynamics of the switching regulator 100, SMPA104 load variations, and switching ripple, if desired. If the switching frequency of the switching regulator 100 is high enough to achieve good tracking performance, most of the power is handled by the switching regulator 100. However, it is also possible to use a switching regulator 100 with a lower switching frequency and thus a lower bandwidth, in which case the proportion of power handled by the linear regulator 102 will increase to compensate for the reduction handled by the switching regulator 100.

In a WCDMA system, or any system that typically exhibits a variable RF envelope with high dynamics (e.g., required BW > 15MHz), the primary functions of the SMPA104 power supply are power control and envelope tracking. However, since the required bandwidth is much higher than for EDGE systems, it is not sufficient to use only the switching regulator 100 (in CMOS technology), and it becomes important to use the linear regulator 100 to provide the required bandwidth. As in the EDGE case, the linear regulator 102 can also compensate for switching ripple and SMPA104 load variations.

Yet another utility gained from the use of embodiments of the present invention is the ability to provide multiple PAs for multi-mode operation. One non-limiting example is the GSM/EDGE class E PA104A and the WCDMA class E PA 104B shown in FIG. 26. In this case, all the PAs 104A, 104B are connected on the same power line at the output of the linear regulator 102. This embodiment, like the embodiment of fig. 27, 29 and 30, assumes that there is a mechanism (e.g., a switch) that enables only one PA104A or 104B at a time.

Note that the PAs 104A and 104B are not limited to class E PAs, and these are shown for convenience only. The same applies to the embodiments shown in fig. 27, 29 and 30.

In fig. 26A, both regulators 100, 102 may be considered "master", i.e., both modulate signal V_mAs their reference and each has its own corresponding output voltage to provide its feedback information. In fig. 2B, the linear regulator 102 is the "master" and the switching regulator 100 is the "slave", which means that its reference signal is the output V of the linear regulator_pa。

Fig. 27 shows an additional multi-mode configuration in which a GSM/EDGE PA104A is connected at the output of the switching regulator 100 (between the output and L)₁In between) and the wcdma pa 104B is connected at the output of the linear regulator 102. This configuration is useful where, as described above, in GSM/EDGE, the desired performance can be achieved by the pure switching regulator 100. With this assumption, in GSM/EDGE, only the switching regulator 100 can be used and the linear regulator 102 can be disabled. This has a positive effect on efficiency, since eliminationBy an inductor L₁The loss caused. Due to L₁The voltage drop over is eliminated, so that it also allows a voltage closer to the battery voltage V to be obtained_batMaximum GSM/EDGE PA supply voltage V₁. Inductor L₁May be smaller because it only handles less PA 104B current in the WCDMA mode of operation. In this embodiment, the linear regulator 102 is enabled only in the WCDMA mode.

Note that if all the PAs 104A and 104B are connected to the same power supply line, the total decoupling capacitance may be too large, as shown in fig. 26. As shown in FIG. 28, the PA104 (class E PA as a non-limiting example) may use its equivalent DC resistance R in a first approximation and from a regulator perspective_paAnd (6) simulating. In practice, and for PA stability reasons, at least one decoupling capacitor C must generally be placed_paIn parallel with the PA 104. If several PAs 104 are connected on the same power line, it is possible to use one or more common (shared) decoupling capacitors. In this case, the connection shown in fig. 26 is possible. However, if each PA104 must have its own decoupling capacitor, e.g., because the capacitor must be placed within the PA module, the total decoupling capacitance may become too large to achieve the desired wide bandwidth, e.g., in the WCDMA mode of operation.

One solution to this problem is to use a switch to disconnect the inactive PA from the power supply line, or at least disconnect its decoupling capacitor. Another possible solution is to connect the PAs 104A, 104B on separate power lines, for example, as shown in fig. 27.

In fig. 27A, regulators 104A, 104B are both connected as "masters". In GSM/EDGE, and assuming acceptable performance is available, the linear regulator 102 can be disabled and only the switching regulator 100 used. However, it is possible to use also the linear regulator 102, the bypass L₁To achieve (some) ripple compensation and dynamic performance improvement. In this case, if the linear regulator 102 is also enabled, and its feedback information is V applied through switch 1(SW1) in the GSM/EDGE position₁. In WCDMA mode, modulationBoth noders 100, 102 are enabled and the feedback information for the linear regulator is V_pa(SW1 in the WCDMA position).

In the embodiment shown in FIG. 27B, the switching regulator 100 acts as a "slave" connection for the WCDMA case (both SW1 and SW2 in the WCDMA position), and receives its V from the output of the linear regulator 102 via SW2_ref-swA signal. In the GSM/EDGE mode (both SW1 and SW2 in the GSM/EDGE position), configuration and operational considerations are as described above for FIG. 27A.

Fig. 29 shows an additional multi-mode configuration in which the PAs 104A, 104B are connected to separate power supply lines at the outputs of the individual linear regulators 102A, 102B. This configuration is an extension of the multimodal configuration shown in FIG. 26. There is only one switching regulator 100 and the PAs 104A, 104B are connected in separate power lines, each assisted by an associated linear regulator 102A, 102B, respectively, and each passing through an associated inductor L, respectively₁And L₂And (4) separating. This arrangement helps to overcome the excessive decoupling capacitance C previously described with reference to figure 28_paTo a problem of (a).

In fig. 29A, the switching regulator 100 and the two linear regulators 102A, 102B are connected as "master", whereas in fig. 29B, the switching regulator 100 is connected as "slave", wherein its reference voltage is the output of the linear regulator 102A or 102B as selected by S1 according to the currently active system (GSM/EDGE or WCDMA).

Fig. 30 shows an additional multi-mode configuration in which a GSM/EDGE PA104A is connected at the output of the switching regulator 100 (between the output and L)₁And wherein the WCDMA PA 104B and CDMA PA 104C are connected to separate power supply lines at the output of the separate linear regulators 102A, 102B, respectively. This embodiment can be considered an extension of the multi-mode embodiment shown in fig. 27 and 29. This embodiment is particularly useful when the GSM/EDGE PA104A can be directly connected to the output of the switching regulator 100 and at least two other PAs require fast supply voltage modulation and can be placed on separate supply lines.

In fig. 30A, the switching regulator 100And both linear regulators 102A, 102B are connected as "master", while in fig. 30B the switching regulator 100 is connected as "slave" only in WCDMA and CDMA modes of operation, with its reference voltage being the output of the linear regulator 102A or 102B as selected by the three-pole switch S1 according to the currently active system (WCDMA or CDMA). In GSM/EDGE mode, the switching regulator 100 is driven from V via S1_mInput receives its V_{ref_sw}Input, and thus function as in fig. 30A.

It should be understood that fig. 21 shows a configuration in which both the switch section 32 and the linear section 34 are "master"; FIG. 22 shows a configuration in which the linear portion 34 is the "master" and the switch portion 32 is the "slave"; and figure 23 shows a configuration in which both the switching section 32 and the linear section 34 are "master" and the switching section 32 operates in open loop. In yet another embodiment of the present invention, the switch portion 32 may function as a "master" and the linear portion 34 functions as a "slave".

Since the switching section 32 is relatively slow, it is also preferable not to use its output V_paAs a reference signal to set the linear part as "slave". Referring to FIG. 21, signal V_{ctrl_sw}Directly related to the duty cycle d of the PWM voltage applied to the LC filter at the node of the pulse width modulator 32. In steady state (constant V)_{ref_sw}) In, V_ctrlAnd an output voltage V_paAnd (4) in proportion. However, in a dynamic state (indeterminate V)_{ref_sw}) The situation is different. For example, if passing V_{ref_sw}Command V_paIncreases rapidly, the result is an error signal V_e1Increase rapidly, resulting in V_{ctrl_sw}Rapidly increases which in turn commands an increase in the duty cycle d. Due to the increased duty cycle, V_paEventually (slowly) increasing to a new higher level. The response of the switching converter is increasing V due to the LC filter_paMiddle ratio is increasing V_ctrl-swAnd the associated duty cycle d is much slower. In other words, V_{ctrl_sw}Comprises and outputs a voltage V_paInformation about the content to occur. V_{ctrl_sw}Is suggestive of a duty cycled is increased so that it represents the output voltage V_paMust be increased. This information may be used to signal the supply current to the linear portion 34 to help increase V_pa. Relatedly, V_{ctrl_sw}Implies a reduction of the duty cycle d and thus it represents the output voltage V_paMust be reduced. This can be used to signal the current sink to the linear portion 34 to help lower V_pa. Thus, V_{ctrl_sw}Contains valuable information that can be used to set the linear stage 34 as "slave".

With reference to the foregoing, this aspect of the invention provides yet another control mechanism in which, as in FIG. 21, instead of V, V_{ref_lin}＝V_mInstead, there is V_{ref_lin}＝G_c3*V_{ctrl_sw}Relationship, wherein G_c3(s) represents the amount of electrical compression in the simplest case and also has frequency dependent characteristics in more complex cases. Suppose, as a non-limiting example, G_c3(s) ═ 1. As described above, in a steady state (constant V)_{ref_sw}Middle), V_{ctrl_sw}And an output voltage V_paAnd (4) in proportion. Again assume, for this non-limiting example, that the proportionality constant is a unity element such that V_pa＝V_{ctrl_sw}And thus also V_{ref_lin}＝V_{ctrl_sw}Thus V_pa＝V_{ref_lin}＝＞V_e20 > the composition of the wireless portion 34. If V is provided_{ref_sw}Is then, as described above, this results in V_{ctrl_sw}Is rapidly increased, and thus V_e2And also increases rapidly, generating a command to the linear part 34 requiring the supply of additional current. Also, if V is provided_{ref_sw}Then this results in V_{ctrl_sw}Decrease rapidly, resulting in V_e2Decreases rapidly and the linear part 32 is thus commanded to sink current. Thus, the linear portion 34 is thus essentially set as "slave" to the switching portion 32.

Similar considerations apply with respect to the embodiment of fig. 23 in which the switching section 32 operates in an open loop, and also apply to fig. 25A and 25bThe embodiments of fig. 26, 27, 29 and 30 are relevant. With particular regard to FIG. 25A, the above-described control configuration implies that V is not_{ref_lin}＝V_mBut instead has V_{ref_lin}＝V_{ctrl_sw}And (4) relationship. Note that although V is not shown in FIG. 25_{ctrl_sw}But V is_{ctrl_sw}Is assumed to be an internal signal to the switching regulator 100 part, and the switching regulator 100 part has a structure such as that shown in fig. 21, that is, a switching section 32 in addition to the controls 36A and 36B.

It will be appreciated that these various embodiments of the present invention allow for an efficient PA supply for a multimode transmitter architecture that can amplitude modulate the PA supply voltage. Some advantages of using these embodiments include: improved efficiency resulting in longer talk times and improved thermal management; and/or the ability to achieve a desired bandwidth; and/or the ability to implement a multi-mode transmitter by one device (presupposing that at least the GSM/EDGE and WCDMA cases should be provided with separate devices).

The use of embodiments of the present invention provides a number of advantages, including high power conversion efficiency. Relatedly, in battery-powered communication devices, longer talk times are provided. Thermal management issues are also managed more efficiently than using a purely linear DC-DC converter, and there is also the possibility to eliminate or at least reduce the size of at least one power supply filter capacitor (e.g. capacitor C in fig. 4A) together.

It is noted that the switching performed in the switching section 32 or the switching regulator 100 is described as a step-down type and has voltage mode control, which is a presently preferred embodiment. However, it should be appreciated that the transition may be of the up/down type. The up/down type is advantageous, but it is more difficult to implement. The up/down type allows the cutoff voltage in a mobile station such as a cellular phone to be lowered because the battery voltage is lowered when its charge is depleted, and the cutoff voltage is the lowest voltage at which the mobile station is kept operating. When the voltage is too low, PA6 cannot produce full output power, and the up/down type solves this problem. For example, by using the rising/falling type switch portion 32, V can be set_batAdjusted to below V_{m_pk}(FIG. 2), whereas in the case of the falling type only, V_batMust be at least equal to V_{m_pk}Plus a certain margin, e.g. V_{m_pk}+ 0.2V. By fast AM modulation as shown in fig. 2, the transition is controlled between rising and falling characteristics, so that the transition does not cause the output voltage V to be_paAnd (4) distortion. In addition, a rising/falling type switching part or converter is used, and at V_{m_pk}＞V_batMust be selected from greater than V_{m_pk}And is therefore greater than V_batThe linear part 34 is powered by a DC source in order to be able to supply current.

It may also be noted that in voltage mode control only the voltage information (e.g. the output voltage of the converter) is used for generating the control signal. However, it is also possible to use current mode control, where in addition to the voltage also current information (e.g. inductor current) is used. In current mode control, there are two control loops, one for current and one for voltage. Of course, other more complex types of controls may be used.

In view of the above description of the preferred embodiments of the present invention, it should be appreciated that these teachings are not limited to use only in GSM/EDGE, WCDMA and/or CDMA systems, but may be used in any type of system having a variable amplitude envelope where the PA supply voltage should be modulated with high efficiency and high bandwidth.

In view of the above description of the preferred embodiments of the present invention, it should be appreciated that these teachings are not limited to use with only class E PAs, but are generally applicable to a variety of SMPAs and generally linear PAs that operate in saturation, such as saturated class B PAs.

In view of the foregoing description of the preferred embodiments of the present invention, it should be appreciated that these teachings are not limited to use with only any particular type of switching converter topology (e.g., not only buck, but also up/down), and not only for voltage mode control.

In view of the above description of the preferred embodiments of the present invention, it should be recognized that these teachings are not limited to use with only a switching section for providing DC and a linear section for providing AC. In practice, it is desirable that the switching part also provides as much AC as possible (when it tries to follow the reference), and the linear part provides the missing AC part (or the missing bandwidth). Thus, embodiments of the invention enhance the overall efficiency as much as possible, since in principle the larger the contribution from the switching section or converter, the higher the efficiency.

In view of the above description of the preferred embodiments of the invention, it will be appreciated that although the linear stage compensates for the non-ideal dynamics of the switching stage, the non-ideal dynamics are also caused to some extent by non-ideal PA behaviour (e.g. load variations), i.e. R_paFollowing V_paChange (i.e., at V)_paDecreasing and increasing) and is in a mismatch condition. Thus, the linear stage 34, 102 compensates at least for non-ideal dynamic characteristics of the switching converter (e.g., insufficient bandwidth and/or peaking referenced into the output characteristics). Further, in this regard, the linear stages 34, 102 and the switching stages 32, 100 complement each other to obtain a particular desired reference-to-output transfer function (not only having a particular bandwidth, but also having a particular shape of the transfer function). For example, the linear stage 34, 102 may have such a reference-to-output transfer function that the resulting reference-to-output transfer function of the hybrid (switched/linear) power supply is of or close to a planar second order butterworth filter type. Thus, the linear stages 34, 102 may be used to shape the resulting overall reference-to-output transfer function in order to obtain the desired characteristics. The linear stages 34, 102 also help track the reference signal and may be used to obtain the reference signal V_mSpecific desired tracking performance.

The linear stage 34, 102 may also compensate at least for switching ripple and may also compensate at least for non-ideal PA behavior, such as R_paAs a function of operating conditions.

It should also be understood that the auxiliary inductor L introduced in fig. 24₁In practice has a similar effect as the converter inductor L shown in fig. 6, as a result of which a current source characteristic is produced. One difference is that in the embodiment of fig. 6 and those embodiments that follow, in the inductorThe input terminal of L is applied with a PWM rectangular voltage, while in the embodiment of fig. 24 and those following, the already smoothed voltage (output of the switching converter 100) is applied to the auxiliary inductor L₁To the input terminal of (1).

In view of the above description of the preferred embodiment of the present invention, it will be appreciated that in the case of GSM/GMSK modulation, the hybrid power supply performs a "power control" function whereby the power level is adjusted by adjusting the voltage level with the power supply. Thus, it will be appreciated that "step control" is used, as opposed to AM control. Note that the goal may be to improve PA6 efficiency, especially when linear PAs are used. When using a linear PA, there will typically be another mechanism to adjust the power level, even at a constant supply voltage V_batBut then at lower power levels the efficiency may be reduced and the DC level may be reduced to increase efficiency. However, with SMPA, the output power is (mainly) controlled by the supply voltage. Thus, it is preferable to control power using PA power supply 30.

In any case, for the fast hybrid power supply 30 according to the preferred embodiment of the invention, and for the GSM case: a) in the TX architecture, the PA power supply is used to control power; b) the PA supply does not have to be very fast (although there are some requirements related to power ramp up/down, they are less demanding than the EDGE case); and c) advantageously, the switching ripple is compensated by the hybrid power supply 30, as in the EDGE case.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best method and apparatus presently contemplated by the inventors for carrying out the invention. However, various changes and modifications may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. For example, while the power supply of the present invention has been described above in the context of polar or ER transmitter embodiments, the present invention is applicable to other applications in which the power supply must meet stringent dynamic requirements while also exhibiting high efficiency. 6-30 may not be understood to limit the number of possible embodiments that a hybrid voltage regulator may assume, or to limit the number of RF power amplifiers and RF communication system types for which embodiments of the present invention may be used. In general, all such and similar modifications of the teachings of this invention will still fall within the scope of the embodiments of this invention.

Furthermore, some of the features of the present invention could be used to advantage without the corresponding use of other features. As such, the foregoing description should be considered as merely illustrative of the principles of the present invention, and not in limitation thereof.

Claims (87)

1. A dc-dc converter comprising:

a switch-mode portion for coupling between a DC source and a load, the switch-mode portion providing an x amount of output power; and

a linear mode section coupled between the same or a different DC source and the load in parallel with the switch mode section, the linear mode section providing an output power of an amount y, where x is greater than y, and the ratio of x to y can be optimized for application specific constraints,

wherein the linear mode portion exhibits a faster response time to a desired change in output voltage than the switch mode portion, wherein the linear mode portion provides an alternating current component to the load. .

2. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises at least one power operational amplifier operating as a variable voltage source.

3. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises at least one power operational transconductance amplifier operating as a variable current source.

4. The dc-dc converter of claim 1 wherein the linear mode section provides a dc component and an ac component to the load.

5. The dc-dc converter of claim 1 wherein the output of the linear mode section compensates for ac ripple output from the switch mode section.

6. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises a bi-directional voltage controlled voltage source.

7. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises a bi-directional Voltage Controlled Voltage Source (VCVS) and comprises two voltage controlled voltage source circuits, wherein in operation, one operates as a sink and one operates as a source.

8. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises a bi-directional voltage controlled current source.

9. The dc-to-dc converter of claim 1 wherein the linear mode portion comprises a bi-directional Voltage Controlled Current Source (VCCS) and comprises two voltage controlled current source circuits, one operating as a sink and one operating as a source.

10. The dc-dc converter of claim 1, wherein the switch mode portion and the linear mode portion are commonly controlled by a control signal in a closed loop manner.

11. The dc-to-dc converter of claim 1 wherein the switch mode portion is controlled by an output from the linear mode portion in a closed loop manner, and wherein the linear mode portion is controlled by a control signal in a closed loop manner.

12. The dc-to-dc converter of claim 1, wherein the switch mode portion operates in an open loop, and wherein the linear mode portion is controlled by a control signal in a closed loop manner.

13. The dc-to-dc converter of claim 1 wherein the linear mode portion is effectively slaved to operation of the switch mode portion to supply or sink current.

14. The dc-dc converter of claim 1, wherein the switch-mode section is provided with little or no output filter capacitance to essentially function as a current source.

15. A dc-dc converter as claimed in claim 1, wherein the switch mode part is provided with an output filter capacitance and acts substantially as a voltage source.

16. The dc-dc converter of claim 1 wherein the switch mode portion is coupled to the load and to an output of the linear mode portion through an inductor.

17. The dc-to-dc converter of claim 1 wherein the load comprises at least one radio frequency power amplifier.

18. The dc-to-dc converter of claim 10 wherein the load comprises at least one Radio Frequency (RF) power amplifier, and wherein the control signal comprises a radio frequency carrier modulated signal.

19. The dc-to-dc converter of claim 11 wherein the load comprises at least one Radio Frequency (RF) power amplifier, and wherein the control signal comprises a radio frequency carrier modulated signal.

20. The dc-to-dc converter of claim 12 wherein the load comprises at least one Radio Frequency (RF) power amplifier, and wherein the control signal comprises a radio frequency carrier modulated signal.

21. The dc-dc converter of claim 1 wherein the linear mode part is coupled to an output of the switch mode part and to the load through a capacitance.

22. The dc-to-dc converter of claim 1 wherein the switch-mode portion is coupled to the load and to an output of the linear-mode portion through an inductance, and wherein the linear-mode portion is coupled to the output of the switch-mode portion through the inductance and to the load through a capacitance.

23. The dc-dc converter of claim 1 wherein the linear mode portion compensates at least to some extent for load variations.

24. The dc-dc converter of claim 1, wherein the linear mode portion compensates at least to some extent for non-ideal dynamics of the switch mode portion.

25. A Radio Frequency (RF) Transmitter (TX) for coupling to an antenna, the transmitter having a polar structure consisting of an Amplitude Modulation (AM) path coupled to a Power Amplifier (PA) supply and a Phase Modulation (PM) path coupled to an input of the power amplifier, wherein the supply includes a switch-mode portion for coupling between a power source and the power amplifier, the switch-mode portion providing an x amount of output power, the supply further including a linear-mode portion coupled in parallel with the switch-mode portion between the power source and the power amplifier, the linear-mode portion providing a y amount of output power, wherein x is greater than y and a ratio of x to y can be optimized for a particular application constraint, and wherein the linear-mode portion exhibits a faster response time to a desired change in output voltage than the switch-mode portion, wherein the linear mode portion provides an alternating current component to the power amplifier.

26. The radio frequency transmitter of claim 25 wherein the linear mode portion comprises at least one power operational amplifier operating as a variable voltage source.

27. The radio frequency transmitter of claim 25 wherein the linear mode portion comprises at least one power operational transconductance amplifier operating as a variable current source.

28. The radio frequency transmitter of claim 25 wherein the linear mode section provides a dc component and an ac component to the power amplifier.

29. The radio frequency transmitter of claim 25 wherein the output of the linear mode section compensates for ac ripple output from the switch mode section.

30. The radio frequency transmitter of claim 25, wherein the linear mode portion comprises a bi-directional voltage controlled voltage source.

31. The radio frequency transmitter of claim 25 wherein the linear mode section comprises a bi-directional Voltage Controlled Voltage Source (VCVS) and comprises two voltage controlled voltage source circuits, wherein in operation, one operates as a sink and one operates as a source.

32. The radio frequency transmitter of claim 25 wherein the linear mode portion comprises a bi-directional voltage controlled current source.

33. The radio frequency transmitter of claim 25 wherein the linear mode portion comprises a bi-directional Voltage Controlled Current Source (VCCS) and comprises two voltage controlled current source circuits, one operating as a sink and one operating as a source.

34. The radio frequency transmitter of claim 25, wherein the switch mode portion and the linear mode portion are commonly controlled by a control signal in a closed loop manner, wherein the control signal comprises an amplitude modulated signal.

35. The radio frequency transmitter of claim 25, wherein the switch mode portion is controlled in a closed loop manner by an output from the linear mode portion, and wherein the linear mode portion is controlled in a closed loop manner by a control signal, wherein the control signal comprises an amplitude modulated signal.

36. The radio frequency transmitter of claim 25, wherein the switch mode portion operates in an open loop, and wherein the linear mode portion is controlled in a closed loop manner by a control signal, wherein the control signal comprises an amplitude modulated signal.

37. The radio frequency transmitter of claim 25, wherein the linear mode portion is operatively slaved to operation of the switch mode portion to supply or sink current.

38. The radio frequency transmitter of claim 25 wherein the switch mode portion is provided with little or no output filter capacitance to function substantially as a current source.

39. The radio frequency transmitter of claim 25 wherein the switch mode portion is provided with an output filter capacitance and functions substantially as a voltage source.

40. The radio frequency transmitter of claim 25 wherein the switch mode section is coupled to the power amplifier and is inductively coupled to an output of the linear mode section.

41. The radio frequency transmitter of claim 25 wherein the switch mode portion is coupled to the power amplifier and to an output of the linear mode portion through an inductance, and wherein the linear mode portion is coupled to the output of the switch mode portion through the inductance and to the power amplifier through a capacitance.

42. The radio frequency transmitter of claim 25, wherein the power supply provides greater power conversion efficiency than a purely linear voltage regulator based power supply while also providing a wider operating bandwidth than a purely switch mode power supply based power supply.

43. The radio frequency transmitter of claim 25 wherein the linear mode section is coupled to an output of the switch mode section and to the load through a capacitance.

44. The radio frequency transmitter of claim 25 wherein the linear mode portion compensates at least to some extent for the load variations exhibited by the power amplifier.

45. The radio frequency transmitter of claim 25 wherein the linear mode portion compensates at least to some extent for non-ideal dynamics of the switch mode portion.

46. A Radio Frequency (RF) Transmitter (TX) for coupling to an antenna, the transmitter having a polar structure consisting of an Amplitude Modulation (AM) path coupled to a Power Amplifier (PA) supply and a Phase Modulation (PM) path coupled to an input of the power amplifier, wherein the supply includes a switch-mode stage for coupling between a power source and the power amplifier, the switch-mode stage providing an x amount of output power, the supply further including at least one linear-mode stage coupled in parallel with the switch-mode stage between the power source and the power amplifier, the linear-mode stage providing a y amount of output power, wherein x is greater than y and a ratio of x to y can be optimized for a particular application constraint, the supply further including at least one auxiliary inductor coupled between an output of the switch-mode stage and an output of the at least one linear-mode stage, wherein the at least one linear mode stage provides an alternating current component to the power amplifier.

47. The radio frequency transmitter of claim 46 wherein the power amplifier is coupled to an output of the switch-mode stage before the auxiliary inductor, and further comprising at least one additional power amplifier coupled to an output of the switch-mode stage after the auxiliary inductor.

48. The radio frequency transmitter of claim 46 wherein the power amplifier is coupled to an output of the switch-mode stage after the auxiliary inductance, and further comprising at least one additional power amplifier also coupled to an output of the switch-mode stage after the auxiliary inductance.

49. The radio frequency transmitter of claim 46 wherein the power amplifier is coupled to the output of the switch-mode stage before the first auxiliary inductor and the second auxiliary inductor, and further comprising a second power amplifier coupled to the output of the switch-mode stage after the first auxiliary inductor and a third power amplifier coupled to the output of the switch-mode stage after the second auxiliary inductor.

50. The radio frequency transmitter of claim 49 wherein the second power amplifier is further coupled to an output of the first linear mode stage and the third power amplifier is coupled to an output of the second linear mode stage.

51. The radio frequency transmitter of claim 46 wherein the power amplifier is coupled to an output of the switch-mode stage after a first auxiliary inductance, and further comprising a second power amplifier coupled to an output of the switch-mode stage after a second auxiliary inductance, wherein the power amplifier is further coupled to an output of the first linear-mode stage and the second power amplifier is coupled to an output of the second linear-mode stage.

52. The radio frequency transmitter of claim 46, wherein the at least one linear mode stage comprises at least one power operational amplifier operating as a variable voltage source.

53. The radio frequency transmitter of claim 46, wherein the at least one linear mode stage comprises at least one power operational transconductance amplifier operating as a variable current source.

54. The radio frequency transmitter of claim 46, wherein the at least one linear mode stage provides a DC component and an AC component to the power amplifier.

55. The radio frequency transmitter of claim 46 wherein the output of the at least one linear mode stage compensates for an AC ripple output from the switch mode stage.

56. The radio frequency transmitter of claim 46, wherein the switch mode stage and the at least one linear mode stage are commonly controlled by a control signal in a closed loop manner, wherein the control signal comprises an amplitude modulated signal.

57. The radio frequency transmitter of claim 46, wherein the switch mode stage is controlled in a closed loop manner by an output from the at least one linear mode stage, and wherein the at least one linear mode stage is controlled in a closed loop manner by a control signal, wherein the control signal comprises an amplitude modulated signal.

58. The radio frequency transmitter of claim 46, wherein the switch mode stage operates in an open loop, and wherein the at least one linear mode stage is controlled in a closed loop manner by a control signal, wherein the control signal comprises an amplitude modulated signal.

59. The radio frequency transmitter of claim 46 wherein the at least one linear mode stage is operatively slaved to operation of the switch mode stage to supply or sink current.

60. The radio frequency transmitter of claim 46 wherein the switch mode stage is provided with an output filter capacitance and functions substantially as a voltage source and provides a smoothed voltage signal to the auxiliary inductance.

61. The radio frequency transmitter of claim 46 wherein the at least one linear mode stage is coupled to an output of the switch mode stage and to the power amplifier through a capacitor.

62. The radio frequency transmitter of claim 46 wherein the at least one linear mode stage compensates at least to some extent for variations in the load exhibited by the power amplifier.

63. The radio frequency transmitter of claim 46 wherein the at least one linear mode stage compensates at least to some extent for non-ideal dynamics of the switch mode stage.

64. A radio frequency transmitter as in claim 46, further comprising a switch coupled to a reference input of the switch mode stage to selectively apply different reference signals to the switch mode stage as a function of operating mode.

65. The radio frequency transmitter of claim 64, wherein one mode of operation comprises a GSM mode.

66. A radio frequency transmitter as in claim 64, where one mode of operation comprises an EDGE mode.

67. The radio frequency transmitter of claim 64 wherein one mode of operation comprises a CDMA mode.

68. The radio frequency transmitter of claim 64, wherein one mode of operation comprises a WCDMA mode.

69. The radio frequency transmitter of claim 46 further comprising a switch coupled to a feedback input of the at least one linear mode stage to selectively apply different feedback signals to the at least one linear mode stage as a function of operating mode.

70. A radio frequency transmitter as in claim 69, where one mode of operation comprises a GSM mode.

71. A radio frequency transmitter as in claim 69, where one mode of operation comprises an EDGE mode.

72. The radio frequency transmitter of claim 69 wherein one mode of operation comprises a CDMA mode.

73. The radio frequency transmitter of claim 69, wherein one mode of operation comprises a WCDMA mode.

74. A method of operating a Radio Frequency (RF) Transmitter (TX) having a polar structure consisting of an Amplitude Modulation (AM) path coupled to a Power Amplifier (PA) supply and a Phase Modulation (PM) path coupled to an input of the PA, the method comprising:

providing the power supply to include a switch mode portion coupled between a power source and the power amplifier, the switch mode portion providing x amounts of output power; and

coupling a linear mode portion in parallel with the switch mode portion between the power source and the power amplifier, the linear mode portion providing an output power of an amount y, wherein x is greater than y, and a ratio of x to y is optimized for a particular application constraint, and wherein the linear mode portion exhibits a faster response time to a desired change in output voltage than the switch mode portion, wherein the linear mode portion provides an alternating current component to the power amplifier.

75. The method of claim 74, wherein the linear mode portion comprises at least one power operational amplifier operating as a variable voltage source or at least one power operational transconductance amplifier operating as a variable current source.

76. A method as in claim 74, wherein the linear mode portion provides a DC component and an AC component to the power amplifier.

77. The method of claim 74 further comprising operating the linear mode section to compensate for at least one of an AC ripple output from the switch mode section, the load variations exhibited by the power amplifier, and non-ideal dynamics of the switch mode section.

78. The method of claim 74, wherein the linear mode portion comprises a bi-directional voltage controlled voltage source or a bi-directional voltage controlled current source.

79. The method of claim 74, further comprising jointly controlling the switch mode portion and the linear mode portion with a control signal in a closed-loop manner, wherein the control signal comprises an amplitude modulated signal.

80. A method as in claim 74, further comprising controlling the switch mode portion in a closed loop manner with an output from the linear mode portion and controlling the linear mode portion in a closed loop manner with a control signal comprising an amplitude modulation signal.

81. A method as in claim 74, further comprising operating the switch mode portion in an open-loop manner and controlling the linear mode portion in a closed-loop manner with a control signal comprising an amplitude modulation signal.

82. A method according to claim 74, further comprising operating the linear mode portion so as to be operatively slaved to operation of the switched mode portion to supply or sink current.

83. A method according to claim 74, comprising operating the switch mode portion to function substantially as a current source.

84. A method according to claim 74, comprising operating the switch mode portion to function substantially as a voltage source.

85. A method as in claim 74, further comprising coupling the switch-mode portion to the power amplifier and to an output of the linear-mode portion through an inductor.

86. A method as in claim 74, further comprising coupling the switch-mode portion to the power amplifier and through an inductance to an output of the linear-mode portion, and wherein the linear-mode portion is coupled through the inductance to an output of the switch-mode portion and through a capacitance to the power amplifier.

87. A method as in claim 74, further comprising coupling the linear mode section to an output of the switch mode section and to the power amplifier through a capacitor.