CN1871690A - Method of manufacturing semiconductor device - Google Patents

Abstract

It is an object of the present invention to provide a method for manufacturing a semiconductor device in which prevention of disconnection due to a step caused by a surface shape before film formation, control of increase in the cost in forming an insulating film over a large-sized substrate, improvement of the usability efficiency of a material, and a reduction in the amount of waste are realized. In the invention, a first insulating film is formed by discharging a composition, a second insulating film is selectively formed over the first insulating film, and an opening is formed by etching the first insulating film by using the second insulating film as a mask. Afterwards, a conductive film is formed by discharging a composition over the opening, and a wiring in a lower layer and a wiring in an upper layer are connected each other with an insulating film therebetween.

Description

Method for manufacturing semiconductor device

(1) Technical field

The present invention relates to a method of manufacturing a semiconductor device using a droplet dispensing method typified by an inkjet method, and particularly relates to a technique of forming an insulating film constituting a semiconductor device.

(2) Background technology

In recent years, semiconductor devices using thin film transistors have been widely used in large-sized liquid crystal display devices such as televisions and portable terminals such as mobile phones, and are also being actively developed.

The drop-drop method has various advantages such as no need for a mask, easy increase in size of a substrate, high usage rate of materials, possibility of reducing equipment investment amount, and minimizing the size of manufacturing equipment. Therefore, the dripping method can be applied to the manufacture of color filter films or lead wires, electrodes, etc. of plasma displays.

In conventional methods of manufacturing semiconductor devices, very complicated steps are used to form patterns of circuits and the like. For example, the following briefly describes the steps of manufacturing a semiconductor device in which leads of a lower layer and leads of an upper layer are connected to each other with an insulating film in between.

Initially, a conductive film to be a wiring base is formed on an insulating surface, and a photoresist is formed on the entire surface of the insulating film by using spin coating. Subsequently, a region for wiring is designated on the conductive film, and a photoresist pattern is formed by exposing and developing to form desired wiring by etching the conductive film. Then, an insulating film is formed on the leads by CVD, sputtering, spin coating, etc., and a photoresist is formed on the insulating film. Then, the insulating film is selectively etched to form an opening by using the photoresist on which the exposure and development processes are performed as a mask as above to expose the wiring in the lower layer. Then, a conductive film is formed to fill the opening, and a photoresist is formed on the conductive film. Thereafter, by using the photoresist on which the exposure and development treatments have been performed as a mask, the conductive film is etched to form the conductive film of the upper layer connected to the wiring in the lower layer.

(3) Contents of the invention

In the above manufacturing steps, an insulating film is formed by sputtering, CVD, spin coating, or the like. The surface shape of an insulating film formed by sputtering or CVD depends on the surface shape before the film is formed. Therefore, when there is a step in the surface shape before the film is formed, there is a problem of disconnection due to the step or the like after the insulating film is formed. In addition, sputtering and CVD are gas phase processes using a vacuum device. Therefore, when an insulating film is formed on one side of a substrate having a large size of one meter or more, the size of the device inevitably increases, resulting in an increase in cost.

On the other hand, when an insulating film is formed by spin coating, the shape of the insulating film does not depend on the surface shape before film formation. However, when the size of the substrate is increased, the film thickness at the end portion of the substrate becomes thicker compared with the central portion, so that the uniformity of the film thickness of the insulating film cannot be maintained. In addition, in spin coating, liquid resin is dispersed on the substrate by centrifugal acceleration, and excess resin drips from the edge of the substrate, thereby forming a thinner resin film on the surface of the substrate. Therefore, the usability of the material is poor and excess resin becomes waste.

In view of the above practical conditions, it is an object of the present invention to provide a method for manufacturing a semiconductor device in which disconnection due to a step due to a surface shape before film formation does not occur. Furthermore, in the case of forming an insulating film on a large-sized substrate, an object of the present invention is to provide a method of manufacturing a semiconductor device in which an increase in size of a device is not required and an increase in cost can be suppressed. Furthermore, it is an object of the present invention to provide a method of manufacturing a semiconductor device in which an improvement in availability of materials and a reduction in the amount of waste can be achieved.

In order to solve the above-mentioned problems of the conventional art, the present invention implements the following steps.

A feature of the present invention is that a first insulating film is formed by dripping a composition including an insulator, a second insulating film is formed on the first insulating film, a mask pattern is formed by exposing and developing on the second insulating film, using The second insulating film is used as a mask, and an opening is formed by etching the first insulating film. Here, although the second insulating film can be formed by a known method such as spin coating, the insulating film can be formed with a minimum of materials using the spot-drop method. Note that in the present invention, the dripping method means a method of forming by selectively dripping a drop (also referred to as a spot) of a composition of materials including a conductive film, an insulating film, etc. at an arbitrary point, according to which the method also It can be called inkjet method.

A feature of the present invention is that, in the above structure, after forming the first insulating film, an insulating film as a mask is formed at an arbitrary point by selectively dripping a composition including an insulator again. By selectively forming a mask, exposure and development steps become unnecessary. A material used as a mask is not limited to an insulating film. Therefore, when a selective ratio of etching rate can be obtained with respect to the first insulating film being etched, a conductive film serving as a mask can be formed by dropping a composition including a conductive material or the like instead of the second insulating film.

The present invention is a method for manufacturing a semiconductor device in which an insulating film is formed by dropping a composition. As its features, one feature is that an insulating film provided with an opening is produced by performing etching after forming a mask on the insulating film, and furthermore, an inert gas is added to the insulating film. Specifically, the inert element is one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe), and one feature is that an insulating film is formed to The inert gas is included at a concentration of from 1×10 ¹⁹ atoms/cm ³ to 5×10 ²¹ atoms/cm ³ , preferably from 2×10 ¹⁹ atoms/cm ³ to 2×10 ²¹ atoms/cm ³ .

A feature of the present invention is that, in the above structure, the opening is formed to have a wedge shape, specifically, the opening may be formed to have a wedge shape from 30° or more than 30° to less than 75°. By forming the wedge-shaped opening, it is made easy to add the inert gas to the sides of the opening.

A feature of the present invention is that the barrier layer is formed by dripping a composition including a conductive material onto the sides of the formed opening. Here, the film used as the barrier layer is not limited to a conductive film, and an insulating film may be used as the barrier layer. For example, when the barrier layer is formed in a region where there is a possibility of a short circuit with a lead wire, it is preferable that the barrier layer is formed of a resin material.

A feature of the insulating film of the present invention is that the insulating film is made of an organic material or a material in which bonds of silicon and oxygen form a skeleton structure. Here, the organic material means acrylic, polyimide, benzocyclobutene, polyamide, and the like. In addition, a material having a skeleton structure composed of bonds of silicon and oxygen generally refers to a compound material formed by polymerization of a polymer including siloxane or the like. Specifically, a material in which a bond of silicon and oxygen constitutes a skeleton structure and at least hydrogen is contained as a substituent, or a material having at least one of fluorine, an alkyl group, or an aromatic hydrocarbon as a substituent is included.

A feature of the present invention is that planarization is performed after the insulating film is formed by dropping the composition. As a method of planarization treatment, a known method can be used. Specifically, planarization methods such as reflow planarization, CMP planarization, bias sputtering planarization, etch-back planarization, or combinations thereof may be used to perform the planarization process.

A feature of the present invention is that, in the above structure, the conductive film filling the opening is formed by dripping a composition including a conductive material to an opening provided in an insulating film formed by dripping the composition. . It is also a feature of the present invention that the conductive film is made of a material including silver, gold, copper or indium tin oxide.

In the present invention, the insulating film is formed by dripping a composition. Thus, it is possible to apply the desired amount of material to any point in the drip at any distance. Therefore, the shape of the manufactured insulating film does not depend on the shape before film formation, and disconnection due to steps in the wiring layer can be prevented. Furthermore, since only the required amount of material needs to be applied, the availability of material can be increased and the amount of waste can be reduced. In the case of forming an insulating film on a large-sized substrate, since an enlarged device is not required, an increase in cost can be suppressed.

(4) Description of drawings

1A to 1E are schematic diagrams illustrating a method of manufacturing an insulating film (Embodiment Mode 1).

2A to 2D are schematic diagrams illustrating a method of manufacturing an insulating film (Embodiment Mode 1).

3A and 3B are schematic diagrams illustrating a method of manufacturing an insulating film (Embodiment Mode 2).

4A and 4B are schematic diagrams illustrating a method of manufacturing an insulating film (Embodiment Mode 3).

5A and 5B are schematic views illustrating a method of manufacturing an insulating film (Embodiment Mode 4).

6A to 6C are diagrams illustrating a method of planarizing an insulating film (Embodiment Mode 5). ;

7A to 7D are schematic views illustrating a method of manufacturing a semiconductor device (Embodiment 1).

8A to 8C are schematic diagrams illustrating a method of manufacturing a semiconductor device (Embodiment 1).

9A to 9E are schematic diagrams illustrating a method of manufacturing a semiconductor device (Embodiment 1).

10A to 10D are schematic diagrams illustrating a method of manufacturing a multilayer lead according to the present invention (Embodiment 4).

11A to 11D are schematic diagrams illustrating a method of manufacturing a semiconductor device (Embodiment 2).

12A and 12B are schematic views illustrating a method of manufacturing a semiconductor device (Embodiment 3).

Fig. 13 is a schematic view of a display panel which is one form of a semiconductor device to which the present invention is applied (Embodiment 5).

14A to 14C are schematic diagrams showing electronic equipment to which the present invention is applied (Embodiment 6).

(5) specific implementation

Embodiment mode 1

An embodiment mode of the present invention is described with reference to FIGS. 1A to 1E.

First, the first substrate 100 is prepared. A glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, or a plastic substrate capable of withstanding the processing temperature of this manufacturing step may be used for the substrate 100 . At this time, a base film made of an insulator or a semiconductor layer, or a conductive film may have been formed on the substrate 100 . Then, the insulating film 101 is formed by dropping a composition made of an insulator on the substrate 100 .

A composition in which an insulator is dissolved or dispersed in a solvent is used as the composition dripped from the nozzle 109 . As the insulator, resin such as epoxy resin, acrylic resin, phenol resin, novolac resin, melamine resin, or polyurethane resin can be used. When using these resins, the viscosity can be adjusted by dissolving or dispersing the resin material using a solvent. As the lyophobic material, a resin including fluorine atoms, a resin configured only with hydrocarbons or the like can be used. In more detail, a resin including a monomer containing fluorine atoms in the molecule, or a resin including a monomer configured only with carbon atoms or hydrogen atoms can be exemplified. In addition, organic materials such as acrylic, benzocyclobutene, parylene, flare, or permeable polyimide, such as those made of Compound materials produced by polymerization of polymers such as siloxane, such as composites containing water-soluble homopolymers and water-soluble copolymers. Organic materials are suitable for use due to their high planarity. Therefore, when the conductive material is subsequently formed, the film thickness does not become extremely thin at the stepped portion, or is not disconnected. However, when an organic material is used, a thin film may be formed of an inorganic material containing silicon under or over an insulating film made of an organic material to prevent outgassing. Specifically, a silicon nitride oxide film or a silicon nitride film may be formed using plasma CVD or sputtering.

A polymer including siloxane can be used as a typical example of a material in which a bond of silicon and oxygen constitutes a skeleton structure, and at least hydrogen is contained as a substituent, or has at least one of fluorine, an alkyl group, or an aromatic hydrocarbon material as a substituent. Therefore, various materials within the range of the above conditions can be used. Polymers including siloxanes have better planarity, even clarity and thermal stability. Therefore, after forming an insulator made of a polymer including siloxane, heat treatment may be performed at a temperature from about 300°C to 600°C or lower. By heat treatment, for example, hydrogenation and baking treatment can be performed at the same time. In addition, by adjusting the kind or concentration of the solvent, the viscosity of the polymer including siloxane can be controlled. Therefore, the polymer including siloxane can be applied to various uses by appropriately using it according to the purpose of use.

As the solvent, esters such as butyl acetate and ethyl acetate, alcohols such as isopropanol and ethanol, organic solvents such as methyl ethyl ketone and acetone, and the like can be used. The viscosity of the composition is preferably 50 cp or less in order to prevent drying or drip the composition from the outlet smoothly. The surface tension of the composition is preferably 40 Mn/m or less. Depending on the solvent or application to be used, the viscosity and the like of the composition can be adjusted as necessary. For example, the viscosity of ITO, organic indium or organic tin dissolved or dispersed in a solvent is from 5mPa·S to 50mPa·S. The viscosity of silver dissolved or dispersed in the solvent is from 5mPa·S to 20mPa·S. The viscosity of ITO and gold dissolved or dispersed in the solvent is from 10mPa·S to 20mPa·S.

As described above, the first insulating film 101 can be formed by selectively dripping a composition on the substrate 100 by the spotting method (FIG. 1A). Since the spot-under-drop method can selectively form an insulating film on a desired portion on a substrate (for example, the entire surface except the end portion of the substrate), it is possible to improve the efficiency of material use.

Then, by dropping a composition, a photoresist made of an insulator (second insulating film) is formed on the first insulating film 101 (FIG. 1B). Here, a photoresist that reacts to ultraviolet rays is dropped and formed as a second insulating film. A composition containing a photosensitizer can be used as a photoresist, for example, using one that is dissolved or dispersed in a solvent such as a novolak resin, diphenyl silane diol, and an acid generator as a typical positive photoresist. composite. Known solvents can be used as the solvent. In addition, the photoresist 102 can be formed by spin coating. However, since the droplet method is used, the photoresist does not have to be formed in unnecessary edge portions of the substrate, and the photoresist can be formed only in desired regions.

Then, by performing exposure and development steps (FIG. 1C), the photoresist 102 can be formed into a desired shape (FIG. 1D). Although the exposure and development steps are performed using a positive-type photoresist, this step can also be performed using a negative-type photoresist.

Then, by using the processed photoresist as a mask, the insulating film 101 not covered by the mask is etched to form openings 103 and 104 (FIG. 1E).

Wet etching using chemicals such as sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid, or dry etching generally using RIE (Reactive Ion Etching) can be used for the etching process, depending on the purpose of use It can be selected appropriately. Depending on the purpose to be processed, an etching gas may be appropriately selected, and a fluorine-based gas such as CF ₄ , NF ₃ or SF ₆ or a chlorine-based gas such as Cl ₂ or BCl ₃ may be used for etching.

Specifically, when the first insulating film is formed of a polymer including siloxane, an inert gas may be added to an etching gas to be used. As the inert element to be added, one or more selected from He, Ne, Ar, Kr, or Xe can be used. In this embodiment mode, etching is performed by using CF ₄ , O ₂ , He, and Ar. In addition, over-etching may be performed by increasing the etching time at a rate of about 10% to 20%, so as to perform etching without leaving any residue on the substrate 100 . The wedge shape can be formed by performing one or more etchings.

The second insulating film 102 used as a mask can be removed using a stripping solution. Evaporation can be done by decomposing and converting O ₃ (ozone) into oxygen radicals as a reactive gas to react with the photoresist using a plasma asher that is removed and evaporated by the reaction of the insulating film with the plasma gas Ozone incinerators for insulating films, wet stations equipped with chemical tanks ideal for dissolving insulating films, etc. When using a plasma asher or an ozone asher, impurities such as heavy metals contained in the actual insulating film are removed. Therefore, it is preferable to use a wet workstation for cleaning. In this way, photoresist residues can be completely removed by sequentially performing wet processing after the dry ashing step.

As described above, the insulating film is formed by dripping the composition, and the insulating film can be formed without using an enlarged apparatus. Therefore, the consumption of material can be minimized. In addition, by forming the photoresist as a mask by the drop casting method instead of the spin coating method, it is possible to improve the use efficiency of the material.

(Embodiment mode 2)

2A to 2D are used to describe Embodiment Mode 2 of the present invention. In Embodiment Mode 2, a method of manufacturing an insulating film while selectively dropping an insulator serving as a mask to form a mask is described.

First, a composition is dropped on the substrate 100 to form the first insulating film 101 as in Embodiment Mode 1 (FIG. 2A).

Then, a composition different from the first insulating film is selectively dropped on the first insulating film 101 to form a mask (second insulating film) 202 made of a material such as photoresist or polyimide. class was made (Figure 2B). A mask capable of obtaining a selectivity ratio of etching with respect to the first insulating film 101 can be used as the mask 202 .

Then, by using the second insulating film 202 as a mask, an etching process is performed on a part of the first insulating film 101 not covered with the mask to form openings 203 and 204 . This etching process can be performed as in the first embodiment. In addition, a spot instillation method may be used for forming the openings. In this case, the opening may be formed by dripping wet etching solution from the nozzle 109 . However, it may be appropriate to provide a cleaning step with a solvent such as water to control the aspect ratio of the openings. Naturally, by applying the drip method also to the cleaning step, by turning the drip dripped from the nozzle into water, or by changing the head in which the solution is filled, it is possible to use the same device for continuous treatment, which can try to Reduce processing time.

Then, the second insulating film 202 serving as a mask is removed using a stripping liquid. Through the above steps, openings 203 and 204 are formed in insulating film 101 (FIG. 2C).

Next, a composition including a conductive material is dropped into the openings 203 and 204 to form conductive films 205 and 206 (FIG. 2D).

As the composition for forming the conductive film, a composition in which a conductive material is dissolved or dispersed in a solvent can be used. Conductive materials correspond to metals such as Ag, Cu, Ni, Pt, Pd, Ir, Rh, W, and Al, sulfides of Cd and Zn, oxides of Fe, Ti, Si, Ge, Zr, and Ba, or silver halides particles or dispersant nanoparticles. Alternatively, the conductive material corresponds to indium tin oxide (hereinafter referred to as "ITO") used as a transparent conductive film, ITSO containing ITO and silicon oxide, organic indium, organic tin, zinc oxide (ZnO), titanium nitride (TiN) wait. However, a composition in which any material of gold, silver, and copper is dissolved or dispersed in a solvent is preferably used as the composition dripped from a nozzle in consideration of a specific resistance value. More preferably, it is available as low resistance silver or copper. However, when using silver or copper, a barrier layer can be provided as a measure for impurities.

The particle diameter of the conductive material is preferably as small as possible to prevent clogging, although the composition made from the conductive material being dripped depends on the diameter and shape required for each nozzle fitted to the head Nozzles and for making precise graphics. Preferably, the particle diameter is 0.1 μm or less. Compositions are made by known methods such as electrolysis, atomization, or moisture reduction, so that the particle size is typically on the order of from 0.5 μm to 10 μm. Each nanomolecule protected by the dispersant is tiny and about 7nm in size when the composite is produced by the vapor phase evaporation method. Furthermore, when each surface of the nanoparticles is covered with a coating, the nanoparticles in the solvent do not adhere to each other and are uniformly dispersed in the solvent at room temperature, thereby exhibiting a behavior similar to an aqueous fluid. Thus, such coatings are preferably used.

As described above, by selectively dropping a composition at an arbitrary position to form an insulating film as a mask, the exposure and development steps can be omitted. In addition, by selectively dripping a composition to form a conductive material, it is also possible to omit exposure and development steps when forming a lead. Therefore, a wiring layer can be formed on one side of a large-sized substrate exceeding 1 meter at a lower cost and a higher yield.

(Embodiment mode 3)

In Embodiment Mode 3, a case where an inert element is added to an insulating film manufactured by the spot-drop method, which is another feature of the present invention, will be described with reference to FIGS. 3A and 3B .

When an inert element with a relatively large atomic radius is added, the insulating film is deformed, and thus impurity components such as water vapor and oxygen are prevented from entering by modifying and densifying the surface. In addition, by adding impurity components, solution components can be prevented from entering the insulating film or even reacting in the subsequent step using a liquid (hereinafter also referred to as a wet step). In addition, release of moisture or gas from the inside of the insulating film can also be prevented. In particular, the release of moisture and gas due to changes over time can be prevented. Reliability can thus be enhanced in accordance with the above-described effects.

A method of adding an inert element to an insulating film will be described with reference to FIGS. 3A and 3B. As in the method shown with reference to FIGS. 1A to 1E or FIGS. 2A to 2D , the steps of forming an insulating film 301 on a substrate 300 and forming openings 303 and 304 in the insulating film 301 by using a droplet method are performed. In addition, the openings 303 and 304 may also be formed in a wedge shape in which the diameter becomes smaller downward by controlling the etching conditions (FIG. 3A).

Then, an inert element 305 is added to the insulating film 301, and the insulating film 301 is formed into a wedge shape to form a dense portion 310 on the surface of the insulating film. A known method such as an ion doping method, an ion implantation method, or a plasma treatment method can be used as a method of adding an inert element. As the inert element to be added, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) can be used. Preferably, argon (Ar), which has a relatively large atomic radius and is cheap, can be used. In addition, a material that does not lower the permeability of the insulating film even when an inert element is added can be used. Deformation can be produced by adding inert elements with relatively large atomic radii, and the entry of water vapor and oxygen can be prevented by modifying and densifying the surface (including the sides). Since the inert element is not sufficiently doped to the side surface of the opening or the side of the edge portion when the bevel angle is not enough, further doping can be performed from the oblique direction, or the addition of the inert element to the side surface by plasma treatment can be increased. Treatment of the side of the opening or the side of the edge portion.

An insulating film including an inert element at a concentration of from 1×10 ¹⁹ atoms/cm ³ to 5×10 ²¹ atoms/cm ³ , preferably from 2×10 ¹⁹ atoms/cm ³ to 2×10 ²¹ atoms/cm ³ may be formed. Later, if necessary, a conductive film, a semiconductor or an insulating film may be formed on the insulating film.

According to this embodiment mode, by adding impurity components and by modifying the surface of the insulating film, solution components can be prevented from entering the insulating film or reacting in a subsequent step using a liquid (also referred to as a wet step). In addition, release of moisture or gas from the insulating film can also be prevented at the time of the heat treatment step performed later. In addition, release of moisture and gas from the insulating film due to changes over time can be prevented. This can enhance the reliability of the semiconductor device.

(Embodiment mode 4)

In this embodiment mode, referring to FIGS. 4A and 4B and FIGS. 5A and 5B , a case where a barrier layer is formed using a spot drip method is described.

4A and 4B show the case where the barrier layer is formed in the opening formed in the insulating film, and FIGS. 5A and 5B show the case where the barrier layer is formed on the insulating film and on the surface of the conductive film.

First, as shown in the above-mentioned embodiment modes, an insulating film 451 is formed on a substrate 450 by a droplet method, and openings 453 and 454 are provided in the insulating film by etching (FIG. 4A). Here, the openings 453 and 454 may be formed to have a wedge shape as shown in FIGS. 2A to 2D .

A barrier layer 460 is formed by selectively dripping a composition to the openings 453 and 454 and edge portions of the insulating film (FIG. 4B). By forming the barrier layer 460 , it is attempted to protect and stabilize the surfaces of the insulating film 451 and the edge portions of the insulating film 451 in the openings 453 and 454 . In other words, the barrier layer serves to protect the interior from contamination by corrosive gases, water vapor, metal ions, and the like. Furthermore, it is possible to prevent the leads covering the openings 453 and 454 to be formed later from being disconnected due to the step of forming the barrier layer of the conductive film.

5A and 5B show the case where a barrier layer is formed on the conductive film 505 after the conductive film 505 is formed in the opening.

First, openings are formed in the insulating film as described in the above embodiment mode. Then, conductive films 505 and 506 are formed by filling a conductive material by dropping a composition into the openings. Then, a barrier layer 520 is formed on the edge portions of the conductive films 505 and 506 and the insulating film 501 by the spotting method.

As a composition included in the barrier layer, a composition having a property of preventing entry of water vapor or oxygen, and having a viscosity of 50 cp or less so as to be able to form the barrier layer 520 using a spot instillation method is preferable. As a composition having these characteristics, known conductive materials, or resin materials such as epoxy resins, acrylic resins, phenolic resins, novolac resins, melamine resins, or polyurethane resins are preferable as examples. When these resin materials are used, their viscosity can be adjusted by dissolving or dispersing these resin materials using a solvent. In addition, a hydrophobic resin is preferable as the barrier layer, for example, a resin containing fluorine atoms or composed of only hydrocarbons is preferable. In more detail, a resin including a monomer containing fluorine atoms in the molecule, or a resin including a monomer configured only with carbon atoms or hydrogen atoms can be exemplified.

Furthermore, when the barrier layer is formed of a conductive material, the barrier layer must be formed without causing a short circuit with the lead. Therefore, it is preferable to form a barrier layer of a resin material in a region where a short circuit with a lead wire may occur.

When forming the barrier layer, there is a possibility that a step is generated depending on the angle of the side of the opening to cause disconnection. Therefore, the sides of the opening must be formed to have gentle sloped surfaces. Specifically, the sides may be formed into a wedge shape greater than 30° to less than 75°. In addition, in order to prevent disconnection due to steps, the treatment of baking the composition may be performed after one or more drops are dripped, and the treatment of curing the composition may be performed. In other words, dripping and baking can be repeated.

In FIGS. 4A and 4B and FIGS. 5A and 5B , as shown in Embodiment Mode 3, it is preferable to modify the surface of the insulating film by adding an impurity element before forming the barrier layer.

As described above, an insulating film to which impurities are added, or an insulating film on which a barrier layer is laminated can be used as an interlayer insulating film, or an insulating film including an opening. Thus, it is possible to prevent deterioration of elements due to, for example, ingress of moisture or oxygen. Note that this embodiment mode can be freely combined with other embodiment modes.

(Embodiment mode 5)

6A to 6C are used to explain Embodiment Mode 5. FIG. 6A to 6C show a state where a planarization process is performed on an insulating film formed by dropping a composition.

Generally, when a film is formed on a substrate by sputtering or CVD, the surface condition of the film depends on the surface condition of the substrate before the film is formed. Therefore, if steps are present on the substrate before the film is formed, steps will also be formed on the surface after the film is formed.

On the other hand, in the drip infusion method, the value of the infusion rate can be controlled during instillation of the composition. Therefore, if the drip rate is predetermined according to the dot, even when there is a step before the film is formed, the step can be modified. However, it is conceivable that unevenness may be generated on the surface due to the kind, viscosity, or one-time drip rate of the solvent. When unevenness increases on the surface, in the case of laminated leads, depending on the poor step coverage of the stepped portion, opening defects due to disconnection of lead layers, or due to poor insulation between lead layers may occur short circuit defect. In addition, in the photolithography step, since the film thickness of the photoresist fluctuates at the step portion and the focal length of the lens is locally inaccurate during exposure, it becomes difficult to produce fine patterns. Therefore, when the unevenness of the dripped composition cannot be ignored, it is preferable to perform a planarization treatment after forming the insulating film by the drop casting method. The planarization process will be specifically described using FIGS. 6A to 6C.

First, the insulating film 601 is formed by dropping an insulator on the substrate 600 (FIG. 6A). Then, planarization treatment is performed on the insulating film 601 . As the planarization treatment, reflow planarization, CMP planarization, bias sputtering planarization, etch back planarization, or a combination thereof may be performed. Note that planarization with CMP is shown here.

In CMP, between a wafer 605 mounted on a head (carrier) 602 for support, a mask cloth (pad) 603 mounted on a mask mold plate 606, and a polishing liquid (slurry) supplied thereto During this period, mechanical polishing and polishing of the substrate surface in which the chemical action is balanced are carried out (FIG. 6B). It allows unevenness on the surface of the insulating film to be flattened (FIG. 6C).

As described above, planarization of the surface of the insulating film can be achieved by performing planarization treatment such as CMP after the insulating film is formed by dropping the composition.

As shown in this embodiment mode, the unevenness on the surface is flattened by performing flattening treatment on the insulating film formed by the droplet method. Therefore, it is extremely effective in laminating and forming leads in multiple layers. In addition, by performing planarization, it is possible to prevent disconnection due to steps, short circuits of electrodes, etc., and to improve yield.

Note that this embodiment mode can be freely combined with the above-mentioned embodiment modes.

Example 1

A method of manufacturing a semiconductor device in which the present invention is applicable to manufacturing an insulating film will be described using the drawings.

In Embodiment 1, a method of manufacturing a thin film transistor using an amorphous semiconductor (amorphous silicon, a-Si) was described. First, a method of manufacturing an upper gate type (forward stacked type) thin film transistor using an amorphous semiconductor (amorphous silicon, a-Si) will be described using FIGS. 7A to 7D and FIGS. 8A to 8C.

First, conductive films 801 and 802 are formed on a substrate 800 by discharging a composition. Then, an n-type amorphous semiconductor 803 and an amorphous semiconductor 804 are formed to cover the conductive films 801 and 802, and an insulating film 805 is laminated thereon. Therefore, the insulating film 805 can be formed by plasma CVD or sputtering, and here it is manufactured by the spotting method. In addition, at this time, the drip rate can be controlled to form recesses on the insulating film 805 (FIG. 7A).

Then, a gate electrode 806 is formed on the insulating film 805 by a spotting method. At this time, a recess is formed on the insulating film 805, and therefore, by utilizing the recess as a bank, the composition can be applied more accurately. Therefore, the conductive material can be precisely formed at an arbitrary point.

Then, a mask 807 is formed with an insulator such as photoresist or polyimide by dropping a composition (FIG. 7B). Then, by simultaneously patterning the n-type amorphous semiconductor 803, the amorphous semiconductor 804, and the insulating film 805, the n-type amorphous semiconductor 808, the amorphous semiconductor 809, and the insulating film 810 are formed.

Then, an insulating film 811 is formed by discharging a composition, and a mask 812 made of an insulator such as polyimide is further formed on 811 by discharging a composition different from that used for the insulating film 811 (FIG. 7C). Here, including siloxane system materials, containing 1×10 ²⁰ /cm ³ Si-CH ₃ bond or Si-C bond, or containing 1×10 ²⁰ /cm ³ or more C, and in 100 square micrometers A composition without cracks of 3 μm or more was used as the insulating film 811 .

Portions not covered with the mask are etched to form openings 813 and 814, and mask 812 is removed (FIG. 7D). Here, wet etching using an etchant such as sulfuric acid, nitric acid, phosphoric acid, hydrofluoric acid, or generally dry etching using RIE (Reactive Ion Etching) may be used for the etching process, according to It can be appropriately selected for the purpose of use. Depending on the object to be processed, the etching gas can be appropriately selected, and a fluorine-based gas such as CF ₄ , NF ₃ or SF ₆ or a chlorine-based gas such as Cl ₂ or BCl ₃ can be used for etching.

Then, by adding impurity elements to the surface of the insulating film 811 (reference numbers 851 to 853 in FIG. 8A ), surface modification can be performed. As a method of adding impurity elements, methods such as ion doping, ion implantation, and ion treatment can be exemplified, and materials selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon can be used. One or more selected from (Xe) as impurity elements to be added.

The conductive films 815 and 816 may be formed by dropping a composition including a conductive material to fill the openings 813 and 814 . A conductive film 817 is formed by dripping a composition including a conductive material and is in contact with the conductive film 816 (FIG. 8B). Here, the conductive film 817 functions as a pixel electrode.

Then, an alignment film 821 is formed. The sealant is cured by heating, and the substrate 825 on which the color filter film 822 , the counter electrode 823 and the alignment film 824 are formed is connected to the substrate 800 . Thereafter, by injecting liquid crystal 826, a semiconductor device using liquid crystal and having a display function is completed. Polarizing plates 827 and 828 are attached to substrates 800 and 825 (FIG. 8C).

Subsequently, a method of manufacturing a semiconductor device in which a channel protection type thin film transistor using an amorphous semiconductor is formed and the present invention is applicable to manufacturing a lead connected to the thin film transistor is described using FIGS. 9A to 9E.

First, the gate electrode 901 is formed by dropping a composition on the substrate 900 . The gate electrode 901 may be formed on the substrate 900 by selectively dripping a composition including a conductive material. Here, as the substrate 900, a substrate made of an insulator such as glass, quartz, plastic, or aluminum, and one in which an insulating film such as silicon oxide or silicon nitride is formed on a metal substrate such as stainless steel, a semiconductor substrate, or the like can be applied. substrate. In addition, it is desirable to form an insulating film such as silicon oxide, silicon nitride, or silicon oxynitride on the surface of a substrate such as plastic or aluminum in order to prevent impurities and the like from being scattered from the substrate side.

Then, an insulating film 902 is formed on the gate electrode 901 . Although the insulating film 902 can be formed by a thin film forming method such as plasma CVD or sputtering, in this embodiment, it is formed by a spotting method. As the formation by the spotting method, compared with the case of forming the insulating film by CVD or sputtering, it is possible to form an insulating film with better planarity without generating a large number of steps.

Then, an amorphous semiconductor is formed on the insulating film 902 and an insulating film is formed on the entire surface thereof to cover the amorphous semiconductor. Then, by patterning only this insulating film using a mask, an insulating film 904 serving as an etching stopper is formed. Then, an n-type amorphous semiconductor is formed over the entire surface to cover the insulating film 904 . Thereafter, the amorphous semiconductor film 905 and the n-type semiconductor films 906 and 907 are formed by simultaneously patterning the amorphous semiconductor and the n-type amorphous semiconductor using a mask. Then, conductive films 908 and 909 connected to n-type semiconductors 906 and 907 are formed (FIG. 9A).

Subsequently, an insulating film 910 is formed by dropping a composition to form a mask 911 made of an insulator such as polyimide at an arbitrary point on the insulating film 910 (FIG. 9B). Although an insulating film is used here as the mask 911, the mask may be made of a conductive material as long as it can obtain a selectable etching ratio with respect to the insulating film 910. Thereafter, an opening 912 is formed so that a portion of the conductive film 909 is exposed by etching a portion not covered by the mask.

Then, a conductive film 913 is formed by dropping a composition including a conductive material to fill the opening 912 (FIG. 9D). Then, conductive films 914 and 915 are formed by dropping a composition including a conductive material so as to be in contact with the conductive film 913 . The conductive films 914 and 915 are made of a conductive material having light-transmitting properties. Specifically, the conductive film is composed of indium tin oxide (ITO) and ITSO including ITO and silicon oxide. Then, an electroluminescent layer 916 and a conductive film 917 are formed so as to be in contact with the conductive film 915 . The conductive film 917 functions as a cathode, and the conductive film 915 functions as an anode. Subsequently, a mask 920 is formed to cover the entire surface. Through the above steps, a so-called bottom-emitting semiconductor device in which light is emitted from the light-emitting element to the substrate 900 side is completed (FIG. 9E). In addition, this structure corresponds to the case where the transistor having the amorphous semiconductor as the channel portion is an n-type transistor.

An organic material such as acrylic or polyimide, or an inorganic material such as silicon oxide, silicon oxide nitride, or a siloxane system can be used as the insulating layer 918 that functions as a bank, and a photosensitive material or a non-photosensitive material can also be used . Preferably, the insulating layer 918 may be formed in a shape with continuously different curvature radii, so that the electroluminescent layer 916 formed later will not be disconnected due to steps. There are three types of light emission according to the light emitting element: upper emission in which light is emitted to the substrate side, lower emission in which light is emitted to its opposite side, and by forming a pair of electrodes made of a transparent material or by forming an electrode capable of transmitting light in the thickness direction , Light emission to the substrate side and dual emission to its opposite side. In addition, any single-layer type, laminated type, or mixed type without an interface of layers can be used as the electroluminescence layer 916 . In addition, any singlet material, triplet material, or a combination of these materials can be used as the electroluminescent layer 916 . In addition, any organic material including low-molecular materials, high-molecular materials, and middle-molecular materials, inorganic materials typified by molybdenum oxide having better electron injection characteristics, or composite materials of organic materials and inorganic materials can be used. Structure The electroluminescent layer 916 can be formed by a known method such as injection vapor deposition, or it can be formed by a spot-drop method in consideration of time or manufacturing cost. Therefore, in the present invention in which an insulating layer or a thin film is manufactured by a droplet method, it is possible to further reduce the time spent and the manufacturing cost.

Accordingly, semiconductor devices include image display devices, light emitting devices, light sources such as light emitting systems. In addition, the semiconductor device includes a screen that surrounds the pixel portion and a driver circuit between the substrate and the cover material, a module in which the FPC is connected to the screen, a module with a driver IC at the point of the FPC, and a module on the screen with COG technology, etc. Modules for mounting driver ICs, monitors for monitoring, etc.

In addition, among the above-mentioned transistors, a transistor in which an amorphous semiconductor is used as a channel portion is shown. However, the present invention is not limited thereto, and a semi-amorphous semiconductor (hereinafter referred to as SAS) in which crystal grains are dispersed in an amorphous semiconductor may be used. A transistor using SAS has a mobility from 2 cm ² /V.sec to 10 cm ² /V.sec, which is 2 to 20 times the field effect mobility of a transistor using an amorphous semiconductor. A transistor using SAS has an intermediate structure of an amorphous structure and a crystal structure (including single crystal and polycrystal). A semiconductor is a semiconductor having a stable third state which is stable due to free energy and a crystalline material with short-range order and lattice deformation. A semiconductor can be dispersed in a non-single-crystal semiconductor by making its grain diameter from 0.5 nm to 20 nm. In addition, the semiconductor includes at least 1 atomic % or more of hydrogen or halogen in order to terminate unbonded bonds (dangling bonds). In addition, better SAS can be obtained by adding noble gas elements such as helium, argon, krypton, or neon to enhance stability to further promote lattice deformation. A description of such an SAS is disclosed, for example, in Patent Publication 3,065,528. This embodiment can freely combine the above-mentioned embodiment manners.

Example 2

A semiconductor to which the method of manufacturing an insulating layer of the present invention is applied will be described by using the drawings.

First, as shown in FIG. 11A , a base insulating film 401 including an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxide nitride film is formed on a substrate 400 . As a material of the substrate 400, a glass substrate, a quartz substrate, a semiconductor substrate, a metal substrate, a stainless steel substrate, or a plastic substrate may be used. The base insulating film 401 may have a single-layer structure of an insulating film or a structure in which two or more insulating films are laminated. Then, an amorphous semiconductor film is formed on the base insulating film. The amorphous semiconductor film can be formed by using a known method (sputtering, LPCVD, plasma CVD, etc.). Then, the amorphous semiconductor film is crystallized by a known crystallization method such as a structural crystallization method, a thermal crystallization method using RTA or an annealing furnace, a thermal crystallization method using a crystallization-promoting metal element, or the like. The semiconductor film 404 is formed by patterning the crystalline semiconductor film obtained in this way to have a desired shape.

A gate insulating film 402 covering the semiconductor film 404 is formed. An insulating film such as a silicon oxide film is formed as the gate insulating film 402 by plasma CVD or sputtering. The gate insulating film 402 can also be formed by a drop drop method. When it is formed by the drip infusion method, the steps can be changed by controlling the infusion rate.

The gate electrode 403 is formed on the gate insulating film 402 by selectively dripping a composition including a conductive material. In this case, the diameter of the nozzle for the drip infusion method is set at from 0.1 μm to 50 μm (preferably from 0.6 μm to 26 μm), and the instillation rate of the composition dripped from the nozzle is set at From 0.00001 pl to 50 pl (preferably from 0.0001 pl to 10 pl). The drip rate increases proportionally to the size of the nozzle diameter. The distance between the object to be treated and the nozzle outlet is as close as possible to drop the composition at the desired point, preferably from about 0.1 nm to 2 nm.

Then, by doping impurities into the semiconductor 404 using the gate electrode 403 as a mask, a source region 405 and a drain region 406 are formed.

Then, by using a spot dropping method, an insulating film 410 is formed. The insulating film 410 is made of a material including silicon such as a silicon oxide nitride film, an organic material such as acrylic or polyimide having a light-transmitting characteristic, a compound material formed by polymerization of a polymer including siloxane, or the like. constitute. The insulating film 410 is formed of a single layer or two or more layers using these materials. A polymer including siloxane is taken as a typical example of a material in which a skeleton structure is constituted with a bond of silicon and oxygen, and at least hydrogen is contained as a substituent, or has at least one of fluorine, an alkyl group, or an aromatic hydrocarbon materials as substituents. Therefore, various materials within the range of the above conditions can be used. Organic materials and materials in which the skeleton structure is formed by bonds of silicon and oxygen have better planarity. Therefore, these materials are preferable because the film thickness is not extremely thin at the stepped portion, or disconnection is not generated even when the conductive material is formed later. In addition, a material whose skeleton structure is composed of bonds of silicon and oxygen also has transparency and thermal stability, and therefore, heat treatment from about 300° C. can be performed after film formation. By heat treatment, for example, hydrogenation and baking treatment can be performed at the same time.

Then, a photoresist 409 which can optionally become a mask is formed on the insulating film 410 (FIG. 11A). As the photoresist 409, a photoresist capable of obtaining a selectable ratio with respect to the insulating film 410 can be used.

Then, openings 411 and 412 in contact with the lower layer side are formed by etching portions not covered by the mask.

In this embodiment, the case when the structure etches the insulating film 410 and the gate insulating film 402 by two-step etching is shown as an example, and the embodiment is not limited thereto. Here, the case where a polymer including siloxane is used for the insulating film 410 and a film containing a large amount of oxygen is used for the gate insulating film 402 is shown.

In this embodiment, the gate insulating film 410 is etched (wet etching or dry etching) under the condition that a selectable ratio can be obtained with respect to the gate insulating film 402 . An inert gas is added to the etching gas to be used in etching the gate insulating film 410 . As the inert element to be added, one or more selected from He, Ne, Ar, Kr, and Xe can be used. In the present invention, with 26% or more and 50% or less of the total flow rate, one or more of Ar, Kr and Xe with a larger atomic radius among the inert elements are added to the etching process. gas. First, argon is preferably used because it has a relatively large atomic radius and is inexpensive. In this example, CF ₄ , O ₂ , He and Ar were used. When performing dry etching, the etching conditions are: the flow rate of CF ₄ is set at 380 sccm; O ₂ , 290 sccm; He, 500 sccm; Ar, 500 sccm; RF power, 3000W; and pressure, 25Pa. As the chamber of the etching apparatus of this embodiment, an apparatus having a volume of about 0.335 m ³ can be used. According to the above conditions, etching residues can be reduced.

In order to perform etching without leaving any residue on the insulating film 410, the etching time may be increased by a ratio of approximately from 10% to 20%. The wedge shape can be formed by performing one or more etchings. Here, to form a wedge shape, by using CF ₄ , O ₂ and He, the flow rate of CF ₄ was set at 550 sccm; the flow rate of O ₂ at 450 sccm; the flow rate of He at 450 sccm; the RF power at 3000 W; and the pressure at 25 Pa, Dry etching may be further performed.

By etching the gate insulating film 402, openings reaching the source region and the drain region are formed. A mask to be used for etching may be re-formed, or a previously formed photoresist mask may be used. In this embodiment, openings 411 and 412 reaching the impurity regions are formed by etching the gate insulating film 402 using the photoresist 409 and the insulating film 410 as masks. CHF ₃ , Ar, He, etc. can be used as the etching gas. In this embodiment, an inert gas is added to the etching gas to be used. As elements to be added, one or more selected from He, Ne, Ar, Kr, and Xe can be used. In this embodiment, as an inert gas, one or more selected from Ar, Kr, and Xe having a large atomic radius is added so that the total flow rate is 60% or more and 85% or less , preferably 65% or more and 85% or less of the total flow. First, argon is preferably used because of its relatively large atomic radius and its low cost. In this embodiment, the etching process of the insulating film 412 is performed with an inert gas in which CHF ₃ and Ar are used. Preferably, the over-etching is performed by increasing the etching time by about 10% to 20% so that the etching can be performed without leaving a residue on the semiconductor layer.

Then, the photoresist 409 is removed. Since the photoresist 409 is an organic substance, the photoresist 409 is effectively removed by oxidation (in other words, the organic substance is converted into _CO2 and _H2O ). Evaporation can be done by decomposing and converting O ₃ (ozone) into oxygen radicals as a reactive gas to react with the photoresist using a plasma asher that is removed and evaporated by the reaction of the insulating film with the plasma gas Insulating film ozone asher, etc. As an asher, an asher having a high oxidation rate and low damage is preferably used. In addition, a wet method for removing photoresist may be used. A wet station or the like on which a chemical tank dissolving an insulating film is installed may be used. Impurities such as heavy metals contained in the actual insulating film are also removed when a plasma asher or an ozone asher is used. Therefore, it is preferable to use a wet workstation for cleaning.

Next, a doping treatment of an inert element is performed to form a highly dense portion 408 on the surface of the insulating film (FIG. 11B). Doping treatment may be performed by ion doping or ion implantation. Usually, argon (Ar) is used as an inert element. Deformation occurs by adding inert elements with relatively large atomic radii to improve the surface (including the sides) or make it denser to prevent the ingress of water vapor or oxygen, for example. The concentration of the inert elements contained in the highly dense part ranges from 1×10 ¹⁹ /cm ³ to 5×10 ²¹ /cm ³ , usually from 2×10 ¹⁹ /cm ³ to 2×10 ²¹ /cm ³ . In addition, the openings are formed in a wedge shape so that an inert element is doped to the surfaces (including side surfaces) of the openings 411 and 412 . It is desirable to set the wedge angle θ larger than 30° and smaller than 75°.

Then, the openings 411 and 412 are filled with a conductive material by dropping a composition to form conductive films 413 and 414 . Subsequently, by using a spot drip method, a conductive film 415 functioning as a first electrode (pixel electrode) is formed (FIG. 11C). When the anode is formed as the first electrode, it is preferable to use a material with a relatively high work function.

Then, an insulator (also referred to as a bank, a partition wall, a barrier, etc.) 416 is formed to cover the end of the first electrode, and an electroluminescent layer is formed to be in contact with the conductive film 415 . Then, a conductive film 418 is laminated so as to be in contact with the electroluminescence layer. Thus, the light emitting element including the conductive film 415, the electroluminescence layer 417, and the conductive film 418 is completed. Finally, an insulating layer 419 functioning as a protective film is formed on the entire surface.

Subsequently, the sealant 421 is formed by a screen printing method or a dispenser method, and the substrate 420 is connected to the substrate 400 with the sealant. Through the above steps, the semiconductor device including the light emitting element shown in Fig. 11D is completed.

An analog video signal or a digital video signal can be used for the above-mentioned semiconductor device including the light-emitting element. However, when digital video signals are used, different drive systems are available depending on the voltage or current used by the video signal. In other words, when emitting light from a light emitting element, in terms of a video signal input to a pixel, there are two driving systems, a system with a constant voltage and a system with a constant current. Furthermore, there are two systems using a video signal with a constant voltage: a drive system in which the voltage applied to the light emitting element is constant, and a drive system in which the current applied to the light emitting element is constant. In addition, there are two systems using a video signal with a constant current: a drive system in which the voltage applied to the light emitting element is constant, and a drive system in which the current applied to the light emitting element is constant. A driving system in which the voltage applied to the light emitting element is constant is constant voltage driving, and a driving system in which the current applied to the light emitting element is constant is constant current driving. In constant current driving, a constant current flows regardless of changes in the resistance of the light emitting element. Either a driving system using a voltage video signal or a driving system using a current video signal can be used for the semiconductor device accomplished by the present invention, and constant voltage driving or constant current driving can also be used. This embodiment can be freely combined with the above-mentioned embodiment modes and embodiments.

Embodiment mode 3

In this embodiment, an example in which the end portion is covered with a metal layer is shown in FIGS. 12A and 12B. Since parts other than the surroundings are the same as FIG. 11D shown in Embodiment 2, detailed descriptions are omitted here. Note that in FIGS. 12A and 12B , the same parts are denoted by the same symbols as in FIGS. 11A to 11D .

In this embodiment, as shown in FIGS. 12A and 12B, a barrier layer 430 is formed on the end of the intermediate insulating layer 410 by dropping a composition. Here, a composition having a property of preventing ingress of water vapor or oxygen, and having a viscosity of 50 cp or less to enable the formation of the barrier layer 430 by a drip method may be used. As a composition having these characteristics, for example, known conductive materials may be used, or resins such as epoxy resins, acrylic resins, phenol resins, novolac resins, melamine resins, or polyurethane resins may be used. When using these materials, the viscosity can be adjusted by dissolving or dispersing the resin material using a solvent. In addition, a lyophobic resin is preferable, for example, a resin including fluorine atoms or a resin formulated only with hydrocarbons can be given. In more detail, a resin including a monomer containing fluorine atoms in the molecule, or a resin including a monomer configured only with carbon atoms or hydrogen atoms can be exemplified.

When the barrier layer 430 is formed of a conductive material, the barrier layer must be formed so as not to be short-circuited with the wiring. Therefore, it is preferable to form the barrier layer 430 with a resin material in a region where a short circuit with the lead wire may occur. An enlarged cross-sectional view of the surrounding is shown in FIG. 12B . In the insulating film 410 , the end portion having a step is covered with a barrier layer 430 . Here, there is a possibility that a step is generated depending on the angle of the end portion when forming the barrier layer 430 to cause disconnection. Therefore, it is necessary to form the end portion to have a gentle inclined surface. Specifically, the sides can be formed into a wedge shape from 30° to 75°. In addition, in order to prevent disconnection due to steps, the treatment of baking the composition may be performed after one or more drops are dripped, and the treatment of curing the composition may be performed.

As described above, by forming the barrier layer on the insulating film, water vapor, oxygen, etc. can be prevented from entering the insulating film in direct contact with the light-emitting element, so that deterioration of the light-emitting element can be prevented. Therefore, dark spots or shrinkage are not generated, which makes it possible to provide a semiconductor device in which product reliability is improved. Note that this embodiment can be freely combined with the embodiment mode and other embodiments.

Embodiment mode 4

In this embodiment, in the manufacturing steps of an upper gate type thin film transistor using a polycrystalline semiconductor (polysilicon, P-Si), a method for manufacturing a semiconductor device in which Among them, the present invention is applied to a method of manufacturing an insulating layer interposed between conductive materials that are in contact with impurity regions included in a thin film transistor.

First, a semiconductor is formed on a substrate 150, and after an insulating film 151 is formed on the semiconductor, conductive films 164 to 166 are formed on the insulating film 151 by a spot-drop method. In addition, by forming an insulating film as a base film on the substrate 150 if necessary, impurities can be prevented from entering the substrate 150 . Then, by using the conductive films 164 to 166 as masks, impurities are added to the semiconductor to form impurity regions 155 to 160 in which impurities are added, and channel formation regions 152 to 154 (FIG. 10A).

Then, after the insulating film 177 is formed by the drip method, a mask formed of an insulating film different from the insulating film 177 is further formed to make openings 171 to 177 by etching a part of the insulating film 177 not covered by the mask. 176 (Fig. 10B). Then, conductive films 181 to 186 are formed to fill the openings 171 to 176 by selectively dripping a composition including a conductive material. Through the above steps, a semiconductor device as shown in FIG. 10C can be manufactured. Note that the insulating film 177 and the conductive films 181 to 186 can be manufactured by using the materials shown in the above-described embodiment modes and embodiments.

By repeating the above-mentioned steps, the layers from the second layer to the fifth layer are stacked, and a semiconductor device having multilayer leads as shown in FIG. 10D is completed.

A semiconductor device having a multilayer lead structure in which leads are stacked as shown in FIG. 10D is very effective when many functional circuits such as CPU (Central Processing Unit), image processing circuit, memory need to be incorporated. In addition, by applying a multilayer wiring structure, there is no need to lead wiring in the same layer as a gate electrode, a source wiring, or a drain wiring of a semiconductor element formed in the first layer, thereby contributing to miniaturization and reduction of semiconductor devices. Extremely effective in terms of weight.

In addition, the more layers are stacked, the more the manufacturing process is simplified, and therefore, low-cost manufacturing becomes possible by forming the lead layer by the drip method compared with the conventional manufacturing method.

Note that this embodiment can be freely combined with the above-described embodiment modes and embodiments.

Example 5

FIG. 13 is used to describe the case of modularizing the liquid crystal display panel or the EL display panel in the first embodiment and the second embodiment.

The screen shown in Embodiment 1 or Embodiment 2 ( FIGS. 8A to 8C , FIGS. 9A to 9E or FIGS. 11A to 11D ) is equipped with circuit systems such as driving LSIs, controllers for driving and controlling liquid crystals and ELs, and Brightness driving voltage generating circuit. In the circuit, a signal processing system and a control system are placed on a printed circuit board (PCB), and a driver IC group is mounted on the periphery of the pixel portion. As a mounting method, a TAB (Tape Automated Bonding) method of mounting a TCP (Chip Tape Carrier) type driver, or a COG (Chip on Glass) method of directly mounting the bare chip of the driver IC on the screen can be used.

Fig. 13 shows the situation of installation by the TAB method. As shown in Embodiment 1 or Embodiment 2, the pixel portion 131 may be a pixel portion in which a liquid crystal portion is used as a display medium, or a pixel portion in which an EL element is used as a display medium. As the driver ICs 132a, 132b to 132n, 133a, 133b, 133c to 133m, and 133n, in addition to forming integrated circuits by using single crystal semiconductors, similar types in TFTs in which polycrystalline semiconductors are used can also be used. Furthermore, in the circuit, a signal processing system and a control system may be provided on the printed circuit board 135 .

The above-mentioned screen can be mounted by the COG method, the driver IC is directly mounted on the screen, and the connection terminals from the outside can be reduced. In this case, a peripheral driver circuit is formed on a substrate to be integrated, and as an element configuring these, a transistor having a P-Si type semiconductor as a channel portion can be used. This is effective when the pixel portion and the driver circuit portion are integrated using a P-Si type semiconductor.

In addition, a semi-amorphous semiconductor (hereinafter referred to as SAS) can be used as the transistor of the channel portion. A transistor in which SAS functions as a channel portion has higher mobility than a transistor in which an amorphous semiconductor (a-Si) functions as a channel portion. And have enough characteristics to configure the driving circuit.

Note that this embodiment can be freely combined with the above-described embodiment modes and embodiments.

Example 6

By using the modules described in FIG. 5, various electronic devices can be completed. A specific embodiment thereof is described with reference to FIGS. 14A to 14C.

FIG. 14A shows a display device including a housing 2001, a support stand 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. In this display device, a display module 2006 using the liquid crystal or EL element shown in Embodiment 5 is included in a housing 2001 . In addition, the display device is manufactured by applying the manufacturing method shown in the embodiment to the display portion 2003 . By using the manufacturing method of the present invention, the present invention can be applied to electronic equipment having a large size without using a large device due to the simplification of the manufacturing process. Therefore, a display device having a large size can be manufactured at low cost. The light emitting device and the like shown in Embodiment 1 or Embodiment 2 are included in this display device. Specifically, a display device for displaying information, such as a display device for a personal computer, TV broadcast receiving station, advertisement display, may be included in the display device.

FIG. 14B shows a computer including a housing 2201, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be applied to manufacture the display portion 2203 . The present invention is also applicable to semiconductor devices such as a CPU and a memory in a main body. By forming the multi-layer structure shown in Embodiment 4 (FIGS. 10A to 10D), the computer can be miniaturized and made light.

FIG. 14C shows a mobile phone in a portable terminal, which includes a casing 2301, a display portion 2302, and the like. Electronic devices such as the above-mentioned mobile phones and other PDAs and digital cameras are portable terminals. Therefore, they have a small image display. Thus, by using a polycrystalline semiconductor as a channel, a multilayer lead shown in Embodiment 4, or a functional circuit such as a CPU on the same substrate as a display portion shown in FIG. It is better to try to minimize and reduce the weight of the mobile phone.

As described above, the semiconductor device manufactured according to the present invention has a wide range of applications and can be applied to electronic equipment in all fields. Note that the electronic device in Embodiment 6 can be completed by implementing Embodiment Modes 1 to 5 and Embodiments 1 to 5.

Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be understood that various modifications and alterations will be apparent to those skilled in the art. Therefore, unless such modifications and changes depart from the scope of the present invention defined below, they should be construed as being included therein.

This application is based on Japanese Patent Application Serial No. 2003-367051 filed with Japan Patent Office on October 28, 2003, the contents of which are incorporated herein by reference.

Claims (100)

1. method that is used for producing the semiconductor devices, this method may further comprise the steps:

Comprise that by instillation the synthetic of insulator forms first dielectric film;

On described first dielectric film, form second dielectric film;

Form mask pattern by on described second dielectric film, exposing and developing; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

2. method of making semiconductor device, this method may further comprise the steps:

Comprise that by instillation the synthetic of insulator forms first dielectric film;

By the synthetic that on described first dielectric film, optionally instils, form second dielectric film; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

3. method that is used for producing the semiconductor devices, this method may further comprise the steps:

Form first dielectric film by instillation synthetic on thin-film transistor, described synthetic comprises insulator;

On described first dielectric film, form second dielectric film;

Form mask pattern by on described second dielectric film, exposing and developing; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

By using described second dielectric film as mask, by described first dielectric film of etching, form at least one opening, wherein said opening arrives in the source electrode of described thin-film transistor and the drain region;

Form conductive layer on described first dielectric film, wherein said conductive layer is connected by one in described opening and source electrode and the drain region.

4. method that is used for producing the semiconductor devices, this method may further comprise the steps:

Form first dielectric film by instillation synthetic on thin-film transistor, described synthetic comprises insulator;

On described first dielectric film, form second dielectric film;

Form mask pattern by on described second dielectric film, exposing and developing; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

By using described second dielectric film as mask, by described first dielectric film of etching, form at least one opening, wherein said opening arrives in the source electrode of described thin-film transistor and the drain electrode;

Form conductive layer on described first dielectric film, wherein said conductive layer is connected by one in described opening and source electrode and the drain electrode.

5. method that is used for producing the semiconductor devices, this method may further comprise the steps:

Form first dielectric film by instillation synthetic on thin-film transistor, described synthetic comprises insulator;

On described first dielectric film, form second dielectric film;

Form mask pattern by on described second dielectric film, exposing and developing; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

By using described second dielectric film as mask, by described first dielectric film of etching, form at least one opening, wherein said opening arrives in the source electrode of described thin-film transistor and the drain region;

Form conductive layer on described first dielectric film, wherein said conductive layer is connected by one in described opening and source electrode and the drain region.

Form the pixel electrode that is electrically connected with described conductive layer.

6. method that is used for producing the semiconductor devices, this method may further comprise the steps:

Form first dielectric film by instillation synthetic on thin-film transistor, described synthetic comprises insulator;

On described first dielectric film, form second dielectric film;

Form mask pattern by on described second dielectric film, exposing and developing; And

By using described second dielectric film, form opening by described first dielectric film of etching as mask.

By using described second dielectric film as mask, by described first dielectric film of etching, form at least one opening, wherein said opening arrives in the source electrode of described thin-film transistor and the drain electrode;

Form conductive layer on described first dielectric film, wherein said conductive layer is connected by one in described opening and source electrode and the drain electrode.

Form the pixel electrode that is electrically connected with described conductive layer.

7. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, forms described conductive layer by instiling.

8. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, forms described conductive layer by instiling.

9. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, forms described conductive layer by instiling.

10. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, forms described conductive layer by instiling.

11. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

12. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

13. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

14. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

15. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

16. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, the opening that forms in described first dielectric film has wedge shape, and inert element is added to described first dielectric film.

17. the method for manufacturing semiconductor device as claimed in claim 11 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

18. the method for manufacturing semiconductor device as claimed in claim 12 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

19. the method for manufacturing semiconductor device as claimed in claim 13 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

20. the method for manufacturing semiconductor device as claimed in claim 14 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

21. the method for manufacturing semiconductor device as claimed in claim 15 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

22. the method for manufacturing semiconductor device as claimed in claim 16 is characterized in that, described inert element is one or more that select from helium (He), neon (Ne), argon (Ar), krypton (Kr) and xenon (Xe).

23. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

24. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

25. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

26. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

27. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

28. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, to the side of opening, forms the barrier layer by the synthetic that optionally instils.

29. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

30. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

31. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

32. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

33. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

34. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, by the synthetic that instils on opening, forms conducting film, and by the synthetic that optionally instils on described conducting film, forms the barrier layer.

35. the method for manufacturing semiconductor device as claimed in claim 23 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

36. the method for manufacturing semiconductor device as claimed in claim 24 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

37. the method for manufacturing semiconductor device as claimed in claim 25 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

38. the method for manufacturing semiconductor device as claimed in claim 26 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

39. the method for manufacturing semiconductor device as claimed in claim 27 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

40. the method for manufacturing semiconductor device as claimed in claim 28 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

41. the method for manufacturing semiconductor device as claimed in claim 29 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

42. the method for manufacturing semiconductor device as claimed in claim 30 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

43. the method for manufacturing semiconductor device as claimed in claim 31 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

44. the method for manufacturing semiconductor device as claimed in claim 32 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

45. the method for manufacturing semiconductor device as claimed in claim 33 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

46. the method for manufacturing semiconductor device as claimed in claim 34 is characterized in that, described barrier layer comprises the resin that comprises the monomer that contains fluorine atom in the molecule or comprises the resin of the monomer that only comprises carbon atom or hydrogen atom.

47. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

48. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

49. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

50. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

51. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

52. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, described first dielectric film is made of one or more that select from polyimides, acrylic acid, benzocyclobutene and polyamide.

53. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

54. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

55. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

56. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

57. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

58. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, described first dielectric film comprises that the key of silicon and oxygen constitutes the material of skeleton structure therein.

59. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

60. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

61. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

62. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

63. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

64. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, first dielectric film is formed and makes inert gas be included in from 1 * 10 ¹⁹Atom/cm ³To 5 * 10 ²¹Atom/cm ³Concentration.

65. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

66. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

67. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

68. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

69. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

70. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, after the synthetic that comprises insulator by instillation forms described first dielectric film, carries out planarizing process.

71. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

72. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

73. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

74. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

75. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

76. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, by the synthetic that comprises electric conducting material being instilled into the opening of described first dielectric film, forms the conducting film of filling opening.

77. the method as the described manufacturing semiconductor device of claim 71 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

78. the method as the described manufacturing semiconductor device of claim 72 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

79. the method as the described manufacturing semiconductor device of claim 73 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

80. the method as the described manufacturing semiconductor device of claim 74 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

81. the method as the described manufacturing semiconductor device of claim 75 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

82. the method as the described manufacturing semiconductor device of claim 76 is characterized in that, described conducting film comprises the material that comprises silver, gold, copper or tin indium oxide.

83. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, forms the opening with wedge shape in described first dielectric film.

84. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, forms the opening with wedge shape in described first dielectric film.

85. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, forms the opening with wedge shape in described first dielectric film.

86. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, forms the opening with wedge shape in described first dielectric film.

87. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, forms the opening with wedge shape in described first dielectric film.

88. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, forms the opening with wedge shape in described first dielectric film.

89. the method for manufacturing semiconductor device as claimed in claim 1 is characterized in that, inert element is added described first dielectric film.

90. the method for manufacturing semiconductor device as claimed in claim 2 is characterized in that, inert element is added described first dielectric film.

91. the method for manufacturing semiconductor device as claimed in claim 3 is characterized in that, inert element is added described first dielectric film.

92. the method for manufacturing semiconductor device as claimed in claim 4 is characterized in that, inert element is added described first dielectric film.

93. the method for manufacturing semiconductor device as claimed in claim 5 is characterized in that, inert element is added described first dielectric film.

94. the method for manufacturing semiconductor device as claimed in claim 6 is characterized in that, inert element is added described first dielectric film.

95. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 1, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

96. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 2, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

97. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 3, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

98. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 4, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

99. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 5, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

100. make a kind of method that comprises the electronic equipment that merges semiconductor device as claimed in claim 6, wherein said semiconductor device comprises display unit, computer, mobile phone, PDA, camera etc.

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