JP2000323572A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid adverse influences of moisture and hydroxide groups in an SOG film by introducing an impurity in an insulation film to reform it and provide impurity-contg. regions where moisture and hydroxide groups in the film are lessened and the film hardly absorbs moisture. SOLUTION: On a single crystal Si substrate 1 a silicon oxide film 2 and an org. SOG film 3 are formed, and the SOG film 3 interior is buried. A metal wiring 7 is buried in trenches on the inner walls of which a reformed SOG film 5 is formed such that B ion is introduced in the SOG film 3, org. components in the film are decomposed, moisture and hydroxide groups in the film are lessened, no org. component is contained and moisture and hydroxide groups are contained a little. This prevents the metal wiring 7 from corrosion and a high-reliability layer insulation film with a possibly reduced inter- wiring capacitance can be obtained and it is adaptable to scale down since only the reformed SOG film 5 exists sideways between the metal wirings 7.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a technique for forming an insulating film on a device.

[0002]

2. Description of the Related Art In recent years, in order to further increase the degree of integration of semiconductor integrated circuits, it has been required to advance wiring miniaturization and multilayering. In order to multi-layer the wiring, an interlayer insulating film is provided between each wiring, but if the surface of the interlayer insulating film is not flat, a step is generated in the wiring formed on the upper part of the interlayer insulating film and a failure such as disconnection may occur. Is caused.

Therefore, the surface of the interlayer insulating film (that is, the surface of the device) must be as flat as possible. As described above, a technique for planarizing the surface of a device is called a planarization technique, and has become more and more important with miniaturization and multilayering of wiring.

[0004] In the planarization technique, there is an SOG (Spin On Glass) film as an interlayer insulating film that is frequently used. In particular, active study has been made on a planarization technique utilizing the flow characteristics of an interlayer insulating film material.

[0005] SOG is a general term for a solution in which a silicon compound is dissolved in an organic solvent and a film formed from the solution and containing silicon dioxide as a main component.

To form an SOG film, first, a solution in which a silicon compound is dissolved in an organic solvent is dropped on a substrate, and the substrate is rotated. Then, the film of the solution is formed thicker in the concave portion and thinner in the convex portion, so as to relieve the step on the substrate formed by the wiring.
As a result, the surface of the coating of the solution is planarized.

Next, when a heat treatment is performed, the organic solvent evaporates and the polymerization reaction proceeds to form an SOG film having a flat surface.

[0008] As shown in the general formula (1), the SOG film includes an inorganic SO containing no organic component in the silicon compound.
There are a G film and an organic SOG film containing an organic component in a silicon compound as represented by the general formula (2).

[SiO ₂ ] _n ··· (1) [R _X Si _Y O _Z ] _n ··· (2) (n, X, Y, Z: integer, R: alkyl group or aryl group) Inorganic SOG Films and organic SOG films have very good flatness, but inorganic SOG films contain a large amount of moisture and hydroxyl groups, which adversely affect metal wiring and the like, deteriorating electrical characteristics, corrosion, etc. Problem may occur.

Although the organic SOG film contains less moisture and hydroxyl groups than the inorganic SOG film, it has the same problem.

Therefore, usually, when an SOG film is used as an interlayer insulating film, it is formed by, for example, a plasma CVD method which has a property of relatively blocking moisture and hydroxyl groups and a property of high insulation and mechanical strength. An insulating film such as a silicon oxide film is interposed between the SOG film and the metal wiring (see, for example, Japanese Patent Application Laid-Open No. Hei 5-22).
No. 6334 (H01L21 / 3205).

[0012]

In the conventional example, S
When a metal wiring is buried in a contact hole or a trench formed in an OG film, the SOG film is still exposed on the inner wall surface of the contact hole or the trench.
The adverse effects of water and hydroxyl groups in the G film cannot be prevented.

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and an object thereof is to solve such a problem.

[0014]

According to a first aspect of the present invention, a semiconductor device includes a first wiring and a first impurity-containing region. The first wiring is substantially buried in the first insulating film up to its upper surface. The first impurity-containing region is formed only in a contact portion of the first insulating film with the first wiring.

In the first aspect, as described above, the first impurity-containing region is provided in the first insulating film, so that the first impurity-containing region is provided.
In the impurity-containing region, the introduction of the impurity modifies the film, thereby reducing the amount of water and hydroxyl groups contained in the film and making the film less likely to absorb water. Thereby, the moisture in the first insulating film does not adversely affect the first wiring. As a result, inconveniences such as corrosion of the first wiring can be effectively prevented. Further, by forming the first impurity-containing region only in the contact portion with the first wiring, even if the relative dielectric constant of this portion is slightly increased due to the introduction of the impurity, other regions in the first insulating film may be formed. The relative permittivity of the region does not increase. Therefore, in the semiconductor device according to the first aspect, an inconvenience such as corrosion of the first wiring can be effectively prevented, and an interlayer insulating film made of a highly reliable first insulating film having a low inter-wiring capacitance is obtained. be able to.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the semiconductor device further includes a second insulating film, a buried opening, and a second wiring. The second insulating film is formed on the first wiring and the first insulating film. The embedding opening is formed in the second insulating film and communicates with the first wiring. The second wiring is embedded in the embedding opening. Further, the second impurity-containing region is formed only in the contact portion between the second insulating film and the second wiring.

In the second aspect, as described above, the second impurity-containing region is provided in the second insulating film, so that the second impurity-containing region is provided.
In the impurity-containing region, the introduction of the impurity modifies the film, thereby reducing the amount of water and hydroxyl groups contained in the film and making the film less likely to absorb water. Thus, moisture in the second insulating film does not adversely affect the second wiring. As a result, inconveniences such as corrosion of the second wiring can be effectively prevented. Further, by forming the second impurity-containing region only in the contact portion with the second wiring, even if the relative dielectric constant of this portion is slightly increased due to the impurity introduction, other regions in the second insulating film are formed. Does not increase. Therefore, in the semiconductor device according to the second aspect, it is possible to effectively prevent inconvenience such as corrosion of the second wiring, and to obtain a highly reliable interlayer insulating film made of the second insulating film having the lowest possible wiring capacitance. be able to.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the embedding opening includes a contact hole communicating with the first wiring and a trench communicating with the contact hole.

According to a fourth aspect of the present invention, in the semiconductor device according to the third aspect, the second insulating film includes a third insulating film in which a contact hole is formed and a fourth insulating film in which a trench is formed.

According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, a mask for etching a contact hole is provided between the third insulating film and the fourth insulating film. Claim 5
By thus interposing the etching mask for the contact hole, the contact hole can be formed by etching continuously to the etching process for forming the trench, thereby simplifying the manufacturing process. be able to.

A semiconductor device according to a sixth aspect includes a first insulating film, a second insulating film, a first wiring, and a first impurity-containing region. The first insulating film is formed on the wiring layer and has a contact hole communicating with the wiring layer. Second
The insulating film is formed on the first insulating film and has a trench leading to the contact hole. The first wiring is formed so as to fill the contact hole and the trench and to make contact with the wiring layer. The first impurity-containing region is formed only in a contact portion of the first insulating film with the first wiring.

According to a sixth aspect of the present invention, as described above, the first impurity-containing region is provided in the first insulating film so that the first impurity-containing region is formed.
In the impurity-containing region, the introduction of the impurity modifies the film, thereby reducing the amount of water and hydroxyl groups contained in the film and making the film less likely to absorb water. Thereby, the moisture in the first insulating film does not adversely affect the first wiring. As a result, inconveniences such as corrosion of the first wiring can be effectively prevented. Further, by forming the first impurity-containing region only in the contact portion between the first insulating film and the first wiring, even if the relative dielectric constant of this portion is slightly increased by the introduction of the impurity, the first impurity-containing region is formed in the first insulating film. The relative permittivity of other regions in the insulating film does not increase. Therefore, in the semiconductor device according to claim 6,
It is possible to effectively prevent inconveniences such as corrosion of the first wiring, and to obtain a highly reliable interlayer insulating film made of the first insulating film, which has as low a capacitance between wirings as possible.

According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the second insulating film has a dielectric constant of 3.5 or less. As described above, when a low dielectric constant insulating film having a dielectric constant of 3.5 or less is used as the second insulating film, the inter-wiring capacitance of the interlayer insulating film formed of the second insulating film can be reduced. As a result, when the interlayer insulating film made of the first insulating film of claim 6 and the interlayer insulating film made of the second insulating film of claim 7 are used, the corrosion of the first wiring is reduced while the capacitance between the wirings is further reduced. Such inconveniences can be effectively prevented.

The semiconductor device according to claim 8 is the semiconductor device according to claim 6 or 7, further comprising a contact hole etching mask between the first insulating film and the second insulating film. As described above, by interposing the etching mask for the contact hole, the contact hole can be formed by etching successively to the etching process for forming the trench, and as a result, the manufacturing process can be simplified. it can.

According to the ninth aspect of the present invention, there is provided a semiconductor device comprising:
In any one of the structures 2, 6, and 7, the insulating film is
Includes a silicon oxide film containing 1 atomic% or more of carbon.

According to a tenth aspect of the present invention, in the semiconductor device according to any one of the first, second, sixth, and seventh aspects, the insulating film includes an inorganic SOG film.

[0027] In a method of manufacturing a semiconductor device according to claim 11, a step of forming a first insulating film on a substrate, and a step of forming a first impurity-containing region by introducing an impurity into a part of the first insulating film. Forming a first burying opening in the first impurity-containing region in the first insulating film; and burying a first wiring in the first burying opening.

According to a twelfth aspect of the invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a substrate; forming a first mask pattern on the first insulating film; Forming a first impurity-containing region larger than the opening of the first mask pattern in the first insulating film by implanting an impurity into the first insulating film using the first mask pattern as a mask. Forming a first burying opening having a first impurity-containing region on a side wall by etching the first impurity-containing region; and burying a first wiring in the first burying opening. Prepare.

In the twelfth aspect, as described above, the first impurity-containing region is formed in the first insulating film. In the first impurity-containing region, the film is modified by the introduction of the impurity, and the film is modified. The amount of water and hydroxyl groups contained in the film is reduced, and the film is less likely to absorb water. Thereby, the moisture in the first insulating film does not adversely affect the first wiring. As a result, inconveniences such as corrosion of the first wiring can be effectively prevented.
Further, by forming the first impurity-containing region only in the contact portion with the first wiring, even if the relative dielectric constant of this portion is slightly increased by the introduction of the impurity, other regions in the first insulating film are formed. Does not increase. Therefore, in the method for manufacturing a semiconductor device according to claim 12, the first
Inconveniences such as corrosion of the wiring can be effectively prevented, and an interlayer insulating film made of a highly reliable first insulating film having a low inter-wiring capacitance can be easily manufactured.

In the twelfth aspect, a first impurity-containing region is partially formed in the first insulating film in advance, and a first burying opening is formed in the first impurity-containing region.
The first impurity-containing region is formed as a side wall (inner wall) of the first embedding opening.
Only can be easily formed.

According to a thirteenth aspect of the present invention, in the semiconductor device manufacturing method according to the eleventh or twelfth aspect, a step of forming a second insulating film on the first wiring and the first insulating film; Forming a second buried opening that has a second impurity-containing region on the side wall and communicates with the first wiring;
Embedding a second wiring in the second embedding opening.

According to a fourteenth aspect of the present invention, in the method of the eleventh or twelfth aspect, a step of forming a second insulating film on the first wiring and the first insulating film; Forming a second impurity-containing region by introducing an impurity into a part of the second insulating film; and forming a second buried opening communicating with the first wiring in the second impurity-containing region in the second insulating film. Embedding the second wiring in the second embedding opening.

According to the fourteenth aspect, as described above, by providing the second impurity-containing region in the second insulating film, the film is modified in the second impurity-containing region by the introduction of impurities, and The moisture and hydroxyl groups contained are reduced and the film is less likely to absorb water. Thus, moisture in the second insulating film does not adversely affect the second wiring. As a result, inconveniences such as corrosion of the second wiring can be effectively prevented. Further, by forming the second impurity-containing region only in the contact portion with the second wiring, even if the relative dielectric constant of this portion is slightly increased due to the impurity introduction, other regions in the second insulating film are formed. Does not increase. Therefore,
In the method of manufacturing a semiconductor device according to the fourteenth aspect, inconveniences such as corrosion of the second wiring can be effectively prevented, and the interlayer insulating film made of the highly reliable second insulating film having the lowest inter-wiring capacitance can be formed. It can be easily manufactured.

According to the present invention, the second impurity-containing region is partially formed in the second insulating film in advance, and the second burying opening is formed in the second impurity-containing region.
The second impurity-containing region is formed as a side wall (inner wall) of the second embedding opening.
Only can be easily formed.

According to a fifteenth aspect of the present invention, in the configuration of the thirteenth or fourteenth aspect, the second embedding opening comprises a contact hole leading to the first wiring and a trench leading to the contact hole.

According to a sixteenth aspect of the present invention, in the method of the eleventh or twelfth aspect, a first step of forming a third insulating film on the first insulating film and the first wiring is provided.
A second step of forming a fourth insulating film on the third insulating film;
A third step of forming a second mask pattern on the fourth insulating film, and implanting an impurity into the third insulating film using the second mask pattern as a mask,
A fourth step of forming a third impurity-containing region larger than the opening of the mask pattern and located on the first wiring; and before or after the fourth step, using the second mask pattern as a mask, forming a fourth insulating film. A fifth step of forming an etching mask made of a fourth insulating film on the third insulating film by etching, and after removing the second mask pattern,
Forming a fifth insulating film on the third insulating film and the etching mask; forming a third mask pattern having an opening larger than the etching mask on the fifth insulating film; By implanting impurities into the fifth insulating film using the third mask pattern as a mask, the fifth insulating film has a size larger than the opening of the etching mask and located on the third impurity-containing region of the third insulating film. Forming a trench having a fourth impurity-containing region on a side wall by etching the fourth impurity-containing region based on the third mask pattern; Forming a contact hole having a third impurity-containing region on a side wall by etching the third impurity-containing region; And a burying the second wiring in the trench.

According to the sixteenth aspect, as described above, the third and fourth impurity-containing regions are formed in the third and fifth insulating films, and the third and fourth impurity-containing regions are formed by implanting impurities. In addition, the membrane is modified so that the moisture and hydroxyl groups contained in the membrane are reduced, and the membrane is less likely to absorb water. Thus, the moisture in the third and fifth insulating films does not adversely affect the second wiring. As a result, inconveniences such as corrosion of the second wiring can be effectively prevented. Further, by forming the third and fourth impurity-containing regions only in the contact portion with the second wiring, even if the relative dielectric constant of this portion is slightly increased due to the impurity introduction, the third and fifth impurity-containing regions are formed. The relative permittivity of other regions in the insulating film does not increase. Therefore, in the method of manufacturing a semiconductor device according to claim 16,
Inconveniences such as corrosion of the second wiring can be effectively prevented, and a highly reliable interlayer insulating film composed of the third and fifth insulating films having a low inter-wiring capacitance can be easily manufactured.

According to a sixteenth aspect, a third impurity-containing region is partially formed in the third insulating film, and a fourth impurity-containing region is partially formed in the fifth insulating film. Since the trench and the contact hole are formed in the impurity-containing region, the third and fourth impurity-containing regions can be easily formed only on the side walls (inner walls) between the trench and the contact hole.

Further, in the sixteenth aspect, the third insulating film and the fifth
By interposing the second mask pattern between the insulating film and the insulating film, the contact hole and the trench can be formed by a single etching, and as a result, the manufacturing process can be simplified.

According to a seventeenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film so as to cover a wiring layer formed on a substrate; and forming a second insulating film on the first insulating film. Forming a first mask pattern on the second insulating film, and implanting an impurity into the first insulating film using the first mask pattern as a mask, so that the first mask pattern is larger than the opening of the first mask pattern. And forming a first impurity-containing region located on the wiring layer, and etching the second insulating film using the first mask pattern as a mask, thereby forming the second insulating film on the first insulating film. After the step of forming an etching mask and removing the first mask pattern, on the first insulating film and the etching mask,
Forming a third insulating film having a dielectric constant of 3.5 or less, forming a second mask pattern having an opening larger than the etching mask on the third insulating film, A step of forming a trench by etching the third insulating film as a mask, and a step of forming a contact hole having a first impurity-containing region on a side wall by etching the first impurity-containing region using the etching mask as a mask. Forming and forming a first wiring in the contact hole and the trench.

In the seventeenth aspect, as described above, by providing the first impurity-containing region in the first insulating film, the film is modified in the first impurity-containing region by the implantation of impurities, and The moisture and hydroxyl groups contained are reduced and the film is less likely to absorb water. Thereby, the moisture in the first insulating film does not adversely affect the first wiring. As a result, inconveniences such as corrosion of the first wiring can be effectively prevented. Further, by forming the first impurity-containing region only in the contact portion with the first wiring, even if the relative dielectric constant of this portion is slightly increased by the introduction of the impurity, other regions in the first insulating film are formed. Does not increase. Therefore, in the method of manufacturing a semiconductor device according to claim 17,
Inconveniences such as corrosion of the wiring can be effectively prevented, and an interlayer insulating film made of a highly reliable first insulating film having a low inter-wiring capacitance can be easily manufactured.

According to the seventeenth aspect, by using a low dielectric constant insulating film having a dielectric constant of 3.5 or less as the third insulating film, the capacitance between wirings of the interlayer insulating film made of the third insulating film is reduced. be able to. As a result, the interlayer insulating film made of the first insulating film and the interlayer insulating film made of the third insulating film can effectively prevent inconvenience such as corrosion of the first wiring while further reducing the capacitance between the wirings. it can.

According to the seventeenth aspect, the first impurity-containing region is partially formed in the first insulating film in advance, and a contact hole is formed in the first impurity-containing region.
The first impurity-containing region is formed on the side wall (inner wall) of the contact hole
Only can be easily formed.

Further, in the seventeenth aspect, the first insulating film and the third
Since the etching mask is interposed between the insulating film and the insulating film, the contact hole and the trench can be formed by one etching, and as a result, the manufacturing process can be simplified.

In the method of manufacturing a semiconductor device according to the present invention, the impurity is implanted into the insulating film by obliquely ion-implanting the impurity into the insulating film. As described above, by ion-implanting an impurity into the insulating film obliquely, an impurity-containing region larger than the opening of the mask pattern can be easily formed in the insulating film.

According to a nineteenth aspect, in the method of manufacturing a semiconductor device according to any one of the eleventh to seventeenth aspects, the insulating film includes a silicon oxide film containing 1 atomic% or more of carbon.

According to a twentieth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the eleventh to seventeenth aspects, the insulating film includes an inorganic SOG film.

[0048]

(First Embodiment) A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of the semiconductor device according to the first embodiment. In FIG. 1, a single crystal silicon substrate 1
On top of this, a silicon oxide film 2 is formed. An organic SOG film 3 is formed on the silicon oxide film 2, and a metal wiring 7 is buried in the organic SOG film 3 up to its upper surface by using a damascene method. A modified SOG film 5 is formed on the inner wall of the trench 6 in which the metal wiring 7 is embedded.

A silicon oxide film 8 is formed on the organic SOG film 3, the modified SOG film 5, and the metal wiring 7, and a contact hole 9 communicating with the metal wiring 7 is formed in the silicon oxide film 8. In this contact hole 9, a connection hole wiring 10 is buried. On the silicon oxide film 8 and the connection hole wiring 10, the organic SOG film 1 is formed similarly to the organic SOG film 3, the modified SOG film 5, and the metal wiring 7.
1. An upper metal wiring 13 electrically connected to the modified SOG film 12 and the connection hole wiring 10 is formed.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS.

Step 1 (see FIG. 2): (100) Silicon oxide film 2 on p-type (or n-type) single-crystal silicon substrate 1
(Thickness: about 200 nm), and an organic SOG
The film 3 is formed. The composition of the organic SOG film 3 is [(CH ₃ )
₂ Si ₄ O ₇ ] _n and its thickness is about 600 nm.

The silicon oxide film 2 is formed by a plasma CVD method. As reaction gas, monosilane and nitrous oxide (SiH ₄ + N ₂ O), monosilane and oxygen (SiH ₄
+ O ₂ ), TEOS (Tetra-ethoxy-silane) and oxygen (T
EOS + O ₂ ) or the like, and the film formation temperature is about 300 to 90
0 ° C.

The silicon oxide film 2 is formed by plasma CV
Methods other than Method D (Normal pressure CVD, Low pressure CVD, ECR
Plasma CVD, photo-excited CVD, TEOS-CVD
Method, a PVD method, etc.). For example,
The gas used in the normal pressure CVD method is monosilane and oxygen (S
iH ₄ + O ₂ ), and the film formation temperature is about 400 ° C. or less. The gas used in the low pressure CVD method is monosilane and nitrous oxide (SiH ₄ + N ₂ O), and the film formation temperature is about 900 ° C. or less.

The method of forming the organic SOG film 3 is as follows. First, an alcohol-based solution of a silicon compound having the above composition (for example,
(PA + acetone) is dropped on the substrate 1 and the substrate is rotated at a rotation speed of about 2300 rpm for about 20 seconds to form a film of this solution on the substrate 1. At this time, the film of the alcohol-based solution is formed so as to be thicker in the concave portion and thinner in the convex portion than the step on the substrate 1 so as to reduce the step. As a result, the surface of the film of the alcohol-based solution is flattened.

Next, at about 100 ° C. in a nitrogen atmosphere.
About 1 minute, about 200 ° C for about 1 minute, about 300 ° C for about 1 minute, about 22 ° C for about 1 minute, about 430 ° C for about 30 minutes.
When the heat treatment is sequentially performed for about a minute, the alcoholic solvent evaporates and the polymerization reaction proceeds to form an organic SOG film having a flat surface and a thickness of about 300 nm. By repeating this film formation-heat treatment operation once more, a film thickness of about 6
A 00 nm organic SOG film 3 is obtained. In addition, this organic SOG
The film 3 corresponds to the “first insulating film” in the present invention.

The organic SOG film 3 is formed with a substantially uniform thickness over the entire surface of the substrate because the underlying surface is flat. The organic SOG film 3 is a silicon oxide film containing 1 atomic% or more of carbon.

Step 2 (see FIG. 3): A resist pattern 4 for forming a buried hole is formed on the organic SOG film 3. The resist pattern 4 corresponds to the “first mask pattern” in the present invention.

Step 3 (see FIG. 4): resist pattern 4
The organic SOG film 3 is doped with boron (boron) ions (B ⁺ ) from an oblique direction under the conditions of an acceleration energy of about 140 KeV and a dose of about 2 × 10 ¹⁵ atoms / cm ² . As described above, by introducing boron ions into the organic SOG film 3, organic components in the film are decomposed, and moisture and hydroxyl groups contained in the film are reduced.

As a result, the organic SOG film 3 does not contain any organic components, and contains only a small amount of water and hydroxyl groups.
Film (hereinafter referred to as a modified SOG film) 5. At this time, since the boron ions are implanted obliquely, the diameter of the modified SOG film 5 becomes larger than the opening of the resist pattern 4. The modified SOG film 5 corresponds to the “first impurity-containing region” in the present invention.

At this time, in order to implant boron ions so that the modified portion becomes larger at an equal ratio to the opening of the resist pattern 4, the entire silicon wafer (not shown) on which the substrate 1 is formed is rotated. In doing so, it is desirable to implant boron ions at an angle of about 15 ° to 60 ° from a normal standing on the surface of the substrate 1. A method of performing ion implantation at a predetermined angle on a silicon wafer while rotating the entire silicon wafer in this manner is generally called a rotational oblique ion implantation method.

Step 4 (see FIG. 5): Subsequently, using the resist pattern 4 as a mask, anisotropic etching is performed using a fluorocarbon-based gas as an etching gas to form a trench 6 as a buried hole in the modified SOG film 5. . At this time, in step 3, since the diameter of the modified SOG film 5 is larger than the diameter of the opening of the resist pattern 4, the inner wall of the trench 6 is formed of the modified SOG film 5. Therefore, even if a wiring is buried in the trench 6 as described later, moisture and a hydroxyl group contained in the organic SOG film 3 do not adversely affect the wiring. The trench 6 corresponds to the “embedding opening or the first embedding opening” in the present invention.

The relative dielectric constant of the modified SOG film 5 is 3.5
Although the relative dielectric constant (2.9) of the organic SOG film 3 is slightly higher than that of the organic SOG film 3, in the present embodiment, the modified SOG film 5 exists only on the inner wall of the trench 6, and other portions are the organic SOG film. Since the film 3 remains as it is, the relative dielectric constant of the whole film is greatly increased, and the capacitance between the wires is increased, so that the occurrence of signal delay can be prevented as much as possible.

Step 5 (see FIG. 6): The resist pattern is removed, and if necessary, the inside of the trench 6 is cleaned by sputter etching using an inert gas (eg, Ar). On the SOG film 5 and the organic SOG film 3, a magnetron sputtering method or CVD
A TiN film as an adhesion layer and a barrier layer is formed by using a method, a Cu film is formed thereon by using a CVD method or a plating method, and further, a CMP (Chemical Mecha)
Then, the surface of the Cu film is polished by using the nical polishing method, and finally a metal wiring 7 made of TiN and Cu is buried only in the trench 6. This technique of embedding metal wiring is generally called a damascene method. The metal wiring 7 corresponds to the “first wiring” in the present invention.

Step 6 (see FIG. 7): On the organic SOG film 3, the modified SOG film 5, and the metal wiring 7, a film thickness of about 600 nm
Of silicon oxide film 8 is formed. This silicon oxide film 8
Is the same as that of the silicon oxide film 2 described above.

Step 7 (see FIG. 8): Using a resist pattern (not shown) as a mask, anisotropic etching is performed using a fluorocarbon-based gas as an etching gas to form a contact hole 9 communicating with the metal wiring 7 in the silicon oxide film 8. I do.

Next, after the inside of the contact hole 9 is cleaned by sputter etching using an inert gas (for example, Ar), a magnetron sputtering method or a CVD method is performed on the silicon oxide film 8 including the inside of the contact hole 9.
A TiN film as an adhesion layer and a barrier layer is formed by using the CVD method, and Cu or Cu is formed thereon by using the CVD method or the plating method.
A film is formed, and the surface of the Cu film is polished by using the CMP method. Finally, TiN and Cu
Is buried.

In steps 6 and 7, as in steps 1 to 5, an organic SOG film is used instead of silicon oxide film 8.
After the film is partially modified by ion implantation using a film, a contact hole 9 may be formed in the modified portion, and a contact hole wiring 10 may be buried in the contact hole 9.

Step 8 (see FIG. 1): The organic SOG film 11, the modified SOG film 1
2 and an upper metal wiring 13 (lamination of TiN and Cu) electrically connected to the connection hole wiring 10 is formed.

Here, FIG. 9 shows that the organic SOG film (untreated) and the modified SOG film (Ar ion implantation treatment) are each subjected to a heat treatment for 30 minutes in a nitrogen atmosphere, and the TDS method (Thermal
The result of evaluation using Desorption Spectroscopy) is shown. The ion implantation conditions were as follows: acceleration energy: 1
40 KeV, dose amount: 1 × 10 ¹⁵ atoms / cm ² .

FIG. 9 shows the amount of desorption with respect to H ₂ O (m / e = 18). As is clear from FIG. 9, the modified SOG film has H ₂ O (m / e = 18). It can be seen that the desorption related to 18) is small. This is achieved by performing ion implantation on the organic SOG film to obtain a modified SOG film.
This shows that water and hydroxyl groups contained in the organic SOG film are reduced.

FIG. 10 shows an organic SOG film (untreated), an organic SOG film exposed to oxygen plasma (oxygen plasma treatment), and a modified SOG film for the purpose of examining the hygroscopicity of the organic SOG film and the modified SOG film. (Ar ion implantation) is left in the air in a clean room, and the result of evaluating the moisture in the film is shown. The amount of water in the film was determined by the FT-IR method (FourierTr
Using ansform Infrared Spectroscopy), the absorption of the O-H group in the infrared absorption spectrum (around 3500 cm ^-1 )
Was used as an index. The ion implantation conditions are acceleration energy: 140 KeV and dose: 1 × 10 ¹⁵ atoms / cm ² .

Referring to FIG. 10, it can be seen that when exposed to oxygen plasma, not only the water before and after the treatment increased, but also after one day. On the other hand, the modified SOG film not only has not increased after ion implantation, but also has a smaller increase in moisture than the organic SOG film even when left in the air in a clean room.

That is, it is understood that the modified SOG film has lower hygroscopicity than the organic SOG film.

FIG. 11 shows a pressure cooker test (PCT) (humidification test) in order to examine the moisture permeability of the modified SOG film and the organic SOG film.
As a condition, the measurement was carried out in a saturated steam atmosphere at 120 ° C. and 2 atm). Using the FT-IR method,
Absorption peak for O—H in the organic SOG film (3500
The area intensity (in the vicinity of cm ⁻¹ ) was determined, and the relationship with the PCT time was plotted.

A sample (Ar ion implantation: 20 KeV) in which only the surface was modified by ion implantation was prepared, and a sample in which the whole film was modified (Ar ion implantation: 140 KeV) and a sample in which the film was not modified (organic) SOG film: untreated), the following was found.

(A) Unmodified organic SOG film is converted to PC
In the case of T, the absorption intensity around 3500 cm ^-1 (absorption for the OH group) shows a dramatic increase.

(B) In the modified SOG film, the increase in the absorption intensity around 3500 cm ^-1 (absorption related to the OH group) is small. A sample in which only the film surface was modified is comparable to a sample in which the entire film has been modified.

From the above results, it can be seen that a layer that suppresses moisture permeability can be formed by implanting ions.

In the experiments shown in FIGS. 9 to 11, the same tendency is exhibited even when the argon ions are replaced with the same boron ions as in the first embodiment.

Including ions such as boron in the organic SOG film, including the description relating to FIGS. 9 to 11, the organic components in the film are decomposed and the moisture and hydroxyl groups contained in the film are reduced. As a result, the applicant has already proposed to prevent corrosion of the metal wiring and to prevent a recess from occurring on the side wall of the via hole formed by etching (for example, Japanese Patent Application Laid-Open No. 9-313339).
Reference).

As described above, in the first embodiment, the organic S
By forming the modified SOG film 5 having high water resistance only on the inner wall of the trench 6 in the OG film 3, corrosion of the metal wiring 7 is prevented, and the capacitance between wirings is as low as possible. Can be obtained.

Further, since only the organic SOG film 3 (modified SOG film 5) exists in the lateral direction between the metal wirings 7, it is possible to cope with further miniaturization.

(Second Embodiment) A second embodiment of the present invention
An embodiment will be described with reference to the drawings. In the second embodiment, the same components as those in the first embodiment are denoted by the same reference numerals, and a detailed description thereof will be omitted.

FIG. 12 is a cross-sectional view of the semiconductor device according to the second embodiment, which is a so-called dual damascene (dual-d
2 shows a multilayer wiring structure formed by using the amascene method.

In FIG. 12, the organic SOG film 3 and the modified S
An organic SOG film 20 is formed on the OG film 5 and the metal wiring 7. In the organic SOG film 20, a contact hole 21 communicating with the metal wiring 7 is formed. A silicon nitride film mask 22a as an etching mask for forming a contact hole 21 is formed on the organic SOG film 20, and an organic SOG film 23 is further formed thereon. A trench 24 leading to the hole 21 is formed. Organic S
A modified SOG film 25 is formed on the inner wall of the contact hole 21 in the OG film 20, and a modified SOG film 26 is formed on the inner wall of the trench 24 in the organic SOG film 23.

An upper metal interconnection 27 electrically connected to the metal interconnection 7 is formed in the contact hole 21 and the trench 24. The upper metal wiring 27 corresponds to the “second wiring” in the present invention.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIGS. Steps 1 to 6 (FIGS. 1 to 6) in the first embodiment are the same as those in the second embodiment, and thus description thereof is omitted.
Here, the subsequent steps will be described.

Step 10 (see FIG. 13): A film thickness of about 60 is formed on the organic SOG film 3, the modified SOG film 5, and the metal wiring 7.
An organic SOG film 20 having a thickness of 0 nm is formed. This organic SOG
The composition and forming method of the film 20 are the same as those of the organic SOG film 3. The organic SOG film 20 corresponds to the “second insulating film or the third insulating film” in the present invention.

Step 11 (see FIG. 14): Organic SOG film 2
Then, a silicon nitride film 22 is formed on 0. The silicon nitride film 22 corresponds to the “fourth insulating film” of the present invention.

Step 12 (see FIG. 15): A resist pattern 28 is formed on the silicon nitride film 22. The resist pattern 28 corresponds to the “second mask pattern” of the present invention.

Step 13 (see FIG. 16): Using the resist pattern 28 as a mask, boron (boron) ions (B ⁺ ) are accelerated with respect to the organic SOG film 20 using the same oblique ion implantation method as in Step 3 described above. Energy: about 140K
Doping is performed under conditions of eV and a dose amount of about 2 × 10 ¹⁵ atoms / cm ² . As described above, by introducing boron ions into the organic SOG film 20, organic components in the film are decomposed, and moisture and hydroxyl groups contained in the film are reduced.

As a result, the organic SOG film 20 is changed to a modified SOG film 25 containing no organic components and containing only a small amount of water and hydroxyl groups. At this time, since the boron ions are implanted obliquely, the modified SOG film 25
The diameter becomes larger than the opening of the resist pattern 28.
The modified SOG film 25 corresponds to the “second impurity-containing region or the third impurity-containing region” in the present invention.

Step 14 (see FIG. 17): The silicon nitride film 22 is etched by RIE using the resist pattern 28 as a mask to form a silicon nitride film mask 22a. The silicon nitride film mask 22a corresponds to the "mask for etching" of the present invention.

Step 15 (see FIG. 18): After removing the resist pattern 28, an organic SO having a thickness of about 600 nm is formed on the modified SOG film 25 and the silicon nitride film mask 22a.
A G film 23 is formed. The composition and forming method of the organic SOG film 23 are the same as those of the organic SOG film 3. Note that the organic SOG film 23 corresponds to the “second insulating film or the fifth insulating film” in the present invention.

Step 16 (see FIG. 19): Organic SOG film 2
A resist pattern 29 having a stripe shape is formed on the resist pattern 3. The opening of the resist pattern 29 includes the opening of the silicon nitride film mask 22a, and has an area larger than that of the silicon nitride film mask 22a. The resist pattern 29 corresponds to the “third mask pattern” in the present invention.

Next, using the resist pattern 29 as a mask, the same oblique ion implantation method as in the above step 3 was used.
For the organic SOG film 23, boron (boron) ions (B
⁺ ) Acceleration energy: about 140 KeV, dose amount: about 2 ×
Doping is performed under the condition of 10 ¹⁵ atoms / cm ² . in this way,
By introducing boron ions into the organic SOG film 23, the organic components in the film are decomposed and the moisture and hydroxyl groups contained in the film are reduced.

As a result, the organic SOG film 23 is changed to a modified SOG film 26 containing no organic components and containing only a small amount of water and hydroxyl groups. At this time, since the boron ions are implanted obliquely, the modified SOG film 26
The width becomes larger than the opening of the resist pattern 29.
The modified SOG film 26 corresponds to the “second impurity-containing region or the fourth impurity-containing region” in the present invention.

Step 17 (see FIG. 20): Using the resist pattern 29 and the silicon nitride film mask 22a as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed to form the modified SOG film 25 and the modified SOG film. 26 is etched. In this case, first, the modified SOG film 26 is etched with the same opening width as the resist pattern 29, and the etching of the modified SOG film 26 is completed when the modified SOG film 26 reaches the silicon nitride film mask 22a.
A trench 24 is formed in the modified SOG film 26. Subsequently, using the silicon nitride film mask 22a as a mask, the modified SOG film 25 is etched with the same opening diameter as this mask, and a contact hole 21 leading to the metal wiring 7 is formed in the modified SOG film 25.

As described above, the silicon nitride film mask 22a
Is used as an etching stopper, the trench 24 and the contact hole 21 can be formed by a single etching.

Moreover, since the trench 24 having a large opening width is formed first, and then the contact hole 21 is formed, the aspect ratio is not increased as compared with the method in which the contact hole 21 is formed first, and etching control is not performed. Easy.

At this time, in step 13, the diameter of the modified SOG film 25 is formed to be larger than the diameter of the opening of the silicon nitride film mask 22a, and in step 16, the width of the modified SOG film 26 is Since the contact hole 21 is formed larger than the opening width, the inner wall of the contact hole 21 is formed of the modified SOG film 25, and the inner wall of the trench 24 is formed of the modified SOG film 26. Therefore, even if a wiring is buried in the contact hole 21 and the trench 24 as described later, moisture and hydroxyl groups contained in the organic SOG films 20 and 23 do not adversely affect the wiring.

The relative dielectric constant of each of the modified SOG films 25 and 26 is 3.5, which is slightly higher than the relative dielectric constant (2.9) of each of the organic SOG films 20 and 23. In the embodiment, the modified SOG film 25 exists only on the inner wall of the contact hole 21, the modified SOG film 26 exists only on the inner wall of the trench 21, and the other portions remain the organic SOG film 20 or the organic SOG film 23. Therefore, the relative dielectric constant of the entire film is greatly increased, and the capacitance between wirings is increased, so that occurrence of signal delay can be prevented as much as possible.

Step 18 (see FIG. 12): After cleaning the inside of the trench 24 and the contact hole 21 by sputter etching using an inert gas (for example, Ar), the organic SOG film 23 including the inside of the trench 24 and the contact hole 21 is removed. And a TiN film as an adhesion layer and a barrier layer is formed on the modified SOG film 26 using a magnetron sputtering method or a CVD method, and a Cu film is formed thereon using a CVD method or a plating method. Then, the surface of the Cu film is polished by using the CMP method, and finally the trench 2 is polished.
4 and the contact hole 21 are buried with an upper metal wiring 27 made of TiN and Cu. The upper metal wiring 27 corresponds to the “second wiring” in the present invention.

As described above, in the second embodiment, the same function and effect as in the first embodiment can be enjoyed even in a multilayer wiring structure formed by using a so-called dual damascene method.

(Third Embodiment) A third embodiment of the present invention
An embodiment will be described with reference to the drawings. In the third embodiment, the same components as those in the first embodiment or the second embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 21 is a cross-sectional view of a semiconductor device according to the third embodiment, and shows a multi-layer wiring structure formed by using a dual damascene method as in the second embodiment.

In FIG. 21, the organic SOG film 3 and the modified S
An organic SOG film 30 is formed on the OG film 5 and the metal wiring 7. In the organic SOG film 30, a contact hole 21 leading to the metal wiring 7 and a trench 24 leading to the contact hole 21 are formed. Modified SO is formed on the inner walls of the contact hole 21 and the trench 24.
A G film 31 is formed.

In the contact hole 21 and the trench 24, an upper metal wiring 27 electrically connected to the metal wiring 7 is formed.

Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Steps 1 to 6 (FIGS. 1 to 6) in the first embodiment are the same as those in the third embodiment, and thus description thereof will be omitted, and the subsequent steps will be described here.

Step 20 (see FIG. 22): On the organic SOG film 3, the modified SOG film 5, and the metal wiring 7, a film thickness of about 90
An organic SOG film 30 having a thickness of 0 nm is formed. This organic SOG
The composition and the formation method of the film 30 are the same as those of the organic SOG film 3, but the thickness of each film is set to a predetermined value by repeating the above-described film formation to heat treatment three times in total. The organic SOG film 30 corresponds to the “second insulating film” in the present invention.

Step 21 (see FIG. 23): Organic SOG film 3
A resist pattern 29 in the form of a stripe is formed on 0.

Step 22 (see FIG. 24): Using the resist pattern 29 as a mask, boron (boron) ions (B ⁺ ) are accelerated with respect to the organic SOG film 30 using the same oblique ion implantation method as in the above step 3. Energy: about 160K
Doping is performed under conditions of eV and a dose amount of about 2 × 10 ¹⁵ atoms / cm ² . As described above, by introducing boron ions into the organic SOG film 30, organic components in the film are decomposed, and moisture and hydroxyl groups contained in the film are reduced.

As a result, the organic SOG film 30 is changed to a modified SOG film 31 containing no organic components and containing only a small amount of water and hydroxyl groups. At this time, since the boron ions are implanted obliquely, the modified SOG film 31
The width becomes larger than the opening of the resist pattern 29.
The modified SOG film 31 corresponds to the “second impurity-containing region” in the present invention.

Step 23 (see FIG. 25): Using the resist pattern 29 as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed until the modified SOG film 31 has a thickness of about 450 nm. Etching is performed to form a trench 24 in the modified SOG film 31.

Step 24 (see FIG. 26): After removing the resist pattern 29, a resist pattern 32 is formed on the modified SOG film 31 again. The opening 32 a of the resist pattern 32 is located in the trench 24.

Step 25 (see FIG. 27): Using the resist pattern 32 as a mask, anisotropic etching using a fluorocarbon gas as an etching gas is performed to etch the modified SOG film 31.

Step 26 (see FIG. 28): By removing the resist pattern 32, the modified SOG film 31 is provided with a trench 24 and a contact hole 2 which communicate with the metal wiring 7.
Form one.

At this time, in step 22, since the dimensions of the modified SOG film 31 are formed larger than the opening width of the resist pattern 29, the inner walls of the contact holes 21 and the trenches 24 are formed of the modified SOG film 31. You. Therefore, even if a wiring is buried in the contact hole 21 and the trench 24 as described later, moisture and a hydroxyl group contained in the organic SOG film 30 do not adversely affect the wiring.

The relative permittivity of the modified SOG film 31 is 3.
5, the relative dielectric constant of the organic SOG film 30 (2.9)
Although slightly higher, in the third embodiment, the modified SOG film 31 exists only on the inner wall of the contact hole 21 and the trench 24, and the other portions remain as the organic SOG film 30. The rate is greatly increased, and the occurrence of signal delay due to an increase in the capacitance between wirings can be prevented as much as possible.

Step 27 (see FIG. 21): After cleaning the inside of the trench 24 and the contact hole 21 by sputter etching using an inert gas (for example, Ar), the organic SOG film 30 including the inside of the trench 24 and the contact hole 21 is removed. And a TiN film as an adhesion layer and a barrier layer is formed on the modified SOG film 31 by using a magnetron sputtering method or a CVD method, and a Cu film is formed thereon by using a CVD method or a plating method. Further, the surface of the Cu film is polished by using the CMP method, and finally, an upper metal wiring 27 made of TiN and Cu is buried in the contact hole 21 and the trench 24.

The technical idea that can be grasped from the third embodiment will be described below together with its effects.

A first insulating film (organic SOG film 3) on a substrate
Forming an impurity-containing region (modified SOG film 5) by introducing an impurity into a part of the first insulating film; and forming a second region in the impurity-containing region in the first insulating film. (1) forming an embedding opening (trench 6); and forming a first wiring (metal wiring 7) in the first embedding opening.
, A step of forming a sixth insulating film (organic SOG film 30) on the first insulating film and the first wiring, and a fifth mask pattern (resist pattern 29) on the sixth insulating film. Forming a fifth mask pattern and using the fifth mask pattern as a mask to inject impurities into the sixth insulating film in an oblique direction, so that the sixth insulating film is larger than the opening of the fifth mask pattern and Forming a fifth impurity-containing region (modified SOG film 31) located on the first wiring, and partially thinning the fifth impurity-containing region based on the fifth mask pattern; Forming a sixth mask pattern (resist pattern 32) on the thinned region; and contacting the fifth impurity-containing region with the first wiring based on the sixth mask pattern. Forming a hole, at least in the contact hole, a manufacturing method of a semiconductor device comprising a step of forming a second wiring which is electrically connected to the first wiring.

In the third embodiment, the modified SOG is formed on the inner walls of the contact hole 21 and the trench 24, respectively.
The step of forming the film 31 is performed in two steps as in the second embodiment.
There is no need to do it separately. Moreover, there is no need to provide the silicon nitride film mask 22. As a result, the manufacturing process can be simplified as compared with the second embodiment.

Further, since the trench 24 having a large opening width is formed first, and then the contact hole 21 is formed, the aspect ratio is not increased as compared with the method of forming the contact hole 21 first, and the etching control is reduced. Easy.

(Fourth Embodiment) A fourth embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings. In the fourth embodiment, the same components as those in the first to third embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

FIG. 29 is a sectional view of a semiconductor device according to the fourth embodiment. The fourth embodiment has a multilayer wiring structure formed by using a dual damascene method as in the second and third embodiments. However, in the fourth embodiment, unlike the second and third embodiments, the modified S
The OG film is formed only on the inner wall of the contact hole 21, and is not formed on the inner wall of the trench 24. Hereinafter, the structure of the fourth embodiment will be described in detail.

Referring to FIG. 29, single crystal silicon substrate 1
A wiring layer 42 having a thickness of about 300 nm to 500 nm is formed thereon. On the wiring layer 42, 9
Organic SOG having a thickness of about 00 nm to 1100 nm
A film 43 is formed. The organic SOG film 43 includes
Contact hole (via hole) 2 leading to wiring layer 42
1 is formed. On the organic SOG film 43, a silicon nitride film mask 44a as an etching mask for forming the contact hole 21 is 20 nm to 40 nm.
It is formed with a film thickness of about. This silicon nitride film mask 44a has a lower etching rate than the organic SOG film 43. A low dielectric constant insulating film 48 having a dielectric constant of 3.5 or less is formed on the silicon nitride film
It is formed with a thickness of about 00 nm.

As the low dielectric constant insulating film 48, for example, an organic SOG film (dielectric constant 2.9) or an amorphous carbon film (dielectric constant 2.0 to 2.5) is used. As the low dielectric constant insulating film 48, a material having an etching rate higher than that of the silicon nitride film mask 44a is used. Note that the low-dielectric-constant insulating film 48 has a trench 24 that is connected to the contact hole 21.
On the inner wall of the contact hole 21 in the organic SOG film 43, a modified SOG film 45 is formed.

In the contact hole 21 and the trench 24, the wiring layer 4 is formed using a dual damascene method.
An upper metal wiring 27 electrically connected to the semiconductor device 2 is buried. The upper metal wiring 27 corresponds to the "first wiring" in the present invention (claims 6 and 17).

Here, in the fourth embodiment, as described above, the modified SOG in which impurities are introduced into the organic SOG film 43 is used.
By providing the film 45, in the modified SOG film 45, the film is reformed by the introduction of impurities, so that moisture and hydroxyl groups contained in the film are reduced and the film is less likely to absorb water. Thus, moisture in the organic SOG film 43 does not adversely affect the upper metal wiring 27. As a result, it is possible to effectively prevent inconvenience such as corrosion at the contact hole 21 portion of the upper metal wiring 27.

Further, by forming the modified SOG film 45 only in the contact portion of the organic SOG film 43 with the upper metal wiring 27, the relative permittivity of this portion is slightly increased by the introduction of impurities. However, the relative dielectric constant of other regions in the organic SOG film 43 does not increase. Therefore, in the fourth embodiment, similarly to the above-described second and third embodiments, inconveniences such as corrosion in the contact hole 21 of the upper metal wiring 27 can be effectively prevented, and the capacitance between the wirings is as low as possible. Thus, an interlayer insulating film composed of the organic SOG film 43 (modified SOG film 45) having high reliability can be obtained.

Further, in the fourth embodiment, the low-dielectric-constant insulating film 48 having a dielectric constant of 3.5 or less is used as the upper insulating film, so that the wiring between the interlayer insulating films formed of the low-dielectric-constant insulating film 48 can be reduced. The capacity can be reduced. As a result,
By combining an interlayer insulating film made of the organic SOG film 43 (modified SOG film 45) and an interlayer insulating film made of the low dielectric constant insulating film 48, the upper layer metal in the contact hole 21 can be reduced while the inter-wiring capacitance is further reduced. Problems such as corrosion of the wiring 27 can be effectively prevented.

The contact hole (via hole) 2
Inconveniences such as recesses and poisoned vias that occur during the etching process 1 are mainly caused by contact holes (via holes) 21.
Therefore, if the modified SOG film 45 is formed on the inner wall of the contact hole (via hole) 21, these disadvantages can be solved, and the trench of the low dielectric constant insulating film 48 made of an organic SOG film or the like can be solved. 24 on the inner wall
It is considered that there is no problem even if the OG film is not formed.

Next, a method of manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS.

Step 30 (see FIG. 30): A wiring layer 42 is formed on the (100) p-type (or n-type) single-crystal silicon substrate 1 to a thickness of about 300 nm to 500 nm. An organic SOG film 43 having a thickness of 900 nm to 1100
It is formed with a thickness of about nm. The composition and forming method of the organic SOG film 43 are the same as those of the organic SOG film 3 of the first embodiment.
Is the same as The organic SOG film 43 corresponds to the “first insulating film” in the present invention (claims 6 and 17). Further, a silicon nitride film 44 is formed on the organic SOG film 43 by 20.
It is formed with a thickness of about nm to 40 nm. The silicon nitride film 44 corresponds to the "second insulating film" of the present invention (claim 17).

Step 31 (see FIG. 31): A resist pattern 46 is formed on the silicon nitride
It is formed with a thickness of about 0 nm. The resist pattern 46 corresponds to the “first mask pattern” of the present invention (claim 17).

Step 32 (see FIG. 32): Using the resist pattern 46 as a mask, the same rotation oblique ion implantation method as in step 3 of the first embodiment is used to implant boron (boron) ions ( B ⁺ ) acceleration energy: about 300 to 500 KeV, dose amount: 1 × 10 ¹⁵ ato
Doping is performed under conditions of about ms / cm ² or more. As described above, by introducing boron ions into the organic SOG film 43, organic components in the film are decomposed, and moisture and hydroxyl groups contained in the film are reduced.

As a result, the ion-implanted region of the organic SOG film 43 is changed to a modified SOG film 45 containing no organic components and containing only a small amount of water and hydroxyl groups. At this time, since the boron ions are implanted obliquely, the diameter of the modified SOG film 45 becomes larger than the opening of the resist pattern 46. Note that this modified SOG film 45
This corresponds to the “first impurity-containing region” in the present invention (claims 6 and 17).

Step 33 (see FIG. 33): The silicon nitride film 44 is anisotropically etched by the RIE method using the resist pattern 46 as a mask, so that the opening 47 is formed.
Is formed. still,
This silicon nitride film mask 44a corresponds to the "etching mask" of the present invention (claims 8 and 17).

Step 34 (see FIG. 34): After removing the resist pattern 46, a low dielectric constant insulating film 48 having a thickness of about 300 nm to 500 nm is formed on the modified SOG film 45 and the silicon nitride film mask 44a. Form. When an organic SOG film is used as the low dielectric constant insulating film 48,
The organic SOG film 3 is formed by the same composition and formation method as those of the organic SOG film 3. When amorphous carbon is used as the low dielectric constant insulating film 48, it is deposited by a CVD method.
The low dielectric constant insulating film 48 is referred to as the “second
Insulating film (Claims 6 and 7) or third insulating film (Claim 1)
7)).

Step 35 (see FIG. 35): A resist pattern 49 is formed on the low dielectric constant insulating film 48. The opening of the resist pattern 49 includes the opening of the silicon nitride film mask 44a, and has an area larger than that of the silicon nitride film mask 44a. The resist pattern 49 corresponds to the “second mask pattern” in the present invention (claim 17).

Step 36 (see FIG. 36): Using the resist pattern 49 and the silicon nitride film mask 44a as a mask, anisotropic etching using a fluorocarbon-based gas as an etching gas is performed to form the low dielectric constant insulating film 48 and the modified SOG. The film 45 is etched. In this case, first, the low dielectric constant insulating film 48 has the same opening width as the resist pattern 49.
Is etched to reach the silicon nitride film mask 44a, the etching of the low dielectric constant insulating film 48 ends. As a result, the trench 24 is formed in the low dielectric constant insulating film 48. Subsequently, using the silicon nitride film mask 44a as a mask, the modified SOG film 4 has the same opening diameter as this mask.
5 is etched, and the modified SOG film 45 is
Is formed.

As described above, the silicon nitride film mask 44a
Is used as an etching stopper, the trench 24 and the contact hole 21 can be formed by one etching, and as a result, the manufacturing process can be simplified.

In addition, since the trench 24 having a large opening width is formed first, and then the contact hole 21 is formed, the aspect ratio is not increased as compared with the method in which the contact hole 21 is formed first, and etching control is not performed. Easy.

Since the diameter of the modified SOG film 45 in step 32 is larger than the diameter of the opening of the silicon nitride film mask 44a, the inner wall of the contact hole 21 formed in step 36 is modified. Quality SOG film 45
It consists of. Therefore, even if wiring is buried in the contact hole 21 as described later, the organic SOG film 43
Does not adversely affect the wiring.

The relative dielectric constant of the modified SOG film 45 is 3.
5, the relative dielectric constant of the organic SOG film 43 (2.9)
Although slightly higher, in the fourth embodiment, the modified SOG film 45
Is present only on the inner wall of the contact hole 21, and the other portions remain as the organic SOG film 43. Therefore, the relative dielectric constant of the entire film is greatly increased, so that the capacitance between wirings is increased and signal delay occurs. Can be effectively prevented.

Step 37 (see FIG. 29): After cleaning the inside of the trench 24 and the contact hole 21 by sputter etching using an inert gas (eg, Ar), a low dielectric constant insulating film including the inside of the trench 24 and the contact hole 21 is formed. On the film 48, TiN as an adhesion layer and a barrier layer is formed by magnetron sputtering or CVD.
A Cu film is formed thereon by using a CVD method or a plating method, and the surface of the Cu film is polished by using a CMP method. Upper metal wiring 27 made of TiN and Cu
Is buried. The upper metal wiring 27 corresponds to the "first wiring" in the present invention (claims 6 and 17).

As described above, in the fourth embodiment, the same function and effect as in the first embodiment can be obtained in a multilayer wiring structure formed by using a so-called dual damascene method.

It should be noted that the embodiment disclosed this time is an example in all respects and should not be construed as limiting. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and further includes all modifications within the scope and meaning equivalent to the terms of the claims.

For example, the same operation and effect as those of the above-described embodiment can be obtained even when the present invention is implemented as follows.

(1) Instead of the organic SOG film, a fluorocarbon film, polyimide, or siloxane-knitted polyimide is used.

(2) In place of Cu as the wiring material, formed by aluminum, gold, silver, silicide, high melting point metal, doped polysilicon, titanium nitride (TiN), tungsten titanium (TiW) or a laminated structure thereof I do.

(3) TiN as adhesion layer and barrier layer
Has a laminated structure with Ti, TaN, Ta and the like. Or
Instead of TiN, Ti, TaN, Ta or the like is used.

(4) Heat treatment is performed on the modified SOG film. In this case, since the number of dangling bonds in the modified SOG film is reduced, the hygroscopicity is further reduced, and the permeation of moisture is further reduced.

(5) The composition of the organic SOG film is represented by the general formula (1)
Is replaced with an inorganic SOG film, and ion implantation is performed on the inorganic SOG film. In this case, moisture and hydroxyl groups contained in the inorganic SOG film can be reduced.

(6) In the above embodiment, boron ions are used as ions to be implanted into the organic SOG film. However, any ions may be used as long as they result in modification of the organic SOG film.

Specifically, ions having relatively small mass such as argon ion, boron ion and nitrogen ion are suitable, and among them, boron ion is most suitable.
In addition to these, the following ions can be expected to have a sufficient effect.

Inert gas ions other than argon (helium ion, neon ion, krypton ion, xenon ion, radon ion). Since the inert gas does not react with the organic SOG film, there is no possibility that an adverse effect is caused by the ion implantation.

IIIb, IVb, Vb, VI other than boron and nitrogen
b, VIIb Elemental simple ions of each group and their compound ions. In particular, oxygen, aluminum, sulfur, chlorine, gallium,
Elemental elemental ions of germanium, arsenic, selenium, bromine, antimony, iodine, indium, tin, tellurium, lead, bismuth and their compound ions.

Group IVa and Va element simple ions and their compound ions. In particular, titanium, vanadium, niobium,
Elemental ions of hafnium and tantalum and their compound ions.

Each ion is used in combination of a plurality of types.
In this case, a more excellent effect can be obtained by the synergistic action of each ion.

(7) In the above embodiment, ions are implanted into the organic SOG film. However, the ions are not limited to ions, but may be atoms, molecules, or particles (in the present invention, these are collectively referred to as impurities). .

(8) As a sputtering method, other than magnetron sputtering, a method such as diode sputtering, high frequency sputtering, quadrupole sputtering or the like may be used.

(9) As a method of sputter etching,
In addition to using an inert gas, a reactive gas (for example, CCl
₄ , reactive ion beam etching (R ₆ ) using SF ₆ )
IBE, also called reactive ion milling).

(10) In the second embodiment, Step 14 is performed before Step 13.

(11) Instead of a single crystal silicon substrate (semiconductor substrate), a conductive substrate or an insulating substrate such as glass is used. That is, in the above embodiment, an example in which an interlayer insulating film is formed on a single crystal silicon substrate is shown. However, for example, an interlayer insulating film is formed on a semiconductor layer on an insulating substrate such as an LCD. The present invention can be sufficiently applied to a device having such a structure, and even a device having an insulating film formed on such an insulating substrate belongs to the concept of “semiconductor device” in the present invention.

(12) Metal wiring 7 or upper metal wiring 27
May be separated from each other or connected at an end, and may be placed at any place as long as an insulating film is interposed between wirings.

(13) In the above embodiment, the example in which the metal wiring 7 is buried in the trenches 6 and 24 has been described. However, other contact holes and via holes also belong to the concept of “buried hole”. In the above embodiments, a contact hole and a via hole are synonymous.

(14) Although an organic SOG film or amorphous carbon is shown as the low dielectric constant insulating film of the fourth embodiment, another insulating film may be used as long as the dielectric constant is 3.5 or less. For example, HSQ (hydrogen silsesoxane: dielectric constant 3.0) or amorphous fluororesin (dielectric constant 2.
1) can also be adopted.

[0171]

As described above, according to the present invention, a highly reliable semiconductor device is provided by obtaining an interlayer insulating film in which wiring corrosion is prevented and an increase in relative dielectric constant is prevented as much as possible. can do.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a semiconductor device according to a first embodiment of the invention.

FIG. 2 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 3 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 4 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment, which embodies the present invention;

FIG. 5 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 6 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment, which embodies the present invention;

FIG. 7 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment which embodies the present invention;

FIG. 8 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment that embodies the present invention;

FIG. 9 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 10 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 11 is a characteristic diagram for explaining the embodiment of the present invention.

FIG. 12 is a schematic sectional view of a semiconductor device according to a second embodiment of the invention.

FIG. 13 is a schematic sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

FIG. 14 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment of the invention.

FIG. 15 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 16 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 17 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 18 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 19 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 20 is a schematic cross-sectional view showing a manufacturing process of the semiconductor device according to the second embodiment which embodies the present invention;

FIG. 21 is a schematic sectional view of a semiconductor device according to a third embodiment of the invention;

FIG. 22 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 23 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 24 is a schematic sectional view showing a manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 25 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 26 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 27 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 28 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the third embodiment which embodies the present invention;

FIG. 29 is a schematic sectional view of a semiconductor device according to a fourth embodiment of the invention;

FIG. 30 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 31 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 32 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 33 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 34 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment which embodies the present invention;

FIG. 35 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

FIG. 36 is a schematic sectional view showing the manufacturing process of the semiconductor device according to the fourth embodiment of the invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 3,20,23,30,43 Organic SOG film 4,28,29,32,46,49 Resist pattern 5,25,26,31,45 Modified SOG film 6,24 Trench 7 Metal wiring 21 Contact Hole 22a, 44a Silicon nitride film mask 27 Upper metal wiring 42 Wiring layer

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Atsuhiro Nishida 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Yasunori Inoue 2-chome, Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. (72) Inventor Hideki Mizuhara 2-5-5 Keihanhondori, Moriguchi-shi, Osaka F-term (reference) 5F033 GG04 HH04 HH08 HH11 HH13 HH14 HH17 HH18 HH21 HH23 HH25 HH33 JJ04 JJ08 JJ11 JJ13 JJ14 JJ17 JJ18 JJ21 JJ23 JJ25 JJ33 KK04 KK08 KK11 KK13 KK14 KK17 KK18 KK21 KK25 KK33 MM01 MM02 MM12 MM13 NN06 NN07 Q12 Q16 Q16 Q28 Q28 QQ92 RR01 RR04 RR06 RR09 RR12 RR21 RR22 RR24 RR25 SS01 SS02 SS04 SS07 SS11 SS12 SS13 SS14 SS15 SS22 TT04 TT06 TT07 WW04 XX18 XX24 XX27

Claims (20)

[Claims] A first wiring which is substantially buried in the first insulating film up to its upper surface; and a first impurity-containing region formed only in a contact portion of the first insulating film with the first wiring. A semiconductor device comprising: A second insulating film formed on the first wiring and the first insulating film; an embedding opening formed in the second insulating film and communicating with the first wiring; 2. The semiconductor device according to claim 1, further comprising: a second wiring buried in the burying opening, wherein a second impurity-containing region is formed only in a contact portion of the second insulating film with the second wiring. 13. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 2, wherein said burying opening comprises a contact hole communicating with said first wiring and a trench communicating with said contact hole. 4. The semiconductor device according to claim 3, wherein said second insulating film comprises a third insulating film in which said contact hole is formed and a fourth insulating film in which said trench is formed. . 5. Between the third insulating film and the fourth insulating film,
The semiconductor device according to claim 4, further comprising a mask for etching the contact hole. 6. A first insulating film formed on a wiring layer and having a contact hole communicating with the wiring layer, and a second insulating film formed on the first insulating film and having a trench communicating with the contact hole. A film, a first wiring buried in the contact hole and the trench, and formed to be in contact with the wiring layer, and formed only in a contact portion of the first insulating film with the first wiring. A semiconductor device comprising: a first impurity-containing region. 7. The semiconductor device according to claim 6, wherein said second insulating film has a dielectric constant of 3.5 or less. 8. The semiconductor device according to claim 6, further comprising a mask for etching said contact hole between said first insulating film and said second insulating film. 9. The semiconductor device according to claim 1, wherein the insulating film includes a silicon oxide film containing 1 atomic% or more of carbon. 10. The semiconductor device according to claim 1, wherein said insulating film includes an inorganic SOG film. 11. A step of forming a first insulating film on a substrate; a step of introducing an impurity into a part of the first insulating film to form a first impurity-containing region; In the first impurity-containing region,
Forming a first embedding opening; embedding a first wiring in the first embedding opening;
A method for manufacturing a semiconductor device, comprising: 12. A step of forming a first insulating film on a substrate, a step of forming a first mask pattern on the first insulating film, and forming the first insulating film on the first insulating film by using the first mask pattern as a mask. Forming a first impurity-containing region larger than the opening of the first mask pattern in the first insulating film by implanting an impurity; and forming the first impurity-containing region using the first mask pattern as a mask. Forming a first burying opening having a first impurity-containing region on a side wall by etching the region; burying a first wiring in the first burying opening;
A method for manufacturing a semiconductor device, comprising: 13. A step of forming a second insulating film on the first wiring and the first insulating film, wherein the second insulating film has a second impurity-containing region on a side wall, and Forming a second embedding opening communicating with the wiring; embedding a second wiring in the second embedding opening;
The method of manufacturing a semiconductor device according to claim 11, further comprising: 14. A step of forming a second insulating film on the first wiring and the first insulating film, and forming a second impurity-containing region by introducing an impurity into a part of the second insulating film. And in the second impurity-containing region of the second insulating film,
Forming a second embedding opening communicating with the first wiring, embedding a second wiring in the second embedding opening,
The method of manufacturing a semiconductor device according to claim 11, further comprising: 15. The semiconductor device according to claim 13, wherein the second embedding opening includes a contact hole communicating with the first wiring and a trench communicating with the contact hole.
15. A method for manufacturing a semiconductor device according to item 14. 16. A first step of forming a third insulating film on the first insulating film and the first wiring, a second step of forming a fourth insulating film on the third insulating film, A third step of forming a second mask pattern on the fourth insulating film; and implanting impurities into the third insulating film using the second mask pattern as a mask, so that the third Fourth forming a third impurity-containing region larger than the opening of the second mask pattern and located on the first wiring.
An etching mask made of the fourth insulating film on the third insulating film by etching the fourth insulating film using the second mask pattern as a mask before or after the fourth step. Forming a fifth insulating film on the third insulating film and the etching mask after removing the second mask pattern; and performing the etching on the fifth insulating film. Forming a third mask pattern having an opening that is larger than the mask for the etching, and implanting an impurity into the fifth insulating film using the third mask pattern as a mask, thereby forming the etching film in the fifth insulating film. Forming a fourth impurity-containing region larger than the opening of the mask and located on the third impurity-containing region of the third insulating film; Forming a trench having a fourth impurity-containing region on the side wall by etching the fourth impurity-containing region; and etching the third impurity-containing region on the side wall based on the etching mask. 12. The method according to claim 11, further comprising: forming a contact hole having a third impurity-containing region; and burying a second wiring in the contact hole and the trench.
3. The method for manufacturing a semiconductor device according to item 2. 17. A step of forming a first insulating film so as to cover a wiring layer formed on a substrate; a step of forming a second insulating film on the first insulating film; and a step of forming the second insulating film. Forming a first mask pattern thereon, and using the first mask pattern as a mask, injecting impurities into the first insulating film, so as to be larger than the opening of the first mask pattern and to form the wiring layer. Forming a first impurity-containing region located above; and etching the second insulating film using the first mask pattern as a mask, so that the second insulating film is formed on the first insulating film. Forming a third insulating film having a dielectric constant of 3.5 or less on the first insulating film and the etching mask after removing the first mask pattern. And before Forming a second mask pattern having an opening larger than the etching mask on the third insulating film; and etching the third insulating film using the second mask pattern as a mask, thereby forming a trench. Forming a contact hole having a first impurity-containing region on a side wall by etching the first impurity-containing region using the etching mask as a mask; and forming a contact hole in the contact hole and the trench. A method of manufacturing a semiconductor device, comprising: a step of embedding one wiring. 18. The method of manufacturing a semiconductor device according to claim 12, wherein the impurity is implanted into the insulating film by ion-implanting the impurity into the insulating film obliquely. 19. The method of manufacturing a semiconductor device according to claim 11, wherein said insulating film includes a silicon oxide film containing 1 atomic% or more of carbon. 20. The method according to claim 11, wherein the insulating film includes an inorganic SOG film.