CN1858911B - Tft array panel, liquid crystal display including same, and method of manufacturing tft array panel - Google Patents

Abstract

A thin film transistor (TFT) array panel that effectively minimizes light leakage current and a liquid crystal display including the same are disclosed. The panel includes a transistor structure having: a gate electrode formed over an insulating substrate; a semiconductor layer formed over and insulated from the gate electrode; a light blocking layer formed around and overlapping a portion of the gate electrode ; The data line intersects with the gate line to form a source electrode, and the source electrode overlaps with a part of the semiconductor layer; the drain electrode, opposite to the source electrode, overlaps with a part of the semiconductor layer, and the panel also includes a pixel electrode, and the pixel electrode forms It is above and insulated from the transistor structure and is electrically connected to the drain electrode.

Description

TFT array panel, liquid crystal display including same, and manufacturing method of TFT array panel

This application claims priority from Korean Patent Application No. 10-2005-0036798 filed with the Korean Intellectual Property Office on May 2, 2005, the disclosure of which is incorporated herein by reference.

technical field

The invention relates to a thin film transistor (TFT) array panel, a liquid crystal display including it, and a manufacturing method of the TFT array panel. More specifically, the present invention relates to a TFT array panel capable of avoiding light leakage current in a channel region, a liquid crystal display including the same, and a manufacturing method of the TFT array panel.

Background technique

A liquid crystal display includes a color filter panel including color filters and a TFT array panel including a thin film transistor (TFT) array. The color filter panel and the TFT array panel face each other and are assembled with a sealing wire interposed therebetween. A liquid crystal layer is formed at an air gap defined between the color filter panel and the TFT array panel. That is, the liquid crystal display includes two panels (a color filter panel and a TFT array panel) including electrodes and a liquid crystal layer interposed between the two panels. When a voltage is applied to the electrodes, the liquid crystal display generates an image by adjusting the amount of light transmitted therethrough through the rearrangement of liquid crystal molecules of the liquid crystal layer. Because LCDs are non-emissive devices, a backlight unit can be placed behind the TFT array panel as a light source. By controlling the orientation of liquid crystals, the transmittance of light emitted from the backlight is adjusted.

Each pixel of the TFT array panel includes a switching device. The switch device is a three-terminal device, including a control terminal connected with a gate line, an input terminal connected with a data line, and an output terminal connected with a pixel electrode.

In a liquid crystal display using such a switching device, light leakage current may occur when light is incident on a channel region of the switching device, thereby reducing contrast, or causing poor display quality such as image flicker. The light leakage current may be caused by external light, or by light emitted from the backlight of the liquid crystal display.

Contents of the invention

The present invention provides an embodiment of a thin film transistor (TFT) array panel capable of avoiding light leakage current.

The present invention also provides an embodiment of a liquid crystal display including such a TFT array panel.

The present invention also provides an embodiment of a manufacturing method of such a TFT array panel.

According to the present invention, there is provided a TFT array panel, comprising: a transistor structure having a gate line and a data line crossing the gate line, the structure comprising: a gate electrode formed by the gate line on an insulating substrate; a semiconductor layer , formed on and insulated from the gate electrode; a light blocking layer, formed around the gate electrode and overlapping with at least a part of the gate electrode; a source electrode, formed of a data line, and overlapping with at least a part of the semiconductor layer; a drain electrode, overlapping with at least a part of the semiconductor layer; The source electrode is opposite to the gate electrode and overlaps at least a portion of the semiconductor layer; and the TFT array panel includes a pixel electrode formed over and insulated from the transistor structure and electrically connected to the drain electrode.

According to another aspect of the present invention, a liquid crystal display is provided, including a TFT array panel and a color filter panel, the TFT array panel includes: a gate electrode formed on an insulating substrate; a semiconductor layer formed on the gate electrode, and insulated, and completely overlapped therewith; a light blocking layer, formed on the same layer as the semiconductor layer, and overlapped with at least a portion of the gate electrode along the edge of the gate electrode; a source electrode, overlapped with at least a portion of the semiconductor layer; a drain electrode, overlapped with the source an electrode opposing a gate electrode, and overlapping at least a portion of the semiconductor layer, wherein a transistor structure is formed by the gate electrode, the semiconductor layer, a light blocking layer, a source electrode, and a drain electrode; and a pixel electrode formed over and in contact with the transistor structure Insulated and electrically connected to the drain electrode, and the color filter panel includes: a color filter and a common electrode, the color filter panel is opposite to the TFT array panel on the insulating substrate and faces the TFT array panel.

According to other aspects of the present invention, there is provided a method for manufacturing a TFT array panel, comprising: forming a gate line on an insulating substrate, the gate line including a gate electrode; forming a semiconductor layer insulated thereon on the gate electrode; A light blocking layer is formed around and overlaps with at least a part of the gate electrode; a data line intersecting with the gate line is formed, wherein the data line includes a source electrode, and the source electrode overlaps with at least a part of the semiconductor layer; a drain electrode is formed, and the drain electrode and the source electrode are connected to the gate electrode The electrodes are opposite, wherein the drain electrode overlaps with at least a part of the semiconductor layer; wherein the transistor structure is formed by the gate electrode, the semiconductor layer, the light blocking layer, the source electrode and the drain electrode, and a pixel electrode insulated therefrom is formed on the transistor structure, The pixel electrode is electrically connected to the drain electrode.

Description of drawings

The above and other features and advantages of the present invention will be apparent by describing in detail exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which:

1A is a circuit diagram of a thin film transistor (TFT) array panel according to an embodiment of the present invention;

Fig. 1B is the cross-sectional view of the TFT array panel of Fig. 1A along the line Ib-Ib';

1C is a sectional view of the TFT array panel of FIG. 1A along the line Ic-Ic', and a color filter panel is placed thereon, showing a liquid crystal display according to an embodiment of the present invention;

2 is a circuit diagram of a TFT array panel according to another embodiment of the present invention;

3 is a circuit diagram of a TFT array panel according to another embodiment of the present invention;

4 is a circuit diagram of a TFT array panel according to another embodiment of the present invention; and

FIG. 5 is a circuit diagram of a TFT array panel according to another embodiment of the present invention.

Detailed ways

Throughout the specification, the same reference numerals denote the same elements.

Referring now to FIGS. 1A to 1C , a thin film transistor (TFT) array panel of a liquid crystal display (LCD) according to an embodiment of the present invention will be described. 1A is a circuit diagram of a thin film transistor (TFT) array panel according to an embodiment of the present invention, FIG. 1B is a sectional view along line Ib-Ib' of FIG. 1A , and FIG. 1C is a sectional view along line Ic-Ic' of FIG. 1A The figure shows a liquid crystal display with a color filter panel placed on a TFT array panel. First, a TFT array panel of a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B. Then, referring to FIG. 1C, a liquid crystal display including a TFT array panel will be described.

Referring to FIGS. 1A and 1B , gate lines 22 , 24 and 26 are formed on an insulating substrate 10 . Here, the gate lines 22, 24, and 26 may be made of conductive metals, including but not limited to: aluminum (Al)-based metals, including aluminum and aluminum alloys; silver (Ag)-based metals, including silver and silver alloys; copper (Cu)-based metals, copper-clad and copper alloys; molybdenum (Mo)-based metals, including molybdenum and molybdenum alloys; and conductive metals also include but are not limited to chromium (Cr), titanium (Ti), or tantalum (Ta ). The gate lines 22, 24, and 26 may have a multilayer structure formed of two conductive layers (not shown) having different physical properties. One of the two conductive layers may be made of a low-resistivity metal such as aluminum-based metal, silver-based metal, or copper-based metal to reduce signal delay or voltage drop of the gate lines 22 , 24 and 26 . The other conductive layer can be made of a material having excellent contact properties with ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), such as molybdenum-based metals, chromium, titanium or tantalum. For example, the gate lines 22, 24, and 26 may have a composite structure, such as including a lower layer of chromium and an upper layer of aluminum, or a lower layer of aluminum and an upper layer of molybdenum. However, the present invention is not limited to the above examples. That is, gate lines 22, 24, and 26 may be made of any suitable conductive material.

The gate lines 22, 24 and 26 include: a gate line 22 extending along the row direction; a gate line terminal 24 connected to the end of the gate line 22, receiving a gate signal from the outside, and transmitting the received gate signal to the gate line 22 ; and a gate electrode 26 connected to the gate line 22 . Gate lines 22 extending mainly in the row direction transmit gate signals to the pixels. The gate line terminal 24 may have a large area suitable for connection with an external circuit. The gate lines 22, 24 and 26 are covered with a gate insulating layer 30 made of silicon nitride (SiNx) or similar insulating material. An island-shaped semiconductor layer 40 made of a semiconductor such as hydrogenated amorphous silicon or polycrystalline silicon is formed over the gate insulating layer 30 of the gate electrode 26 . The semiconductor layer 40 may completely overlap the gate electrode 26 to prevent light from a backlight located at the back of the TFT array panel from directly incident on the semiconductor layer 40 . The shape of the semiconductor layer 40 can be variously changed.

A light blocking layer is also formed on the gate insulating layer 30 on the same layer as the semiconductor layer 40 . After the light emitted from the backlight is incident around the gate electrode 26 at a predetermined incident angle, the light is reflected from a common electrode (not shown) of a color filter panel (not shown), and then is incident into the semiconductor layer 40 . The light blocking layer serves to prevent light from being incident into the semiconductor layer 40 . Accordingly, the light blocking layer may overlap at least a portion of the gate electrode 26 along the edges of the gate electrode 26 . When the light blocking layer overlaps the gate electrode 26 along the edge of the gate electrode 26 , it can effectively prevent light passing through the periphery of the gate electrode 26 at a predetermined incident angle from entering the semiconductor layer 40 . Preferably, the overlap area between the light blocking layer and the gate electrode 26 is small enough to minimize parasitic capacitance. In this way, the light blocking layer is aligned along the edge of the gate electrode 26 to minimize parasitic capacitance. However, when process margin is considered, the overlapping width between the light blocking layer and the gate electrode 26 may be about 3 μm or less. The light blocking layer may be made of a material capable of effectively absorbing light. For example, the light blocking layer may be made of substantially the same material as the semiconductor layer 40 .

In this embodiment, the light blocking layer may consist of a plurality of light blocking sub-layers insulated from each other. Here, the light-blocking sublayer includes a first light-blocking layer 91, a second light-blocking layer 92, a third light-blocking layer 93 and a fourth light-blocking layer respectively surrounding the upper, left, right and lower sides of the gate electrode 26. 94. The light blocking sublayers 91, 92, 93, and 94 are island-shaped and insulated from each other. The embodiment shown has four light blocking sub-layers 91, 92, 93 and 94 to avoid light leakage current, however the invention is not limited thereto. One or more of the light blocking sublayers 91, 92, 93, and 94 may be used as long as light leakage current can be effectively avoided. However, when the light blocking sub-layers 91 , 92 , 93 and 94 are conductive, they may be arranged to avoid a short circuit between the source electrode 65 and the drain electrode 66 . That is, the light blocking sublayers 91 , 92 , 93 and 94 may overlap the source electrode 65 or the drain electrode 66 . It is preferable that the first and fourth light blocking sublayers 91 and 94 do not overlap the source electrode 65 and the drain electrode 66 in order to effectively transmit the data signal to the pixel. The shapes of the light blocking sublayers 91, 92, 93, and 94 are not limited to the above examples, and may be variously changed.

Ohmic contact layers 55 and 56 are formed as a pair on the semiconductor layer 40, and they may be made of silicide or n+ hydrogenated amorphous silicon doped with a high concentration of n-type impurities. Data lines 62 , 65 , 66 and 68 are formed over the ohmic contact layers 55 and 56 and the gate insulating layer 30 . Data lines 62, 65, 66 and 68 include: data lines 62 extending along the column direction and intersecting with gate lines 22 to define pixels; source electrodes 65 connected to data lines 62 and on ohmic contact layer 55 extension; a data line terminal 68, connected to the end of the data line 62, and receives an image signal from the outside; and a drain electrode 66, separated from the source electrode 65, and formed on the ohmic contact layer 56 to be connected to the source electrode 65 with respect to the gate electrode 26 relative. The data line terminal 68, which is the end of the data line 62, may be sufficiently wide to be connected to an external circuit. Data lines 62, 65, 66 and 68 may be made of refractory metals such as, but not limited to, chromium, molybdenum-based metals, tantalum, titanium. The data lines 62, 65, 66, and 68 may have a multilayer structure consisting of a lower layer (not shown) of a refractory metal and an upper layer (not shown) of a low-resistivity material formed on the lower layer. For example, the data lines 62, 65, 66, and 68 may have a double-layer structure consisting of a lower layer of chromium and an upper layer of aluminum, or the above-mentioned double-layer structure of a lower layer of aluminum and an upper layer of molybdenum, or a layer of molybdenum and aluminum. and molybdenum layer composed of a three-layer structure. The source electrode 65 overlaps at least a part of the semiconductor layer 40 . The drain electrode 66 is opposed to the source electrode 65 with respect to the gate electrode 26 , and overlaps at least a part of the semiconductor layer 40 . Ohmic contact layers 55 and 56 are interposed between the lower semiconductor layer 40 and the upper source and drain electrodes 65 and 66 to reduce contact resistance. The light blocking sublayers 91 , 92 , 93 and 94 may overlap the source electrode 65 or the drain electrode 66 . However, it is preferable that the overlapping area between the light blocking sublayers 91, 92, 93 and 94 and the source electrode 65 or the drain electrode 66 is small enough to efficiently transmit the data signals applied to the data lines 62, 65, 66 and 68. , and reduce parasitic capacitance. That is, the first light blocking layer 91 and the fourth light blocking layer 94 may not overlap with the source electrode 65 and the drain electrode 66, while the second light blocking layer 92 and the third light blocking layer 93 overlap with the drain electrode 66 and the source electrode 65 respectively. overlapping. Although it is not desirable that each light blocking layer overlaps both the source electrode 65 and the drain electrode 66 , each light blocking layer may overlap a predetermined portion of the source electrode 65 or the drain electrode 66 .

A passivation layer 70 is formed on the data lines 62, 65, 66, and 68 and exposed portions of the semiconductor layer 40 therein. The passivation layer 70 may be: an inorganic layer made of silicon nitride (SiNx) or silicon oxide; a low dielectric chemical vapor deposition (CVD) layer deposited by plasma enhanced CVD (PECVD), such as a-Si:C :O or a-Si:O:F layer; or an acrylic organic insulating layer with excellent planarization properties and photosensitivity. Low dielectric CVD layers such as a-Si:C:O or a-Si:O:F layers deposited by PECVD typically have a very low dielectric constant, i.e. about 4 or less, and are best at Between about 2 and about 4. Therefore, parasitic capacitance can be minimized even when the low-dielectric CVD layer is thin. In addition, low-k CVD layers can exhibit excellent adhesion to another layer and step overlay. Furthermore, since the low-dielectric CVD layer is an inorganic CVD layer, it tends to exhibit excellent heat resistance compared with an organic insulating layer. In addition, the deposition rate and etch rate of the low-k CVD layer can be about 4 to about 10 times that of the silicon nitride layer, thus significantly reducing processing time. For example, the passivation layer 70 may have a double-layer structure composed of an inorganic lower layer and an organic upper layer to protect the exposed portion of the semiconductor layer 40 while maintaining desired characteristics of the organic layer. Contact holes 76 and 78 are formed in the passivation layer 70 to expose the drain electrode 66 and the data line terminal 68, respectively. The passivation layer 70 is formed together with the gate insulating layer 30 to have a contact hole 74 to expose the gate line terminal 24 . At this time, contact holes 74 and 78 may be formed to expose the gate electrical terminal 24 and the data line terminal 68 . Holes 74 and 78 may be provided in various shapes, such as square or circular. The width of the contact holes 74 and 78 can be enlarged to connect with external circuits. A pixel electrode 82 is formed on the passivation layer 70 so as to be electrically connected to the drain electrode 66 via the contact hole 76 and to be located in the pixel region. In addition, an auxiliary gate line terminal 86 and an auxiliary data line terminal 88 are formed on the passivation layer 70 to be connected to the gate line terminal 24 and the data line terminal 68 via the contact holes 74 and 78, respectively. Here, the pixel electrode 82 and the auxiliary gate and data line terminals 86 and 88 may be made of, for example, a light-transmitting conductor such as ITO or IZO or a reflective conductor such as aluminum.

As shown in FIGS. 1A and 1B, by overlapping the pixel electrode 82 with the gate line 22, a storage capacitor can be formed. When the holding capacity is insufficient, additional lines for holding the capacity may be formed on the same layer as the gate lines 22 , 24 and 26 . The pixel electrodes 82 may also overlap the data lines 62 to maximize the pixel aperture ratio. Even when the pixel electrode 82 overlaps with the data line 62 so that the aperture ratio of the pixel is maximized, due to the low dielectric constant of the passivation layer 70, the gap formed between the pixel electrode 82 and the data line 62 can be substantially reduced. parasitic capacitance. In order to improve side visibility, the pixel electrode 82 may include a plurality of cutouts or protrusions formed in a direction oblique to the gate line 22 .

Next, a method of manufacturing a TFT array panel of a liquid crystal display according to an embodiment of the present invention will be described with reference to FIGS. 1A and 1B . First, a multilayer metal film (not shown) for gate lines is deposited on the substrate 10 and patterned to form gate lines 22, 24 and 26 extending along the row direction, including gate lines 22, Gate electrode 26 and gate line terminal 24 . Then, a gate insulating layer 30 , an amorphous silicon layer (not shown) for a semiconductor layer, and a doped amorphous silicon layer are sequentially deposited on the substrate 10 . Exemplary layer 30 may be made of silicon nitride. The amorphous silicon layer and the doped amorphous silicon layer are subjected to photolithography, thereby forming an island-shaped semiconductor layer 40 on the gate insulating layer 30 of the gate electrode 26, and forming light blocking sub-layers 91, 92 around the gate electrode 26 , 93 and 94 overlap at least a portion of the gate electrode 26 and form a doped amorphous silicon layer pattern (not shown) on the semiconductor layer 40 . A data metal layer (not shown) is deposited on the resulting structure and patterned by photolithography using a mask to form data lines 62, 65, 66 and 68 such that data line 62 intersects gate line 22; Electrode 65 is connected to data line 62 and extends over gate electrode 26 ; data line terminal 68 is connected to the end of data line 62 ; Then, portions of the amorphous silicon layer pattern exposed by the data lines 62 , 65 , 66 and 68 are etched to form ohmic contact layer patterns 55 and 56 which are separated from each other with respect to the gate electrode 26 . At this time, the semiconductor layer 40 between the ohmic contact layer patterns 55 and 56 is exposed. In order to stabilize the exposed surface of the semiconductor layer 40, oxygen plasma treatment may be performed. The passivation layer 70 is formed by CVD growth of a silicon nitride layer, an a-Si:C:O layer or an a-Si:O:F layer. The passivation layer 70 may also be formed by oxidizing the insulating layer coating. Then, patterning is performed on the gate insulating layer 30 and the passivation layer 70 by photolithography to form contact holes 74 , 76 and 78 to expose the gate line terminal 24 , the drain electrode 66 and the data line terminal 68 . For example, the contact holes 74, 76, and 78 may be formed in a square shape or a circle shape. Then, deposit ITO or IZO layer, carry out photolithography step afterwards, to form the pixel electrode 82 that is connected with drain electrode 66 through contact hole 76, and through contact hole 74 and 78 and gate line terminal 24 and data line terminal respectively. 68 connected to the auxiliary gate line terminal 86 and the auxiliary data line terminal 88 . Nitrogen preheating may be performed prior to deposition of the ITO or IZO layer to avoid formation of metal oxide layers on exposed surfaces of gate line terminal 24, drain electrode 66, and data line terminal 68 through contact holes 74, 76, and 78, respectively.

Next, referring to FIG. 1C, an operation for avoiding light leakage current in a liquid crystal display according to an embodiment of the present invention will be described. Referring to FIG. 1C, a color filter panel is placed opposite to the TFT array panel. The color filter panel includes an insulating substrate 110 made of transparent glass or the like, a black matrix 120 formed on the insulating substrate 10 to avoid light leakage, a red-green-blue (RGB) color filter 130, and a light-transmitting substrate made of, for example, ITO or IZO. The common electrode 140 is made of conductive material. Here, the black matrix 120 may be composed of black matrix portions corresponding to gate lines (see 22 of FIG. 1A ), data lines (see 62 of FIG. 1A ), and pixel electrodes 82 . The black matrix 120 may be formed in various shapes to avoid light leakage that may occur at or around the pixel electrode 82 . To improve side visibility, the common electrode 140 may include a plurality of cutouts or protrusions formed in a direction inclined with respect to the gate lines.

The liquid crystal display according to the embodiment of the present invention shown in FIG. 1C includes a color filter panel, a TFT array panel opposite to the color filter panel, and a liquid crystal layer 200 interposed therebetween. When a voltage is applied across the pixel electrodes 82 of the TFT array panel and the common electrode 140 of the color filter panel, the liquid crystal display displays images by rearranging liquid crystal molecules of the liquid crystal layer 200 to adjust the amount of light transmitted therethrough. Generally, an optical leakage current of a liquid crystal display is generated by light emitted from a backlight (see A1 and A2 of FIG. 1C ) and light incident from the outside (see B1 of FIG. 1C ). The liquid crystal display according to the embodiment of the present invention shown in FIGS. 1A to 1C uses a gate electrode 26 and light blocking sublayers 91 , 92 , 93 and 94 to minimize light leakage current. That is, the semiconductor layer 40 completely overlaps the gate electrode 26 to prevent the light beam A2 emitted from the backlight from being directly incident on the semiconductor layer 40 . Regarding this, it is preferable that the width Wg of the gate electrode 26 is much larger than the width Wa of the semiconductor layer 40 . In the absence of the light blocking sublayers 91, 92, 93, and 94, after being emitted from the backlight and incident around the grid electrode 26 at a predetermined incident angle, the light beam A1 is reflected from the common electrode 140 of the color filter panel, and then incident on the semiconductor layer 40. However, according to the present invention, the light blocking sublayers 91 , 92 , 93 and 94 overlapping the gate electrode 26 along the edges of the gate electrode 26 can minimize the light leakage current by absorbing the light beam A1 . In this regard, in order to effectively prevent the light beam A1 from being incident on the periphery of the gate electrode 26 , the light blocking sublayers 91 , 92 , 93 and 94 may overlap at least a portion of the gate electrode 26 . For example, the overlapping width Wo between each of the light blocking sublayers 91, 92, 93, and 94 and the gate electrode 26 may be about 3 μm or less.

In the absence of the light blocking sublayers 91, 92, 93, and 94, the external light beam B1 incident on the periphery of the black matrix 120 at a predetermined incident angle may be sequentially reflected from the gate electrode 26 and the common electrode 140, and then incident on the semiconductor layer. 40 on. However, by disposing the light blocking sublayers 91, 92, 93 and 94 to overlap the gate electrode 26 along the edges of the gate electrode 26, by absorbing the light beam B1 before it is reflected from the gate electrode 26, the light leakage current can be made minimize.

In this regard, as the width Wb of the light blocking sublayers 91, 92, 93, and 94 increases, light leakage current can be minimized. However, in order to avoid reducing the aperture ratio of the pixel, it is preferable to form the light blocking sublayers 91, 92, 93, and 94 to have a width of about 10 [mu]m or less. More preferably, the light blocking sub-layers 91 , 92 , 93 and 94 may have a width between about 4 μm to about 8 μm.

Next, a TFT array panel according to an embodiment of the present invention will be described with reference to FIGS. 2 to 5 . For ease of illustration, the same constituent elements as in the embodiment shown in FIGS. 1A to 1C are denoted by the same reference numerals, and thus detailed descriptions thereof are omitted. FIG. 2 is a circuit diagram of a TFT array panel according to another embodiment of the present invention. The TFT array panel shown in FIG. 2 may have substantially the same structure as the embodiment shown in FIGS. 1A to 1C , but may also have an optional structure as shown below. Referring to FIG. 2 , the light blocking layer 9124 extends along the upper, left, and lower sides of the gate electrode 26 , while the light blocking layer 93 is located on the right side of the gate electrode 26 . FIG. 3 is a circuit diagram of a TFT array panel according to another embodiment of the present invention. The TFT array panel shown in FIG. 3 may have substantially the same structure as the embodiment shown in FIGS. 1A to 1C , but may also have an optional structure as shown below. Referring to FIG. 3 , the light blocking layer 9134 extends along the upper, right, and lower sides of the gate electrode 26 , while the light blocking layer 92 is located on the left side of the gate electrode 26 . FIG. 4 is a circuit diagram of a TFT array panel according to another embodiment of the present invention. The TFT array panel shown in FIG. 4 may have substantially the same structure as the embodiment shown in FIGS. 1A to 1C , but may also have an optional structure as shown below. Referring to FIG. 4 , the light blocking layer 912 extends along the upper and left sides of the gate electrode 26 , and the light blocking layer 934 extends along the lower and right sides of the gate electrode 26 . FIG. 5 is a circuit diagram of a TFT array panel according to another embodiment of the present invention. The TFT array panel shown in FIG. 5 may have substantially the same structure as the embodiment shown in FIGS. 1A to 1C , but may also have an optional structure as shown below. Referring to FIG. 5 , the light blocking layer 913 extends along the upper and right sides of the gate electrode 26 , and the light blocking layer 924 extends along the lower and left sides of the gate electrode 26 . That is, the above-mentioned light blocking sublayers 91, 92, 93, 94, 9134, 912, 934, 913, and 924 may overlap at least a part of the gate electrode 26, and may be formed in various shapes as long as there is a gap between the source electrode and the drain electrode. No short circuit will occur.

As described above, in the manufacturing method of the TFT array panel, the liquid crystal display including it, and the TFT array panel according to the present invention, the light leakage current can be effectively minimized, thereby improving display characteristics, such as increasing contrast, or reducing image flicker .

Although the present invention has been described with reference to exemplary embodiments thereof, it will be apparent to those skilled in the art that various modifications and changes can be made without departing from the scope and spirit of the invention. Therefore, it should be understood that the above embodiments are not limiting, but demonstrations of various aspects.

Claims (30)

1. thin-film transistor tft array panel comprises:

Transistor arrangement, the data wire that has gate line and intersect with gate line, this transistor arrangement comprises:

Gate electrode is formed by gate line on insulated substrate,

Gate insulator is formed on gate electrode and the insulated substrate,

Semiconductor layer directly forms on gate insulator also and gate electrode,

Photoresist layer, be formed on gate electrode around and with at least a portion gate electrode, this photoresist layer directly forms on gate insulator,

The source electrode is formed by data wire, and overlapping with at least a portion semiconductor layer, and

Drain electrode, relative with the source electrode about gate electrode, and overlapping with at least a portion semiconductor layer, and

Pixel capacitors is formed on the transistor arrangement and insulation with it, and is electrically connected with drain electrode.

2. tft array panel according to claim 1, wherein, photoresist layer is positioned on the layer identical with semiconductor layer.

3. tft array panel according to claim 2, wherein, photoresist layer comprises and the semiconductor layer identical materials.

4. tft array panel according to claim 1, wherein, photoresist layer comprises light absorbing material.

5. tft array panel according to claim 4, wherein, photoresist layer comprises amorphous silicon.

6. tft array panel according to claim 1, wherein, photoresist layer is neither not overlapping with drain electrode with the source electrode yet.

7. tft array panel according to claim 1, wherein, photoresist layer and one of source electrode and drain electrode are overlapping.

8. tft array panel according to claim 1, wherein, semiconductor layer and gate electrode are overlapping fully.

9. tft array panel according to claim 1, wherein, photoresist layer comprises a plurality of light blockings sublayer, wherein separate with other light blocking sublayers each light blocking sublayer.

10. tft array panel according to claim 1, wherein, the overlapping width between gate electrode and the photoresist layer is 3 μ m or still less.

11. tft array panel according to claim 1, wherein, photoresist layer has 10 μ m or littler width.

12. a LCD LCD comprises:

Thin-film transistor tft array panel comprises transistor arrangement and pixel capacitors, and transistor arrangement has: gate electrode is formed on the insulated substrate; Gate insulator is formed on gate electrode and the insulated substrate; Semiconductor layer directly forms on gate insulator also and gate electrode, and semiconductor layer and gate electrode are overlapping fully; Photoresist layer is formed on identical with the semiconductor layer layer, and along edge and at least a portion gate electrode of gate electrode, wherein this photoresist layer directly forms on gate insulator; The source electrode, overlapping with at least a portion semiconductor layer; Drain electrode, relative with the source electrode about gate electrode, and overlapping with at least a portion semiconductor layer, and pixel capacitors is formed on the transistor arrangement and insulation with it, and be electrically connected with drain electrode; And

Color filter panel comprises filter and public electrode, and color filter panel and tft array panel are relatively also in the face of the tft array panel.

13. LCD according to claim 12, wherein, photoresist layer comprises and the semiconductor layer identical materials.

14. LCD according to claim 12, wherein, photoresist layer comprises light absorbing material.

15. LCD according to claim 14, wherein, photoresist layer comprises amorphous silicon.

16. LCD according to claim 12, wherein, photoresist layer is neither not overlapping with drain electrode with the source electrode yet.

17. LCD according to claim 12, wherein, photoresist layer and one of source electrode and drain electrode are overlapping.

18. LCD according to claim 12, wherein, photoresist layer comprises a plurality of light blockings sublayer, and wherein separate with other light blocking sublayers each light blocking sublayer.

19. LCD according to claim 12, wherein, the overlapping width between gate electrode and the photoresist layer is 3 μ m or still less.

20. LCD according to claim 12, wherein, photoresist layer has 10 μ m or littler width.

21. a method of making thin-film transistor tft array panel comprises:

On insulated substrate, form gate line, wherein gate line comprises gate electrode;

On gate electrode and insulated substrate, form gate insulator;

Directly on gate insulator, form semiconductor layer, semiconductor layer and gate electrode;

Around gate electrode, directly on gate insulator, form photoresist layer, wherein photoresist layer and at least a portion gate electrode;

Form the data wire that intersects with gate line, wherein data wire comprises the source electrode, and source electrode and at least a portion semiconductor layer are overlapping;

Form drain electrode, drain electrode is relative about gate electrode with the source electrode, and wherein drain electrode and at least a portion semiconductor layer are overlapping, wherein, form transistor arrangement by gate electrode, semiconductor layer, photoresist layer, source electrode and drain electrode; And

On transistor arrangement, form the pixel capacitors of insulation with it, wherein, pixel capacitors is electrically connected with drain electrode.

22. method according to claim 21, wherein, photoresist layer comprises and the semiconductor layer identical materials.

23. method according to claim 21, wherein, photoresist layer comprises light absorbing material.

24. method according to claim 23, wherein, photoresist layer comprises amorphous silicon.

25. method according to claim 21, wherein, photoresist layer is neither not overlapping with drain electrode with the source electrode yet.

26. method according to claim 21, wherein, photoresist layer and one of source electrode and drain electrode are overlapping.

27. method according to claim 21, wherein, semiconductor layer and gate electrode are overlapping fully.

28. method according to claim 21, wherein, photoresist layer comprises a plurality of light blockings sublayer, and wherein separate with other light blocking sublayers each light blocking sublayer.

29. method according to claim 21, wherein, the overlapping width between gate electrode and the photoresist layer is 3 μ m or still less.

30. method according to claim 21, wherein, photoresist layer has 10 μ m or littler width.

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