CN1845341A - Thin film transistor and method of fabricating the same - Google Patents

Abstract

A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a middle part and two side parts of the middle part; a gate on the middle part; and a source on the two side parts and separated from the source open drain, where the source and drain are electrically connected to the silicon nanowires, respectively.

Description

Thin film transistor and manufacturing method thereof

This application claims the benefit of Application No. 10-2005-0029120 filed in Korea on April 7, 2005, the entire contents of which are incorporated herein by reference.

technical field

The present invention relates to a flat panel display (FPD), in particular to a thin film transistor (TFT) for the FPD and a manufacturing method thereof.

Background technique

Generally, the FPD includes a liquid crystal display (LCD) device, a plasma display panel (PDP), an organic electroluminescent display device (OLED), and the like. Here, TFTs are used as switching elements or driving elements of the FPD.

FIG. 1 shows the structure of an LCD according to the prior art.

In FIG. 1, the LCD 3 includes upper and lower substrates 5 and 22 facing each other and a liquid crystal layer 11 between the upper and lower substrates 5 and 22.

Gate lines 12 and data lines 24 crossing the gate lines 12 are formed on the lower substrate 22 to define a pixel region P. Referring to FIG. The TFT T is disposed at a position adjacent to the intersection of the gate line 12 and the data line 24, and the pixel electrode 17 is connected to the TFT T and disposed in the pixel region P. The pixel electrode 17 includes a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

The TFT T comprises a gate 30 connected to the gate line 12, a source 34 connected to the data line 24, a drain 36 separated from the source 34, and between the source 34 and the gate 30 and at the drain. 36 and the semiconductor layer 32 between the gate 30.

Here, the gate line 12 supplies the scan signal from the first external circuit to the gate 30 , and the data line 24 supplies the data signal from the second external circuit to the source 34 .

In addition, red, green, and blue sub-color filters 7a, 7b, and 7c are formed on the upper substrate 5, wherein each of the red, green, and blue sub-color filters 7a, 7b, and 7c is repeatedly arranged at a position corresponding to the pixel region P. in the area. A black matrix 6 is formed in intermediate spaces between red, green and blue sub-color filters 7a, 7b and 7c. Generally, a common electrode 9 is formed on the red, green and blue sub-color filters 7 a , 7 b and 7 c and the black matrix 6 .

The liquid crystal molecules of the liquid crystal layer 11 have anisotropic dielectric constant and anisotropic refractive index characteristics due to their long and thin shape. In addition, for example, two electric field generating electrodes are respectively formed on the two substrates. Therefore, the orientation of the liquid crystal molecules can be controlled by applying a voltage to the two electrodes. The light transmittance of the LCD panel is thereby changed according to the polarization characteristics of the liquid crystal material.

TFTs can have different configurations. Typically, an inverted staggered type TFT of amorphous silicon or a top gate type TFT of polysilicon is used.

FIG. 2 shows a schematic cross-sectional view of an inverted staggered TFT according to the prior art.

In FIG. 2, the inverted staggered TFT T includes a gate electrode 52 on a substrate 50, a gate insulating layer 54 on the entire surface of the substrate 50 having the gate electrode 52, an active layer on the gate insulating layer 54 above the gate electrode 52. 56 , and the ohmic contact layer 58 on the active layer 56 . Here, the ohmic contact layer 58 has an opening portion 59 exposing a middle portion of the active layer 56 . A source 60 and a drain 62 are formed on the ohmic contact layer 58 . The source electrode 60 and the drain electrode 62 are separated from each other by the opening portion 59 . Essentially, the opening portion 59 defines a channel portion (not shown) of the TFT T.

In addition, a passivation layer 64 is formed on the TFT T. The passivation layer 64 has a drain contact hole 66 exposing a portion of the drain electrode 62 . A pixel electrode 68 is formed on the passivation layer 64 and connected to the drain electrode 62 via the drain contact hole 66 .

Hereinafter, the manufacturing process of the reverse staggered TFT will be described with reference to the drawings.

3A to 3E show schematic cross-sectional views of an array substrate including reverse-staggered TFTs according to a manufacturing process of the prior art.

As shown in FIG. 3A, a gate 52 is formed on a substrate 50 by depositing and patterning a conductive material such as aluminum (Al), Al alloy, copper, tungsten (W), or molybdenum (Mo).

Then, a gate insulating layer 54 is formed by depositing an inorganic insulating material such as silicon nitride or silicon dioxide on the substrate 50 formed with the gate electrode 52 .

As shown in FIG. 3B , amorphous silicon and doped amorphous silicon layers are deposited on gate insulating layer 54 and patterned into active layer 56 and ohmic contact layer 58 , respectively. For example, amorphous silicon is deposited by plasma enhanced chemical vapor deposition (PECVD) after decomposing silane gas (SiH ₄ ) with radio frequency (RF) energy. Forming doped amorphous silicon includes preparing a chamber (not shown) in which a substrate 50 on which amorphous silicon is formed, and injecting, for example, silane (SiH ₄ ), hydrogen diluent gas, phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) dopant gas is injected into the chamber. Here, when the gas pressure reaches a predetermined value, impurities such as phosphorus (P) or boron (B) may be doped into amorphous silicon as a dopant by supplying RF energy in the chamber.

The active layer 56 and the ohmic contact layer 58 having a predetermined pattern may be formed by performing a mask process for patterning the amorphous silicon layer and the doped amorphous silicon layer.

As shown in FIG. 3C , source and drain electrodes 60 and 62 are formed by depositing and patterning a conductive material, eg, the same material as the gate material, on ohmic contact layer 58 . Here, the source and drain electrodes 60 and 62 are separated from each other by the opening portion 59 exposing a portion of the ohmic contact layer 58 .

Subsequently, a portion of the ohmic contact layer 58 corresponding to the opening portion 59 is removed, and a portion of the active layer 56 corresponding to the opening portion 59 is exposed. The exposed portion of active layer 56 is defined as a channel region (not shown).

The active layer 56 and the ohmic contact layer 58 form a semiconductor layer 57 .

By employing the above-described processes, a TFT T including the gate electrode 52, the semiconductor layer 57, and the source and drain electrodes 60 and 62 can be formed.

As shown in FIG. 3D, on the substrate formed with the source and drain electrodes 60 and 62, by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or by coating such as benzocyclobutene ( BCB) or an organic insulating layer of acrylic resin forms the passivation layer 64 .

Then, a drain contact hole 66 is formed by patterning the passivation layer 64 , wherein the drain contact hole 66 exposes part of the drain electrode 62 .

As shown in FIG. 3E , a pixel electrode 68 is formed on the passivation layer 64 by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Here, the pixel electrode 68 is connected to the drain electrode 62 via the drain contact hole 66 .

Although the semiconductor layer 57 of the inverted staggered TFT T includes amorphous silicon, in practice, amorphous silicon is not suitable for a large-sized LCD. This is because amorphous silicon has low mobility of electrons and holes.

As a means of solving the problem, a top gate type TFT using polysilicon having a higher mobility than amorphous silicon has been suggested.

FIG. 4 shows a schematic cross-sectional view of a top-gate TFT according to the prior art.

In FIG. 4 , the top-gate TFT T includes an active layer 72 of polysilicon on a substrate 70, an ohmic contact layer 74 on the active layer 72 with an opening 73 that exposes the middle part of the active layer 72, and an ohmic contact layer 74 through the opening. 73 and a source 76 and a drain 78 separated from each other.

The opening portion 73 defines a channel region (not shown). A gate insulating layer 80 is formed on the entire surface of the substrate 70 where the active layer 72 , the ohmic contact layer 74 and the opening portion 73 are formed. The gate electrode 82 is formed on the gate insulating layer 80 to be disposed at a position corresponding to the opening portion 73 . A passivation layer 84 is formed on the gate 82 and has a drain contact hole 85 exposing a portion of the drain 78 . A pixel electrode 86 is formed on the passivation layer 84 and connected to the drain electrode 78 via the drain contact hole 85 . The active layer 72 is made of polysilicon formed by crystallization of amorphous silicon.

As described above, an inverted staggered type or top gate type TFT is manufactured through complicated processes for forming the active layer 72 and the ohmic contact layer 74 . In addition, forming the array substrate includes forming a TFT T, followed by forming a source electrode 76 and a drain electrode 78, followed by forming a gate line and a data line (not shown) for applying signals to the source electrode 76 and the drain electrode 78, respectively.

Therefore, manufacturing the array substrate increases processing time and manufacturing cost.

In order to solve this problem, a TFT using silicon nanowires has been proposed.

FIG. 5 shows a schematic cross-sectional view of a TFT structure including silicon nanowires according to the prior art.

In FIG. 5, a gate 92 is formed on a substrate 90, a source 98 and a drain 99 are formed on both sides of the gate 92, and silicon nanowires 95 are disposed on the gate 92 to directly contact the source through both sides thereof. 98 and drain 99. Typically, silicon nanowires 95 are formed before source and drain electrodes 98 and 99 are formed.

In order to connect the silicon nanowire 95 with the source electrode 98 and the drain electrode 99, the silicon nanowire 95 such as the crystalline silicon 94 surrounding the silicon nanowire 95 should be removed on both sides of the silicon nanowire 95 before the source electrode 98 and the drain electrode 99 are formed. The insulating layer 96 of the oxide layer.

Therefore, electrical contact instability is caused in part by the following events: the silicon nanowire (95) disposed on the gate (92) and the semiconductor material from the silicon nanowire (95) to the source and drain (98 and 99 ) metal connections. These events lead to unstable device operation.

Contents of the invention

Accordingly, the present invention is directed to a TFT including silicon nanowires and a method of fabricating the same that substantially overcome one or more of the problems due to limitations and disadvantages of the related art.

An advantage of the present invention is to provide a TFT that can operate stably and includes silicon nanowires.

Another advantage of the present invention is to provide a TFT including silicon nanowires that does not interfere with efficient processing.

Still another advantage of the present invention is to provide a method of manufacturing a TFT including silicon nanowires capable of forming a TFT including silicon nanowires through a simpler process than the prior art.

Additional advantages and features of the invention will be set forth in the description which follows, and in part will become apparent to those skilled in the art from the description, or may be learned by practice of the invention. These and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

To achieve these and other advantages, and in accordance with the purposes of the present invention, as specifically and broadly described, a thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a middle portion and two side portions of the middle portion; and a source on each side portion and a drain separated from the source, wherein the source and the drain are electrically connected to the silicon nanowire.

In another aspect of the present invention, an array substrate for a flat panel display device includes: a silicon nanowire on the substrate, the silicon nanowire has a middle part and two side parts of the middle part; a gate on the middle part; A first source on each side portion and a first drain separated from the first source, the first source and the first drain are respectively electrically connected to the silicon nanowire; the first drain connected to the first source two source electrodes and a second drain electrode connected to the first drain electrode; and a pixel electrode connected to the second drain electrode.

In yet another aspect of the present invention, a thin film transistor includes: a silicon nanowire on a substrate, wherein the silicon nanowire has a middle part and two side parts of the middle part; a gate insulating layer on the middle part; a gate insulating layer on the and a source electrode on each side portion and a drain electrode separated from the source electrode, wherein the source electrode and the drain electrode directly contact the silicon nanowire respectively.

In another aspect of the present invention, an array substrate for a flat panel display device includes: a silicon nanowire on the substrate, the silicon nanowire has a middle part and two side parts of the middle part; a gate insulating layer on the middle part ; a gate located on the gate insulating layer; a first source located on each side portion and a first drain separated from the first source, the first source and the first drain directly contacting the silicon nanowire respectively ; a second source connected to the first source and a second drain connected to the first drain; and a pixel electrode connected to the second drain.

In another aspect of the present invention, a manufacturing method of a thin film transistor includes: disposing a silicon nanowire on a substrate, the silicon nanowire having a middle part and two side parts of the middle part; forming a gate on the middle part; A source and a drain separated from the source are formed on the side portion, and the source and the drain are respectively electrically connected to the silicon nanowire.

In yet another aspect of the present invention, a method for manufacturing an array substrate for a flat panel display device includes: disposing silicon nanowires on the substrate, the silicon nanowires having a middle part and two side parts of the middle part; gate; forming a first source and a first drain separated from the first source on each side portion, wherein the first source and the first drain are respectively electrically connected to the silicon nanowire; forming a connection to the second a second source of a source and a second drain connected to the first drain; and a pixel electrode connected to the second drain is formed.

In yet another aspect of the present invention, a method for manufacturing a thin film transistor includes: coating a solvent comprising silicon nanowires on a substrate, the silicon nanowires having a middle part and two side parts of the middle part; Solvent outside the wire; a gate insulating layer and a gate are sequentially formed on the silicon nanowire on the middle part; and a source and a drain separated from the source are formed on each side part, and the source and the drain are respectively direct contact with silicon nanowires.

In yet another aspect of the present invention, a method for manufacturing an array substrate for a flat panel display device includes: coating a solvent comprising silicon nanowires on the substrate, the silicon nanowires having a middle part and two side parts of the middle part; removing solvents other than silicon nanowires from the substrate; sequentially forming a gate insulating layer and a gate on the middle portion; forming a first source and a first drain separated from the first source on each side portion, The first source and the first drain directly contact the silicon nanowire; and forming a second source connected to the first source and a second drain connected to the first drain; and forming a second drain connected to the second drain pixel electrodes.

It is to be understood that both the foregoing general description and the following detailed description are schematic and explanatory and are intended to provide further explanation of the claims of the present invention.

Description of drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and together with the description serve to explain the principle of the invention.

In the attached picture:

FIG. 1 shows a schematic diagram of the structure of an LCD according to the prior art;

Figure 2 shows a schematic cross-sectional view of an inverted staggered TFT according to the prior art;

3A to 3E respectively show schematic cross-sectional views of an array substrate including reverse-staggered TFTs according to the manufacturing process of the prior art;

4 shows a schematic cross-sectional view of a top-gate TFT according to the prior art;

Figure 5 shows a schematic cross-sectional view of a TFT structure comprising silicon nanowires according to the prior art;

6A to 6E illustrate schematic cross-sectional views of an array substrate having TFTs including silicon nanowires according to a manufacturing process according to a first embodiment of the present invention; and

7A to 7F illustrate schematic cross-sectional views of an array substrate including TFTs having silicon nanowires according to a manufacturing process according to a second embodiment of the present invention.

Detailed ways

Preferred embodiments of the present invention will now be described in detail, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

The first embodiment according to the present invention includes a silicon nanowire as an active layer, and a source and a drain formed of the same material as a gate through the same process.

6A to 6E illustrate schematic cross-sectional views of an array substrate having TFTs including silicon nanowires according to a manufacturing process according to a first embodiment of the present invention.

In FIG. 6A , silicon nanowires 102 are disposed on a substrate 100 . Although not shown, for example, the silicon nanowires 102 are formed by depositing a catalyst on a semiconductor substrate (not shown) and crystallizing the catalyst by using a reaction gas including silicon. The silicon nanowires 102 are sputtered on the substrate 100 after deposition and crystallization on the semiconductor substrate. In addition, the silicon nanowire 102 has a rod shape as shown in FIG. 6A. Although not shown, the silicon nanowire 102 includes a core of semiconductor material and an insulating layer surrounding the core to form a coaxial structure between the core and the insulating layer.

For example, the core is formed by crystallizing a semiconductor material, and the insulating layer is formed by crystallizing one of silica and alumina. Therefore, the core comprises crystalline silicon. In addition, the silicon nanowire 102 may be composed of multiple silicon nanowires.

Then, the fixed layer 104 is formed by coating an organic insulating material such as benzocyclobutene (BCB) or acrylic resin on the substrate 100 formed with the silicon nanowires 102 . The fixing layer 104 is used to fix the silicon nanowires 102 on the substrate 100 .

In FIG. 6B , first and second contact holes 106 and 108 are formed by etching the fixed layer 104 to expose both side portions of the silicon nanowire 102 . Forming the first and second contact holes 106 and 108 may include removing the insulating layer of the silicon nanowire 102 .

Depending on circumstances, the step of forming the pinned layer may be omitted.

In FIG. 6C, by depositing, for example, aluminum (Al), aluminum alloy, copper, tungsten (W), molybdenum (Mo), titanium (Ti), or chromium ( Cr) conductive metal material forms the first source 110 , the first drain 112 and the gate 114 . Here, the first source 110 and the first drain 112 are connected to the silicon nanowire 102 via the first and second contact holes 106 and 108, respectively, and the gate 114 is disposed on the first source 110 and the first drain 112. in the space between. That is, the first source 110, the gate 114, and the first drain 112 are separated from each other.

In addition, a silicide layer (not shown) may be formed on interfaces between the silicon nanowires 102 and the first source 110 and between the silicon nanowires 102 and the first drain 112 . Therefore, the silicide layer can be used as an ohmic contact layer, thereby omitting an additional step of forming an ohmic contact layer.

The silicon nanowire 102, the gate 114, the first source 110 and the first drain 112 constitute a TFT T. Note that the first source 110 and the first drain 112 are formed through the same process as the gate 114, thereby reducing the number of TFT process steps.

In FIG. 6D , a gate insulating layer 116 is formed by depositing an inorganic insulating material such as silicon nitride or silicon oxide on the substrate 100 having the first source and drain electrodes 110 and 112 and the gate electrode 114 . In addition, third and fourth contact holes 118 and 120 are formed by etching the gate insulating layer 116 to expose portions of the first source and drain electrodes 110 and 112 .

Then, the second source 122 and the second drain 112 are formed by depositing and patterning a conductive metal material such as the same material as the first source 110 and the first drain 112 on the substrate 100 having the first source 110 and the first drain 112. Two drains 124 . Here, the second source 122 is connected to the first source 110 via the third contact hole 118 , and the second drain 124 is connected to the first drain 112 via the fourth contact hole 120 .

Although not shown, a data line integrated with the second source electrode 122 may be formed during the formation of the second source electrode 122 and the second drain electrode 124 .

In FIG. 6E , on the substrate 100 having the second source 122 and the second drain 124 , by depositing and patterning inorganic materials such as silicon nitride or silicon oxide or by coating and patterning such as benzocyclobutene (BCB ) or an organic material of acrylic resin forms the passivation layer 126.

Then, a drain contact hole 128 is formed by etching the passivation layer 126 to expose a portion of the second drain 124 .

The pixel electrode 130 is formed by depositing a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the entire surface of the substrate 100 having the passivation layer 126 . Here, the pixel electrode 130 is connected to the second drain electrode 124 via the drain contact hole 128 .

Through the above-described processes, an array substrate having TFTs made of silicon nanowires 102 and used as switching elements or driving elements was obtained.

The second embodiment is characterized in that silicon nanowires are formed on the substrate by sputtering.

7A to 7F illustrate schematic cross-sectional views of an array substrate including TFTs having silicon nanowires according to a manufacturing process according to a second embodiment of the present invention.

In FIG. 7A , silicon nanowires 202 are disposed on a substrate 200 , for example, a solvent 201 having silicon nanowires 202 and a surfactant (not shown) is prepared, and the solvent 201 may be applied by spraying on the substrate 200 . For example, the silicon nanowires 202 may be formed by depositing a catalyst having a nanoscale size on a semiconductor substrate (not shown) and crystallizing the catalyst using a reaction gas including silicon before preparing the solvent 201 .

Essentially, although not shown, the silicon nanowire 202 includes a core and an insulating layer surrounding the core, thereby forming a coaxial structure between the core and the insulating layer. In addition, the silicon nanowire 202 has a rod shape. In addition, the silicon nanowire 202 is composed of a plurality of silicon nanowires.

In FIG. 7B , through the steps of FIG. 7A , residual solvent (not shown) other than the silicon nanowires 202 is removed from the substrate 200 by heating at a temperature below about 100 degrees Celsius. Here, the heating step may be performed on the entire surface of the substrate 200 . After this step, the silicon nanowires 202 are arranged in a direction parallel to the surface of the substrate 202 .

In FIG. 7C , a fixed layer 204 , a gate insulating layer 206 and a gate 208 are sequentially deposited on the middle portion of the silicon nanowire 202 .

For example, the fixed layer 204 and the gate insulating layer 206 are deposited simultaneously and patterned through the same process. Here, the insulating layer surrounding crystalline silicon in the silicon nanowire 202 may be removed by patterning the fixed layer 204 and the gate insulating layer 206 or by using the gate 208 as an etch stopper after patterning the gate 208 .

For example, the fixing layer 204 is formed of an organic insulating material such as benzocyclobutene (BCB) or acrylic resin and serves to fix the silicon nanowire 202 .

However, the forming process of the fixed layer 204 may be omitted according to specific circumstances.

In FIG. 7D, by depositing and patterning such as aluminum (Al), aluminum alloy, copper, tungsten (W), molybdenum (Mo), titanium (Ti), or chromium (Cr) on the substrate 200 formed with the gate 208 The conductive metal material forms the first source 210 and the first drain 212 . Here, the first source electrode 210 and the first drain electrode 212 are separated from each other by the fixed layer 204 , the gate insulating layer 206 and the gate electrode 208 . Here, the first source 210 and the first drain 212 directly cover the exposed silicon nanowires 202 , so as to be directly connected to a part of the silicon nanowires 202 .

In addition, although not shown, a silicide layer may be formed on the interface between the silicon nanowire 202 and the first source electrode 210 and the interface between the silicon nanowire 202 and the first drain electrode 212 . The silicide layer may serve as an ohmic contact layer with respect to the first source electrode 210 and the first drain electrode 212, and thus, an additional ohmic contact layer is unnecessary.

Using the above process, the silicon nanowire 202, the gate 208, the first source 210 and the first drain 212 constitute a TFT T. Therefore, since the first source electrode 210 and the first drain electrode 212 are formed through the same process as the gate electrode 208, processing time and manufacturing cost of the TFT T can be reduced.

In FIG. 7E, an interlayer insulating film 214 is formed by depositing and patterning an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) on the TFT T-formed substrate 200. Through this step, the interlayer insulating film 214 has first and second contact holes 216 and 218 exposing parts of the first source electrode 210 and the first drain electrode 212, respectively.

Then, the second source 220 and the second drain 222 are formed by depositing and patterning, for example, a conductive metal material of the same material as the first source 210 and the first drain 212 on the substrate 200 formed with the interlayer insulating film 214 . Here, the second source 220 is connected to the first source 210 via the first contact hole 216 , and the second drain 222 is connected to the first drain 216 via the second contact hole 218 .

In FIG. 7F , on the substrate 100 formed with the second source 220 and the second drain 222 , by depositing an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or by coating such as a benzo ring An organic insulating material of butene (BCB) or acrylic resin forms the passivation layer 224 . Here, the passivation layer 224 is patterned to have a drain contact hole 226 exposing a portion of the second drain electrode 222 .

Then, the pixel electrode 228 is formed by depositing and patterning a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) on the passivation layer 224 . Here, the pixel electrode 228 is connected to the second drain electrode 222 via the drain contact hole 226 .

Through the above-described processes, an array substrate including TFTs having silicon nanowires according to the second embodiment can be manufactured.

The TFT according to the present invention is characterized in that silicon nanowires are used instead of a semiconductor layer and the silicon nanowires are fixed and reinforced by a fixing layer, thereby stabilizing the operation of the TFT.

Therefore, the TFT is formed independently from the array element, and therefore, the source, the drain, and the gate are formed of the same material through the same process. Therefore, it is possible to reduce the processing time and process cost of the TFT through a simpler process than the related art.

It is obvious that those skilled in the art can make modifications and changes to the present invention without departing from the spirit or scope of the present invention. Thus, the present invention is intended to cover various modifications and changes that come within the scope of the claims of the present invention and their equivalents.

Claims (35)

1, a kind of thin-film transistor comprises:

Be positioned at the silicon nanowires on the substrate, wherein said silicon nanowires has each side part of mid portion and mid portion;

Be positioned at the grid on the described mid portion; And

Be positioned on each side part source electrode and with the separated drain electrode of described source electrode, wherein said source electrode and drain electrode are electrically connected to described silicon nanowires.

2, thin-film transistor according to claim 1 is characterized in that, described silicon nanowires comprises the core of semi-conducting material and surrounds the insulating barrier of described core.

3, thin-film transistor according to claim 2 is characterized in that, described silicon nanowires has coaxial configuration between core and insulating barrier.

4, thin-film transistor according to claim 1 is characterized in that, described silicon nanowires has bar-shaped.

5, thin-film transistor according to claim 1 is characterized in that, described silicon nanowires is made up of many silicon nanowires.

6, thin-film transistor according to claim 1 is characterized in that, described grid is by making with described source electrode and drain electrode identical materials.

7, thin-film transistor according to claim 1, it is characterized in that, also comprise between described silicon nanowires and the described grid, between described silicon nanowires and the described source electrode and the fixed bed between described silicon nanowires and the described drain electrode, wherein said fixed bed is fixed on described silicon nanowires on the described substrate.

8, thin-film transistor according to claim 7, it is characterized in that, described fixed bed comprises first contact hole and second contact hole that exposes described source electrode of part and described drain electrode respectively, and described source electrode and described drain electrode are connected to described silicon nanowires via described first contact hole and second contact hole respectively.

9, thin-film transistor according to claim 7 is characterized in that, described fixed bed comprises organic insulating material.

10, thin-film transistor according to claim 9 is characterized in that, described organic insulating material one of comprises in benzocyclobutene and the acrylic resin.

11, a kind of array base palte that is used for flat-panel display device comprises:

Be positioned at the silicon nanowires on the substrate, wherein said silicon nanowires has each side part of mid portion and described mid portion;

Be positioned at the grid on the described mid portion;

Be positioned on described each side part first source electrode and with separated first drain electrode of described first source electrode, wherein said first source electrode and described first drain electrode are electrically connected to described silicon nanowires;

Be connected to second source electrode of described first source electrode and be connected to second of described first drain electrode and drain; And

Be connected to the pixel electrode of described second drain electrode.

12, array base palte according to claim 11, it is characterized in that, also be included between described first source electrode and described second source electrode and described first drain electrode and described second drain electrode between gate insulation layer, described gate insulation layer has first and second contact holes that expose described first source electrode of part and described first drain electrode respectively.

13, array base palte according to claim 12 is characterized in that, described second source electrode is connected to described first source electrode via described first contact hole and described second drain electrode is connected to described first drain electrode via described second contact hole.

14, array base palte according to claim 11, it is characterized in that, also comprise between described second source electrode and the described pixel electrode and described second the drain electrode and described pixel electrode between passivation layer, wherein said passivation layer comprise expose part described second the drain electrode the drain contact hole.

15, array base palte according to claim 14 is characterized in that, described pixel electrode is connected to described second drain electrode via described drain contact hole.

16, a kind of thin-film transistor comprises:

Be positioned at the silicon nanowires on the substrate, described silicon nanowires has each side part of mid portion and described mid portion;

Be positioned at the gate insulation layer on the described mid portion;

Be positioned at the grid on the described gate insulation layer; And

Be positioned on described each side part source electrode and with the separated drain electrode of described source electrode, described source electrode directly contacts described silicon nanowires with described drain electrode.

17, thin-film transistor according to claim 16 is characterized in that, also comprises at the mid portion of described silicon nanowires and the fixed bed between the described gate insulation layer.

18, a kind of array base palte that is used for flat-panel display device comprises:

Be positioned at the silicon nanowires on the described substrate, described silicon nanowires has each side part of mid portion and described mid portion;

Be positioned at the gate insulation layer of described mid portion;

Be positioned at the grid on the described gate insulation layer;

Be positioned on described each side part first source electrode and with separated first drain electrode of described first source electrode, described first source electrode and described first drain electrode directly contact silicon nanowires;

Be connected to second source electrode of described first source electrode and be connected to second of described first drain electrode and drain; And

Be connected to the pixel electrode of described second drain electrode.

19, a kind of method of manufacturing thin film transistor comprises:

Silicon nanowires is set on substrate, and described silicon nanowires has each side part of mid portion and described mid portion;

On described mid portion, form grid; And

On described each side part, form source electrode and with the separated drain electrode of described source electrode, described source electrode and drain electrode are electrically connected to described silicon nanowires.

20, method according to claim 19 is characterized in that, also is included between described silicon nanowires and the described source electrode and between described silicon nanowires and the described drain electrode and forms fixed bed, and described fixed bed is fixed on described silicon nanowires on the described substrate.

21, method according to claim 20, it is characterized in that, the step of described formation fixed bed comprises and forms first contact hole and second contact hole expose described source electrode of part and described drain electrode, and described source electrode and described drain electrode are connected to described silicon nanowires via described first contact hole and described second contact hole respectively.

22, method according to claim 19 is characterized in that, by spraying described silicon nanowires is arranged on the described substrate.

23, method according to claim 19 is characterized in that, also comprises by deposition having the catalyst of nano-grade size and comprising that by use the reaction gas of silicon makes the described silicon nanowires of the brilliant formation of described catalyst junction.

24, method according to claim 19 is characterized in that, forms described grid by the operation identical with described drain electrode with described source electrode.

25, a kind of manufacture method that is used for the array base palte of flat-panel display device comprises:

Silicon nanowires is set on substrate, and described silicon nanowires has each side part of mid portion and described mid portion;

On described mid portion, form grid;

On described each side part, form first source electrode and with separated first drain electrode of described first source electrode, described first source electrode and described first drain electrode are electrically connected to described silicon nanowires;

Formation is connected to second source electrode of described first source electrode and is connected to second drain electrode of described first drain electrode; And

Formation is connected to the pixel electrode of described second drain electrode.

26, method according to claim 25, it is characterized in that, also be included between described first source electrode and described second source electrode and described first drain electrode and described second drain electrode between form gate insulation layer, described gate insulation layer has first contact hole and second contact hole that exposes described first source electrode of part and described first drain electrode respectively.

27, method according to claim 26 is characterized in that, described second source electrode is connected to described first source electrode via described first contact hole and described second drain electrode is connected to described first drain electrode via described second contact hole.

28, method according to claim 26, it is characterized in that, also be included between described second source electrode and the described pixel electrode and between described second drain electrode and the described pixel electrode and form passivation layer, described passivation layer comprises the drain contact hole that exposes described second drain electrode of part.

29, method according to claim 28 is characterized in that, described pixel electrode is connected to described second drain electrode via described drain contact hole.

30, a kind of method of manufacturing thin film transistor comprises:

Coating comprises the solvent of silicon nanowires on substrate, and described silicon nanowires has each side part of mid portion and described mid portion;

Remove solvent outside the silica removal nano wire from substrate;

Order forms gate insulation layer and grid on described mid portion; And

On described each side part, form source electrode and with the separated drain electrode of described source electrode, described source electrode directly contacts described silicon nanowires with described drain electrode.

31, method according to claim 30 is characterized in that, described solvent also comprises surfactant.

32, method according to claim 31 is characterized in that, by adding the described solvent of heat abstraction.

33, method according to claim 32 is characterized in that, carries out described heating under about 100 degrees centigrade temperature being lower than.

34, method according to claim 30 is characterized in that, also is included between the mid portion of described silicon nanowires and the described gate insulation layer and forms fixed bed.

35, a kind of manufacture method that is used for the array base palte of flat-panel display device comprises:

Coating comprises the solvent of silicon nanowires on substrate, and wherein said silicon nanowires has each side part of mid portion and described mid portion;

From the solvent of substrate removal except that described silicon nanowires;

Order forms gate insulation layer and grid on described mid portion;

On each side part, form first source electrode and with separated first drain electrode of described first source electrode, wherein said first source electrode and described first drain electrode directly contact silicon nanowires;

Formation is connected to second source electrode of described first source electrode and is connected to second drain electrode of described first drain electrode; And

Formation is connected to the pixel electrode of described second drain electrode.

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