CN1171188C - Thin film transistor flat display and manufacturing method thereof - Google Patents

Abstract

A thin film transistor flat panel display and a method for fabricating the same are provided, wherein the display is fabricated on a substrate, and the substrate comprises a transistor region and a connection pad region. The method comprises forming a gate electrode and a pad electrode on a transistor region and a connection pad region, respectively, depositing a first insulating layer on a substrate, and forming a connection pad opening in the first insulating layer on the connection pad region. And then sequentially depositing a second insulating layer, a semiconductor layer, a doped silicon conducting layer and a second metal layer on the first insulating layer, and then defining a channel region in the transistor region. Finally, a patterned protective layer is formed on the substrate, and then the semiconductor layer and the second insulating layer which are not shielded by the protective layer are etched.

Description

Thin film transistor flat panel display and manufacturing method thereof

technical field

The invention relates to a manufacturing method of a thin film transistor plane display and its corresponding structure.

Background technique

Thin film transistor flat panel displays, especially thin film transistor liquid crystal displays (thin film transistor display, hereinafter referred to as TFT-LCD), mainly use thin film transistors arranged in a matrix to drive liquid crystal pixels with appropriate capacitors, adapter pads and other electronic components. To produce rich and bright graphics. Because TFT-LCD has the characteristics of light and thin appearance, low power consumption and no radiation pollution, it is widely used in portable information products such as notebook computers (notebooks) and personal digital assistants (PDAs), and has even gradually replaced traditional LCDs. The trend of CRT monitors for desktop computers.

Please refer to FIG. 1A to FIG. 1H . FIG. 1A to FIG. 1H are schematic diagrams of the manufacturing process of a transistor (transistor) of a conventional thin film transistor liquid crystal display 10 . The transistor of existing TFT-LCD 10 is made on the surface of a glass substrate (glass substrate) 12. As shown in FIG. 1A, the manufacturing process of the existing TFT-LCD 10 first deposits an aluminum metal layer 14 and a cover layer (cap layer) 16 on the surface of the glass substrate 12, and then performs a first yellow light and etching process. In a photo-etching-process (PEP), a pattern of an aluminum metal layer 14 and a cover layer 16 is formed on the surface of the glass substrate 12 to serve as a gate electrode.

Subsequently, as shown in FIG. 1B , an insulating layer 18 , an amorphous silicon layer 20 and a doped amorphous silicon layer 22 are sequentially deposited on the glass substrate 12 . As shown in Figure 1C, then carry out a second photolithography and etching process (PEP), remove the doped amorphous silicon layer 22 and the amorphous silicon layer 20 outside a transistor region 24, make the transistor region 24 outside The insulating layer 18 is exposed. As shown in FIG. 1D , after the second photolithography and etching process is completed, a metal layer 26 is then fully deposited on the surface of the glass substrate 12 . Subsequently, as shown in FIG. 1E , a third photolithography and etching process is performed to define the pattern of the metal layer 26 . Next, using the metal layer 26 as a mask (hard mask), the doped amorphous silicon layer 22 is etched downward, and the remaining doped amorphous silicon layer 22 and the metal layer 26 are respectively used as a source conductive layer 28 and a Drain conductive layer 30 .

As shown in FIG. 1F , after the third photolithography and etching process, a protective layer 32 is fully deposited on the surface of the glass substrate 12 . As shown in FIG. 1G , a fourth photolithography and etching process is then performed to define the pattern of the protection layer 32 and form a drain opening 34 on the surface of the drain conductive layer 30 . Subsequently, an indium tin oxide (ITO) layer 32 is fully deposited on the surface of the glass substrate 12 , and the ITO layer 32 is filled into the drain opening 34 .

Finally, as shown in FIG. 1H , a fifth photolithography and etching process is performed to form a pattern of the ITO layer 36 to electrically conduct the drain conductive layer 30 with a display region (not shown). TFT-LCD 10 uses transistors to control the brightness of the display area.

The current manufacturing method of TFT-LCD 10 requires as many as five yellow light and etching processes to form transistors as switching elements. This not only increases the cost and time of the manufacturing process, but also makes the production of TFT-LCD 10 The process yield is difficult to further improve. In addition, TFT-LCD still includes many other electronic components. In order to save costs and reduce the complexity of the manufacturing process, it is necessary to integrate related electronic components into a single manufacturing process to compete with cheap CRT monitors. Accelerate the market to replace CRT monitors.

Contents of the invention

The purpose of the present invention is to provide a method for manufacturing a thin film transistor flat panel display, which can manufacture a variety of different capacitors and reduce the resistance values of transistors and capacitors without changing the manufacturing process parameters.

The object of the present invention is achieved by providing a manufacturing method of a thin film transistor flat panel display, the display is manufactured on a substrate (substrate), the substrate includes a first part and a second part, the first part includes a transistor (transistor) region, used to form a transistor, the second part includes a connection pad (pad) region, used to form a connection pad, the manufacturing method includes the following steps: (a) depositing a first on the surface of the substrate a metal layer; (b) defining the pattern of the first metal layer for forming a gate electrode in the transistor region, and forming a pad electrode in the connection pad region; (c) forming a first on the substrate insulating layer, and define the pattern of the first insulating layer, and form a connection pad opening in the connection pad region, so that the pad electrode is exposed; (d) sequentially depositing a second insulating layer, A semiconductor layer, a doped silicon (doped silicon) conductive layer and a second metal layer; (e) defining a channel region in the transistor region, while removing the second metal layer and the second metal layer in the channel and outside the transistor region The doped silicon conductive layer is such that the remaining second metal layer in the transistor region forms a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region (f) depositing a passivation layer (passivation layer) on the entire surface of the substrate; and (g) defining a pattern of the passivation layer and removing the passivation layer outside the first portion , so that the semiconductor layer is exposed to the area other than the first part, and then, using the protective layer as an etching mask, remove the semiconductor layer and the second insulating layer not covered by the protective layer, so that the first insulating layer A region exposed outside the first portion, and the pad electrode is exposed in the connection pad opening.

Preferably, the substrate further includes a capacitor region for forming a capacitor, and the manufacturing method further includes the following steps: when defining the pattern of the first metal layer in step (b), forming a capacitor in the capacitor region lower electrode; when defining the protective layer pattern in step (g), define a source opening on the source metal layer, define a drain opening on the drain metal layer, remove the source opening and the The protection layer in the drain opening, so that the source metal layer and the drain metal layer of the transistor region are exposed, and the first insulating layer is also exposed in the capacitor region; (h) forming a transparent layer on the substrate a conductive layer, the transparent conductive layer covers the capacitance area, and fills in the source opening, the drain opening and the connection pad opening; and (i) defines a pattern of the transparent conductive layer, so that the transparent conductive layer is spaced apart by A source block, a drain block and a connection pad block electrically isolated from each other, wherein the source block is electrically connected to the source metal layer through the source opening, and the drain block is electrically connected to the source metal layer through the drain The electrode opening is electrically connected to the drain metal layer, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive layer forms a capacitor upper electrode in the capacitor area.

The present invention also provides a manufacturing method of a thin film transistor flat panel display, the display is manufactured on a substrate (substrate), the substrate includes a first part, a second part and a third part, the first part includes a transistor (transistor ) area for forming a transistor, the second part includes a connection pad (pad) area for forming a connection pad, the third part includes a capacitor (capacitor) area for forming a capacitor, the manufacturing method The method comprises the following steps: (a) depositing a first metal layer on the surface of the substrate; (b) defining a pattern of the first metal layer for forming a gate electrode in the transistor region and forming a gate electrode in the capacitor region Capacitor lower electrode, and form a pad electrode in the connection pad area; (c) form a first insulating layer on the substrate, and define the pattern of the first insulating layer, and form a connection pad opening in the connection pad area, exposing the pad electrode; (d) sequentially depositing a second insulating layer, a semiconductor layer, a doped silicon (doped silicon) conductive layer and a second metal layer on the first insulating layer; (e) Define a channel area in the transistor area, and remove (1) the channel area, and (2) the second metal layer and the doped silicon conductive layer outside the transistor area and the capacitor area, so that in the transistor area The remaining second metal layer forms a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region, so that the remaining second metal layer in the capacitance region The metal layer forms a capacitor upper electrode, and the semiconductor layer is exposed outside the transistor region and the capacitor region; (f) depositing a passivation layer on the substrate so as to cover the transistor region, and the capacitor area and the connection pad area, and the protection layer will be filled in the channel area; and (g) define the pattern of the protection layer, first define a source opening on the source metal layer, and define a source opening on the drain metal layer A drain opening is defined above, a capacitor opening is defined in the capacitor region, and (1) the protective layer outside the first part and the third part and (2) inside the source opening, inside the drain opening, and the protective layer in the capacitor opening, so that (1) the semiconductor layer is exposed to areas other than the first portion and the third portion, (2) the source metal layer is exposed to the source opening, and the drain metal layer layer is exposed to the drain opening, and the capacitor upper electrode is exposed to the capacitor opening; (h) using the protective layer as an etching mask, simultaneously removing the semiconductor layer and the second insulating layer not covered by the protective layer, so that (1) the first insulating layer is exposed to areas other than the first part and the third part, (2) the pad electrode is exposed in the connection pad opening; (i) a transparent conductive layer is formed on the entire surface of the substrate , the transparent conductive layer is filled into the source opening, the drain opening, the capacitor opening and the connection pad opening; and (j) defining the pattern of the transparent conductive layer, so that the transparent conductive layer is spaced to be electrically isolated from each other A source block, a drain block and a connection pad block, wherein the source block is electrically connected to the source metal layer through the source opening, and the drain block is connected to the source metal layer through the drain opening The drain metal layer is electrically connected, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive layer is electrically connected to the capacitor upper electrode.

Preferably, the method further includes the following steps: when defining the first insulating layer in step (c), forming an opening in the capacitor insulating layer in the capacitor region to expose the lower electrode of the capacitor; and in step (d) , the second insulating layer will fill the opening of the capacitive insulating layer.

The present invention also provides a thin film transistor flat panel display, which includes: a substrate; a thin film transistor, the thin film transistor includes: a gate electrode is formed on the substrate; a transistor insulating layer and a transistor semiconductor layer are sequentially formed on the substrate On the gate electrode; a first doped silicon layer and a second doped silicon layer are formed on the semiconductor layer of the transistor, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer is formed on the first doped silicon layer; a drain conductive layer is formed on the second doped silicon layer; and a transistor protection layer covers the channel region, the source conductive layer, and the drain conductive layer ; a gate contact, the gate contact includes: a pad electrode formed on the substrate, the pad electrode is electrically connected to the gate electrode; a connection pad insulating layer is formed around the border of the pad electrode to form a connection pad an opening; the connection pad opening penetrates the connection pad insulating layer to expose the pad electrode; wherein, the side wall of the transistor insulating layer is substantially aligned with the side wall of the transistor semiconductor layer, and the side wall of the source conductive layer is aligned with the side wall of the transistor semiconductor layer. The sidewalls of the first doped silicon layer are substantially flush.

Preferably, there is a distance between the sidewall of the source conductive layer and the sidewall of the transistor insulating layer.

Preferably, the protective layer has a source opening on the source conductive layer and a drain opening on the drain conductive layer, and the thin film transistor liquid crystal display further includes: a transparent source conductive layer block electrically conducting with the source conductive layer through the source opening; a transparent drain conducting layer block electrically conducting with the drain conducting layer through the drain opening; and a transparent connecting pad conducting layer block passing through the connecting pad opening is in electrical conduction with the pad electrode.

Preferably, the thin film transistor flat-panel display further includes a capacitor, and the capacitor includes: a lower electrode of the capacitor, which has the same composition as the gate electrode; a first insulating layer, covering the lower electrode of the capacitor; and a transparent conductive layer covering the lower electrode of the capacitor. first insulating layer. Another solution is that the thin film transistor flat panel display further includes a capacitor, and the capacitor includes in sequence: a lower electrode of the capacitor, which has the same composition as the gate electrode; a first insulating layer, covering the lower electrode of the capacitor; a second An insulating layer and a semiconductor layer are formed on the first insulating layer; a doped silicon layer, a capacitor upper electrode, and a capacitor protection layer are formed on the semiconductor layer, and the capacitor protection layer has a capacitor opening, so that The capacitor upper electrode is exposed in the capacitor opening; and a transparent conductive layer covers the first capacitor protection layer, the transparent conductive layer fills the capacitor opening and is electrically connected with the capacitor upper electrode.

Preferably, the first insulating layer of the capacitor has an opening of the first insulating layer, exposing the lower electrode of the capacitor, and the second insulating layer will fill the opening of the first insulating layer.

The present invention also provides a manufacturing method of a thin film transistor display (thin film transistor display), the display is manufactured on a substrate (substrate), the substrate includes a first part and a second part, the first part includes a transistor (transistor) region, used to form a transistor, the second part includes a connection pad (pad) region, used to form a connection pad, the manufacturing method includes the following steps: (a) depositing a first on the surface of the substrate a metal layer; (b) defining the pattern of the first metal layer to form a gate electrode in the transistor region and a pad electrode in the connection pad region; (c) sequentially depositing a insulating layer, a semiconductor layer, a doped silicon (doped silicon) conductive layer, and a second metal layer; (d) defining a channel region in the transistor region, while removing (1) the channel region in the first part and (2) the second metal layer and the doped silicon conductive layer outside the transistor region, so that the remaining second metal layer in the transistor region forms a source metal layer and a drain metal layer layer, and the source metal layer and the drain metal layer are separated by the channel region, and the semiconductor layer is exposed outside the transistor region; (e) depositing a passivation layer on the substrate, make it cover the transistor region and the connection pad region, and the protection layer will fill in the channel region; and (f) define the pattern of the protection layer, first define a connection pad opening in the connection pad region, and remove (1) a protective layer outside the first portion and (2) outside the second portion and within the connection pad opening, such that the semiconductor layer is exposed to (1) the area outside the first portion and (2) the area outside the second portion and the connection pad opening; (g) using the protective layer as an etching mask, simultaneously remove (1) the first part and (2) the second part and the connection pad opening that are not covered by the protective layer The semiconductor layer and the insulating layer, so that (1) the substrate is exposed in the first part and the area outside the second part, and (2) the pad electrode is exposed in the connection pad opening.

Preferably, the method further includes the following steps: when defining the protective layer pattern in step (f), defining a source opening on the source metal layer, and defining a drain opening on the drain metal layer , removing the protective layer in the source opening and the drain opening, so that the source metal layer and the drain metal layer of the transistor region are exposed; (h) forming a transparent conductive layer on the substrate to make the transparent a conductive layer filling the source opening, the drain opening and the connection pad opening; and (i) defining a pattern of the transparent conductive layer such that the transparent conductive layer is spaced into a source region electrically isolated from each other, a a drain block and a connection pad block, wherein the source block is electrically connected to the source metal layer through the source opening, and the drain block is electrically connected to the drain metal layer through the drain opening, The connection pad block is electrically connected to the pad electrode through the connection pad opening.

Preferably, the substrate further includes a third portion, the third portion includes a capacitor area for forming a capacitor, and the manufacturing method further includes the following steps: defining the pattern of the first metal layer in step (b) When, a capacitor lower electrode is further formed in the capacitor region; in step (c), the insulating layer, the semiconductor layer, the doped silicon conductive layer, and the second metal layer are also formed in the capacitor region; in step (c) In d), the second metal layer and the doped silicon conductive layer in the third part that do not cover the lower electrode of the capacitor are removed at the same time, so that the semiconductor layer outside the capacitor region is exposed, and the second metal remaining in the capacitor region layer to form a capacitor upper electrode; when (f) step defines the protective layer pattern, a capacitor opening is formed in the capacitor region, so that the capacitor upper electrode is exposed; and in (h) step, the transparent conductive layer is also It is filled into the opening of the capacitor and is electrically connected to the upper electrode of the capacitor.

Preferably, the TFT-LCD is a planar rotation TFT-LCD.

Preferably, the semiconductor layer is an amorphous silicon layer or a polysilicon layer.

The present invention also provides a thin film transistor flat panel display, which includes: a substrate; a thin film transistor, the thin film transistor includes: a gate electrode is formed on the substrate; a transistor insulating layer and a transistor semiconductor layer are sequentially formed on the substrate On the gate electrode; a first doped silicon layer and a second doped silicon layer are formed on the semiconductor layer of the transistor, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer is formed on the first doped silicon layer; a drain conductive layer is formed on the second doped silicon layer; and a transistor protection layer covers the channel region, the source conductive layer, and the drain conductive layer. layer; a gate contact, the gate contact includes: a pad electrode formed on the substrate, the pad electrode is electrically connected to the gate electrode; a connection pad insulating layer, a connection pad semiconductor layer, and a connection pad protection Layers are sequentially formed around the boundary of the pad electrode to form a connection pad opening; the connection pad opening penetrates the connection pad insulating layer, the connection pad semiconductor layer, and the connection pad protection layer to expose the pad electrode; A conductive layer is filled into the opening of the connection pad region to electrically connect the pad electrode; wherein, the sidewall of the transistor insulating layer is substantially aligned with the sidewall of the transistor semiconductor layer, and the sidewall of the source conductive layer is aligned with the sidewall of the transistor semiconductor layer. The sidewalls of the first doped silicon layer are substantially flush.

Preferably, there is a distance between the sidewall of the source conductive layer and the sidewall of the transistor insulating layer.

Alternatively, the thin film transistor flat-panel display further includes a capacitor, and the capacitor includes: a capacitor lower electrode, which has the same composition as the gate electrode; a capacitor insulating layer, covering the capacitor lower electrode; a capacitor semiconductor layer, a capacitor doped silicon Layer, a capacitor upper electrode, and a capacitor protection layer are formed on the capacitor semiconductor layer, the capacitor protection layer has a capacitor opening, so that the capacitor upper electrode is exposed in the capacitor opening; and a transparent conductive layer covers the capacitor The capacitor protection layer, and the transparent conductive layer fills the capacitor opening and is electrically connected with the capacitor upper electrode.

Alternatively, the transistor protection layer has a source opening on the source conductive layer and a drain opening on the drain conductive layer, and the thin film transistor liquid crystal display further includes: a transparent source conductive layer block electrically conducting with the source conductive layer through the source opening; a transparent drain conducting layer block electrically conducting with the drain conducting layer through the drain opening; and a transparent connecting pad conducting layer block passing through the connecting pad opening is in electrical conduction with the pad electrode.

The present invention also provides a thin film transistor, which includes: a substrate; a gate electrode formed on the substrate; an insulating layer and a semiconductor layer sequentially formed on the gate electrode; a first doped silicon layer and A second doped silicon layer is formed on the semiconductor layer, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer and a drain conductive layer are respectively formed on the semiconductor layer On the first doped silicon layer and the second doped silicon layer; and a protective layer covering the channel region, the source conductive layer, and the drain conductive layer; wherein, the insulating layer sidewall and the semiconductor layer The sidewalls are substantially aligned, and the sidewalls of the source conductive layer are substantially aligned with the sidewalls of the first doped silicon layer.

Preferably, there is a distance between the sidewall of the source conductive layer and the sidewall of the insulating layer.

Preferably, the protection layer has a drain opening to expose the drain metal layer.

Preferably, the thin film transistor further includes a transparent electrode formed on the protection layer, filling the drain opening of the protection layer, and electrically communicating with the drain metal layer.

The present invention also provides a manufacturing method of a thin film transistor display (thin film transistor display), the display is manufactured on a substrate, the substrate includes a first part and a second part, the first part includes a transistor (transistor) region , used to form a transistor, the second part includes a connection pad (pad) region, used to form a connection pad, the manufacturing method includes the following steps: (a) depositing a first metal layer on the surface of the substrate; (b) defining the pattern of the first metal layer for forming a gate electrode in the transistor region and forming a pad electrode in the connection pad region; (c) sequentially forming a first insulating layer on the substrate , a second insulating layer, a semiconductor layer, a doped silicon (doped silicon) conductive layer, and a second metal layer; (d) defining a channel region in the transistor region, while removing (1) the channel and (2) The second metal layer outside the transistor region and the doped silicon conductive layer, so that the remaining second metal layer in the transistor region forms a source metal layer and a drain metal layer, and the source The metal layer and the drain metal layer are separated by the channel region, and the semiconductor layer is exposed outside the transistor region; (e) depositing a passivation layer on the substrate; (f) defining the passivation layer pattern, remove the protective layer outside the first part, so that the semiconductor layer is exposed to the area outside the first part, and then use the protective layer as an etching mask to remove the semiconductor layer and the first part that are not shielded by the protective layer. Two insulating layers, so that the first insulating layer is exposed to the area outside the first portion; and (g) defining a pattern of the first insulating layer, forming a connection pad opening in the connection pad area, exposing the pad electrode .

Preferably, the substrate further includes a capacitor region for forming a capacitor, and the manufacturing method further includes the following steps: when defining the pattern of the first metal layer in step (b), forming a capacitor lower electrode in the capacitor region; When defining the protective layer pattern in step (f), define a source opening on the source metal layer, define a drain opening on the drain metal layer, remove the source opening and the drain opening The inner protective layer, so that the source metal layer and the drain metal layer of the transistor region are exposed, and the first insulating layer is also exposed in the capacitor region; (h) forming a transparent conductive layer on the substrate, The transparent conductive layer covers the capacitor region and fills in the source opening, the drain opening and the connection pad opening; and (i) defining a pattern of the transparent conductive layer such that the transparent conductive layers are spaced to be electrically isolated from each other A source block, a drain block and a connection pad block, wherein the source block is electrically connected to the source metal layer through the source opening, and the drain block is connected to the source metal layer through the drain opening The drain metal layer is electrically connected, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive layer forms a capacitor upper electrode in the capacitor area.

Description of drawings

Embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

FIG. 1A to FIG. 1H are schematic diagrams of the manufacturing process of the transistor of the existing thin film transistor liquid crystal display;

2A to 2G are schematic diagrams of the manufacturing process of the first embodiment of the thin film transistor liquid crystal display of the present invention;

3A to 3B are schematic diagrams of a second embodiment of the thin film transistor liquid crystal display of the present invention;

4A to 4I are schematic diagrams of the manufacturing process of the third embodiment of the manufacturing method of the present invention;

Fig. 5 is a schematic diagram of a fourth embodiment of the manufacturing method of the present invention.

Illustration of symbols

50 Thin Film Transistor Liquid Crystal Displays 51 Part 1

52 Substrates 53 Part II

54 Transistor Area 55 Part 3

56 Capacitor Area 58 Transfer Pad Area

60 transistors 62 capacitors

64 transfer pads 66 metal layers

66a grid electrode 66b capacitor lower electrode

66c pad electrode 68, 681, 682 insulation layer

68a Transistor insulating layer         68b Capacitor insulating layer

68c connection pad insulation layer 70 semiconductor layer

70a transistor semiconductor layer 70b capacitor semiconductor layer

70c connection pad semiconductor layer 72 doped silicon conductive layer

72a first doped silicon layer 72b second doped silicon layer

72c capacitor doped silicon layer 74 metal layer

74a source metal layer 74b drain metal layer

74c capacitor upper electrode 75 channel area

76 protective layer 76a transistor protective layer

76b capacitor protection layer 76c connection pad protection layer

78a source open 78b drain open

78c capacitor opening 80 connection pad opening

82 transparent conductive layer 82a source block

82b drain block 82c connection pad block

84a Capacitor insulating layer opening 84b Connection pad opening

Detailed ways

Please refer to FIG. 2A to FIG. 2G . FIG. 2A to FIG. 2G are schematic diagrams of the manufacturing process of the thin film crystal flat panel display 50 of the present invention. The preferred embodiment of the present invention takes a thin film transistor liquid crystal display (hereinafter referred to as TFT-LCD) 50 as an example. , at least one second part 53 and at least one third part 55 . The first part 51 includes a transistor region 54 , the third part 55 includes a capacitor region 56 , and the second part 53 includes a pad region 58 . The transistor region 54 , the capacitor region 56 and the transfer pad region 58 are used to form a transistor 60 , a capacitor 62 and a transfer pad 64 respectively.

The manufacturing process of the TFT-LCD 50 of the present invention is to deposit a metal layer 66 in an all-round way on the surface of the substrate 52 earlier, and then define the pattern of the metal layer 66, in order to form a gate electrode 66a in the transistor region 54, in the capacitance region 56 A capacitor bottom electrode 66b is formed, and a pad electrode 66c is formed in the connection pad area 58, as shown in FIG. 2A.

As shown in FIG. 2B , an insulating layer 68 , a semiconductor layer 70 , a doped silicon conductive layer 72 and a metal layer 74 are deposited on the substrate 52 in sequence. The semiconductor layer 70 can be selected as a polysilicon (poly-silicon) layer or an amorphous silicon (amorphous silicon) layer, depending on conditions such as manufacturing process and display area.

Then, as shown in FIG. 2C, the patterns of the insulating layer 68, the semiconductor layer 70, the doped silicon conductive layer 72 and the metal layer 74 are defined, and a channel region 75 is first defined in the transistor region 54, and the (1) first part 51 is removed Inside the channel region 75 and outside the transistor region 54, (2) the metal layer 74 in the second part 53 and the doped silicon conductive layer 72, (3) the metal layer not covering the capacitor lower electrode 66b in the third part 55 74 and the conductive layer 72 of doped silicon. In this way, the remaining metal layer 74 in the transistor region 54 forms a source metal layer 74a and a drain metal layer 74b, and the remaining metal layer 74 in the capacitor region 56 forms a capacitor upper electrode 74c. The source metal layer 74 a and the drain metal layer 74 b are separated by the channel region 75 and expose the semiconductor layer 70 outside the transistor region 54 and the capacitor region 56 .

Next, as shown in FIG. 2D , a passivation layer 76 is deposited on the patterned surface of the semiconductor layer 70 and the metal layer 74 . The protection layer 76 covers the transistor region 54 , the capacitor region 56 and the connection pad region 58 , and the protection layer 76 fills in the channel region 75 .

Next, define the pattern of the protective layer 76, as shown in Figure 2E, define a source opening 78a on the source metal layer 74a, define a drain opening 78b on the drain metal layer 74b, and define a The capacitor opening 78c defines a pad opening 80 in the pad area 58 . Then remove the protection layer 76 outside the first portion 51 , the second portion 53 and the third portion 55 , and simultaneously remove the protection layer 76 in the source opening 78 a , drain opening 78 b , capacitor opening 78 c and connection pad opening 80 . At this time, the semiconductor layer 70 will be exposed to areas other than the first portion 51 , the second portion 53 and the third portion 55 , and exposed to the connection pad opening 80 . In addition, the source metal layer 74a and the drain metal layer 74b in the transistor region 54 will be exposed, and the capacitor top electrode 74c will also be exposed.

Then use the protective layer 76 as an etching mask to simultaneously remove the semiconductor layer 70 and the insulating layer 68 that are not covered by the protective layer 76 and are located outside the first portion 51, the second portion 53 and the third portion 55, and simultaneously remove the connection pad opening The semiconductor layer 70 and the insulating layer 68 within the 80. In this way, (1) the glass substrate 52 is exposed outside the first portion 51 , the second portion 53 and the third portion 55 , and (2) the pad electrode 66 c is exposed in the connection pad opening 80 . So far in the manufacturing method of the present invention, the manufacturing of the transistor 60 and the capacitor 62 is completed.

Next, as shown in FIG. 2F , a transparent conductive layer 82 is deposited on the substrate 52 . The transparent conductive layer 82 is usually made of indium tin oxide (ITO), and is filled into the source opening 78a, the drain opening 78b, the capacitor opening 78c and the connection pad opening 80, so that the transparent conductive layer 82 It is electrically connected with the source metal layer 74a, the drain metal layer 74b, the capacitor upper electrode 74c and the pad electrode 66c.

Finally, as shown in FIG. 2G , the pattern of the transparent conductive layer 82 is defined so that the transparent conductive layer 82 is separated into a source block 82 a , a drain block 82 b and a connection pad block 82 c which are electrically isolated from each other. The source block 82a is electrically connected to the source metal layer 74a through the source opening 78a, the drain block 82b is electrically connected to the drain metal layer 74b through the drain opening 78b, and the drain block 82b is connected to the drain metal layer 74b through the capacitor opening 78c. The capacitor upper electrode 74c is electrically connected, and the connection pad block 82c is electrically connected to the pad electrode 66c through the connection pad opening 80 . After this step, the transparent conductive layer 82 is electrically connected to the transistor 60 and the capacitor 62, and the fabrication of the transfer pad 64 is also completed.

On the other hand, the TFT-LCD 50 produced by the above-mentioned production method only needs four yellow light and etching production processes to produce. Its structure includes a substrate 52 , a TFT 60 , a capacitor 62 and a connection pad 64 as a gate contact. As shown in FIG. 2G, the thin film transistor 60 includes: a gate electrode 66a formed on the substrate 52; a transistor insulating layer 68a and a transistor semiconductor layer 70a sequentially formed on the gate electrode 66a; a first doped The heterosilicon layer 72a and a second doped silicon layer 72b are formed on the transistor semiconductor layer 70a, and a channel region 75 is separated between the first and second doped silicon layers 72a, 72b; a source conductive layer 74a is formed On the first doped silicon layer 72a; a drain conductive layer 74b is formed on the second doped silicon layer 72b; and a transistor protection layer 76a covers the channel region 75, the source conductive layer 74a, and the drain conductive layer Layer 74b.

Wherein, the sidewall of the transistor insulating layer 68a of the transistor 60 is substantially aligned with the sidewall of the transistor semiconductor layer 70a, and the sidewall of the source conductive layer 74a is substantially cut with the sidewall of the first doped silicon layer 72a. and the sidewalls of the drain conductive layer 74b are substantially aligned with the sidewalls of the second doped silicon layer 72b. In addition, there is a distance between the sidewalls of the source conductive layer 74 a , the sidewalls of the drain conductive layer 74 b and the sidewalls of the transistor insulating layer 70 .

The capacitor 62 includes: a capacitor lower electrode 66b, which has the same composition as the gate electrode 66a; a capacitor insulating layer 68b, covering the capacitor lower electrode 66b; a capacitor semiconductor layer 70b, a capacitor doped silicon layer 72c, The capacitor upper electrode 74c and a capacitor protection layer 76b are formed on the capacitor semiconductor layer 70b; and a transparent conductive layer 82b covers the capacitor protection layer 76b. The capacitive protection layer 76b has a capacitive opening 78c, exposing the capacitive top electrode 74c in the capacitive opening 78c, so that the transparent conductive layer 82b can fill the capacitive opening 78c and be electrically connected with the capacitive top electrode 74c.

The gate contact includes: a pad electrode 66c is formed on the substrate 52, and the pad electrode 66c is electrically connected to the gate electrode 66a; a connection pad insulating layer 68c, a connection pad semiconductor layer 70c, and a connection pad protection layer 76c are all The connection pad opening 80 is formed around the boundary of the pad electrode 66c in sequence. The connection pad opening 80 penetrates the connection pad insulation layer 68c, the connection pad semiconductor layer 70c, and the connection pad protection layer 82c to expose the pad electrode 66c. The transparent conductive layer 82c fills in the opening 80 of the connection pad region to electrically connect the pad electrode 66c.

The transistor protection layer 76a has a source opening 78a on the source conductive layer 74a and a drain opening 78b on the drain conductive layer 74b. The TFT-LCD 10 also includes: the transparent source conductive layer block 82a is electrically connected to the source conductive layer 74a through the source opening 78a; the transparent drain conductive layer block 82b is electrically connected to the drain conductive layer 74b through the drain opening 78b and the transparent connection pad conductive layer block 82c is electrically connected to the pad electrode 66c through the connection pad opening 80 .

Please refer to FIG. 3A and FIG. 3B , which are schematic diagrams of a second embodiment of the present invention. The second embodiment is mainly applied to an in-plain-switch (IPS) type TFT-LCD. The second embodiment only needs three yellow light and etching processes, and the first two yellow light and etching processes are exactly the same as the first two yellow light and etching processes in the first embodiment. That is to say, in the third embodiment, the manufacturing process shown in FIG. 2A to FIG. 2D is performed first to form a semi-finished product as shown in FIG. 2D .

Since the in-plane switching TFT-LCD does not require large-area transparent electrodes to transmit light, and the in-plane switching TFT-LCD can directly use metal as electrodes for liquid crystal driving, the manufacturing steps of the transparent conductive layer can be omitted. As shown in FIG. 3A, in the second embodiment, the final step only needs to remove the protective layer 76, the insulating layer 68 and the semiconductor layer 70 other than the first part 51, the second part 53 and the third part 55, and connect the pads It is only necessary to form the connection pad opening 80 in the region 58 .

The above-mentioned liquid crystal display further includes a gate line (not shown), which can connect the gate electrode 66a and the pad electrode 66c, and a signal line (not shown) intersecting with the gate line. The signal line terminates at a signal line connection pad, a cross-sectional view of which is shown in FIG. 3B. As shown in FIG. 3B , the substrate 52 is sequentially provided with an insulating layer 68d, a semiconductor layer 70d and a doped silicon conductive layer 72d. Then a second conductive layer 74d is formed in a specific area of the doped silicon conductive layer, and finally a protection layer 76d is used to cover the second conductive layer 74d and the doped silicon conductive layer 72d. Wherein, an opening 82 is provided at a position corresponding to the second conductive layer 74d to expose the second conductive layer 74d to facilitate electrical connection with an external circuit (not shown).

The structure of the second embodiment of the manufacturing method of the present invention is similar to that of the first embodiment, except that: (1) the protective layer 76 is not formed on the source conductive layer 74a, the drain conductive layer 74b and the capacitor upper electrode 74c. (2) The structure of the second embodiment does not include a transparent conductive layer.

Please refer to FIG. 4A to FIG. 4I again. FIG. 4A to FIG. 4I are schematic diagrams of the manufacturing process of the third embodiment of the manufacturing method of the present invention. In the third embodiment of the present invention, three different capacitors can be fabricated in the third parts 55a, 55b and 55c respectively. As shown in FIG. 4A, the third embodiment of the present invention first deposits a metal layer 66 on the substrate 52 to define the pattern of the metal layer 66, and then uses a first photolithography and etching process (PEP-III-1) to define the metal layer. layer 66 to form gate electrode 66a, capacitor bottom electrode 66b, and pad electrode 66c.

As shown in FIG. 4B , an insulating layer 681 is deposited on the entire surface of the substrate 52 . Subsequently, as shown in FIG. 4C, a second photolithography and etching process (PEP-III-2) is used to define the pattern of the insulating layer 681, and a capacitor insulating layer opening 84a is formed in the capacitor region 56c, so that the capacitor lower electrode 66b exposed. At the same time, a connection pad opening 84b is formed in the connection pad area 58 to expose the pad electrode 66c.

As shown in FIG. 4D, an insulating layer 682, a semiconductor layer 70, a doped silicon conductive layer 72, and a metal layer 74 are deposited on the surface of the substrate 52. The insulating layer 682 will fill the capacitor insulating layer opening 84a and the connection pad opening 84b. among. In this embodiment, the total thickness of the insulating layer 681 and the insulating layer 682 is the same as that of the insulating layer 68 in the first embodiment, so that the structure of the transistor 60 formed in the two different embodiments remains unchanged.

As shown in FIG. 4E, a third photolithography and etching process (PEP-III-3) is used to define the patterns of the insulating layer 682, the semiconductor layer 70, the doped silicon conductive layer 72, and the metal layer 74, first in the transistor area 54 defines a channel region 75, while removing the metal layer 74 and the doped silicon conductive layer 72 within the channel region 75, outside the transistor region 54, and outside the capacitor regions 56b, 56c. In this way, the remaining metal layer 74 in the transistor region 54 forms a source metal layer 74 a and a drain metal layer 74 b, and the source metal layer 74 a and the drain metal layer 74 b are separated by the channel region 75 . The remaining metal layer 74 in the capacitor regions 56b, 56c forms a capacitor upper electrode 74c, and exposes the semiconductor layer 70 to the outside of the transistor region 54 and the capacitor regions 56b, 56c.

Next, as shown in FIG. 4F, a protective layer 76 is deposited on the surface of the substrate 52, so that the protective layer 76 covers the first part 51, the second part 53, the third part 55b, 55c, the transistor region 54, the capacitor regions 56a, 56b, 56c and the connection pad area 58, and the protective layer 76 will be filled in the channel area 75.

Then, as shown in FIG. 4G, a fourth photolithography and etching process (PEP-III-4) is carried out to define the pattern of the protective layer 76, and the protective layer 76 outside the first part 51 and the third part 55b, 55c is removed, In this way, the semiconductor layer 70 of the second portion 53 and the third portion 55a is exposed. In this step, the source opening 78a is defined on the source metal layer 74a, the drain opening 78b is defined on the drain metal layer 74b, the capacitance opening 78c is defined in the capacitance regions 56b, 56c, and the source opening 78a, The protection layer 76 inside the drain opening 78b and the capacitor opening 78c. In this way, the source metal layer 74a of the transistor region 54 is exposed to the source opening 78a, the drain metal layer 74b is exposed to the drain opening 78b, and the insulating layer is also exposed to the capacitor region 66b, and the capacitive upper electrode 74c is exposed to the capacitor region. in the opening 78c.

Next, using the protective layer 76 as an etching mask, the semiconductor layer 70 and the insulating layer 682 not covered by the protective layer 76 are removed, so that the insulating layer 681 is exposed to areas other than the first part 51 and the third part 55b, 55c. That is, the second portion 53 and the third portion 55a are exposed, and the pad electrode 66c is exposed to the connection pad opening 84b. So far, the fabrication of the transistor 60 and the capacitors 62b and 62c is completed.

The connection pad opening 84b formed in FIG. 4C may not be formed in the second photolithography and etching process, and the making of the connection pad opening 84b may also be moved to after the fourth photolithography and etching process (PEP-III-4) It is carried out immediately, that is to say, the second photolithography and etching process (PEP-III-2) is moved to the fourth photolithography and etching process (PEP-III-4).

Next, as shown in FIG. 4H, a transparent conductive layer 82 is deposited on the substrate 52. The transparent conductive layer 82 will cover the capacitor regions 56a, 56b, 56c, and will fill in the source opening 78a, drain opening 78b, capacitor opening 78c and within the connection pad opening 84b.

Finally, as shown in FIG. 4I, a fifth photolithography and etching process (PEP-III-5) is performed to define the pattern of the transparent conductive layer 82, so that the transparent conductive layer 82 is at least separated into source regions 82a that are electrically isolated from each other. , the drain block 82b and the connection pad block 82c. The source block 82a is electrically connected to the source metal layer 74a through the source opening 78a, the drain block 82b is electrically connected to the drain metal layer 78b through the drain opening 78b, and the connection pad block 82c is connected to the source metal layer 74a through the connection pad opening 84b. The pad electrode 66c is electrically connected, and the transparent conductive layer 82 is electrically connected to the capacitor upper electrode 74c. The transparent conductive layer 82 electrically connects the transistor 60 and each capacitor, and completes the fabrication of the capacitor 62 a and the transfer pad 64 .

The structure of the transistor formed in the third embodiment is substantially the same as that of the first embodiment, but the structures of the gate contacts and capacitors are different. As shown in FIG. 4I, the gate contact of the third embodiment includes: a pad electrode 66c is formed on the substrate 52, and the pad electrode 66c is electrically connected to the gate electrode 66a; a connection pad insulating layer 681 is formed around the boundary of the pad electrode 66c to form a connection pad opening 84b; the connection pad opening 84b penetrates the connection pad insulating layer 681 to expose the pad electrode 66c; the connection pad block 82c is electrically connected to the pad electrode 66c through the connection pad opening 84b.

In the third embodiment, there are three capacitors with different structures. The capacitor 62a includes a capacitor lower electrode 66b, which has the same composition as the gate electrode 66a (common with the gate electrode), an insulating layer 681 covering the capacitor lower electrode 66b, and a transparent conductive layer 82b covering the insulating layer 681 . The transparent conductive layer 82b is used as the capacitor upper electrode of the capacitor 62a.

The capacitor 62b includes a capacitor lower electrode 66b, which has the same composition as the gate electrode 66a; an insulating layer 681 covers the capacitor lower electrode 66b; an insulating layer 682 and a semiconductor layer 70 are formed on the insulating layer 681; a doped silicon layer 72. The capacitor upper electrode 74c and the capacitor protection layer 76c are formed on the semiconductor layer 70; and a transparent conductive layer 82d covers the capacitor protection layer 76c. The capacitive protection layer 76c has a capacitive opening 78c, exposing the capacitive upper electrode 74c to the capacitive opening 78c, and the transparent conductive layer 82d fills the capacitive opening 78c and is electrically connected to the capacitive top electrode 74c.

The structure of the capacitor 62c is similar to that of the capacitor 62b, except that the insulating layer 681 of the capacitor 62c has an insulating layer opening 84a to expose the lower electrode 66b of the capacitor, and the insulating layer 682 will fill the insulating layer opening 84a. Then, in the capacitor 62c, the distance between the upper and lower electrodes 64 and 66 of the capacitor will be shortened, and the capacitance value will be larger.

Please refer to FIG. 5 , which is a schematic structural diagram of a fourth embodiment of the present invention. The fourth embodiment is mainly applied to an in-plain-switch (IPS) type TFT-LCD. Because the IPS type TFT-LCD does not need to use a transparent conductive layer, the fourth embodiment of the present invention combines the features of the second and third embodiments—a variety of capacitors can be formed without using a transparent conductive layer. Similarly, the first three yellowing and etching processes of the fourth embodiment are exactly the same as the first three yellowing and etching processes of the third embodiment, and a semi-finished product as shown in FIG. 4F is formed.

As shown in FIG. 5, the fourth photolithography and etching process of the fourth embodiment will remove the protective layer 76, the semiconductor layer 70 and the insulating layer 682 outside the first part 51, the third part 55b, 55c, and directly complete the transistor 60. Capacitor 62b, capacitor 62c and transfer pad 64 can be applied to the manufacture of plane switching TFT-LCD. Because the transparent conductive layer is not used at last, the third portion 55a is not used to form a capacitor, but can be used to form a wire 62a.

The structure of the fourth embodiment of the manufacturing method of the present invention is similar to that of the third embodiment, except that: (1) the protective layer 76 is not formed on the source conductive layer 74a, the drain conductive layer 74b and the capacitor upper electrode 74c. (2) The structure of the fourth embodiment does not include a transparent conductive layer.

The manufacturing method of the present invention is characterized in that the metal layer 74 is deposited on the doped silicon conductive layer 72 , which can reduce the resistance of the transistor 60 and the capacitor 62 , thereby increasing the operation speed of the transistor 60 and the capacitor 62 . When fabricating a plane-switching TFT-LCD, the method of the present invention can even omit the fabricating of the transparent conductive layer 82, which can greatly reduce the fabricating cost and the resistance value of the element. In addition, the method of the present invention can use the same manufacturing process to form a variety of different capacitors without affecting the structure of the transistor 60 and the transfer pad 64, and does not need to change the area of the capacitor region 66, which can increase the selectivity of circuit design. The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (25)

1. A manufacturing method of a thin film transistor flat panel display, the display is manufactured on a substrate, the substrate includes a first part and a second part, the first part includes a transistor region for forming a transistor, and the second part It includes a connection pad area for forming a connection pad, and the manufacturing method includes the following steps: (a) depositing a first metal layer on the substrate surface; (b) defining a pattern of the first metal layer for forming a gate electrode in the transistor region and forming a pad electrode in the connection pad region; (c) forming a first insulating layer on the substrate, defining a pattern of the first insulating layer, forming a connection pad opening in the connection pad region, exposing the pad electrode; (d) sequentially depositing a second insulating layer, a semiconductor layer, a doped silicon conductive layer and a second metal layer on the first insulating layer; (e) Define a channel region in the transistor region, and simultaneously remove the second metal layer and the doped silicon conductive layer in the channel and outside the transistor region, so that the remaining second metal layer in the transistor region is formed a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region, and the semiconductor layer is exposed outside the transistor region; (f) depositing a protective layer over the substrate; and (g) defining the pattern of the protective layer, removing the protective layer outside the first part, so that the semiconductor layer is exposed to the area outside the first part, then, using the protective layer as an etching mask, removing the protective layer not covered by the protective layer Shielding the semiconductor layer and the second insulating layer such that the first insulating layer is exposed in a region outside the first portion and the pad electrode is exposed in the connection pad opening. 2. The method according to claim 1, wherein the substrate further includes a capacitor region for forming a capacitor, and the manufacturing method further comprises the following steps: When defining the pattern of the first metal layer in step (b), a capacitor lower electrode is also formed in the capacitor region; When defining the protective layer pattern in step (g), define a source opening on the source metal layer, define a drain opening on the drain metal layer, remove the source opening and the drain opening the inner protection layer, so that the source metal layer and the drain metal layer of the transistor region are exposed, and the first insulating layer is also exposed in the capacitor region; (h) forming a transparent conductive layer on the substrate, the transparent conductive layer covers the capacitance area, and fills in the source opening, the drain opening and the connection pad opening; and (i) defining the pattern of the transparent conductive layer so that the transparent conductive layer is separated into a source block, a drain block and a connection pad block which are electrically isolated from each other, wherein the source block passes through the source The opening is electrically connected to the source metal layer, the drain block is electrically connected to the drain metal layer through the drain opening, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive layer forms a capacitor top electrode in the capacitor region. 3. A manufacturing method of a flat-panel thin-film transistor display, the display is fabricated on a substrate, the substrate includes a first part, a second part and a third part, the first part includes a transistor region for forming a transistor , the second part includes a connection pad area for forming a connection pad, the third part includes a capacitor area for forming a capacitor, the manufacturing method includes the following steps: (a) depositing a first metal layer on the substrate surface; (b) defining a pattern of the first metal layer for forming a gate electrode in the transistor region, a capacitor bottom electrode in the capacitor region, and a pad electrode in the connection pad region; (c) forming a first insulating layer on the substrate, defining a pattern of the first insulating layer, forming a connection pad opening in the connection pad region, exposing the pad electrode; (d) sequentially depositing a second insulating layer, a semiconductor layer, a doped silicon conductive layer and a second metal layer on the first insulating layer; (e) Define a channel region in the transistor region, and remove the second metal layer and the doped silicon conductive layer in the channel, outside the transistor region and the capacitance region, so that the remaining in the transistor region The second metal layer forms a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region, so that the remaining second metal layer in the capacitance region forms a capacitor upper electrode, exposing the semiconductor layer outside the transistor region and the capacitor region; (f) Depositing a protective layer on the substrate so as to cover the transistor region, the capacitor region and the connection pad region, and the protective layer will fill in the channel region; and (g) To define the pattern of the protection layer, first define a source opening on the source metal layer, define a drain opening on the drain metal layer, define a capacitance opening in the capacitance region, and remove the The protection layer outside the first part and the third part and the protection layer in the source opening, the drain opening and the capacitor opening, so that the semiconductor layer is exposed to the first part and the third part region, and the source metal layer is exposed to the source opening, the drain metal layer is exposed to the drain opening, and the capacitor upper electrode is exposed to the capacitor opening; (h) using the protective layer as an etching mask, simultaneously removing the semiconductor layer and the second insulating layer not covered by the protective layer, so that the first insulating layer is exposed to areas other than the first portion and the third portion , and exposing the pad electrode to the connection pad opening; (i) forming a transparent conductive layer on the entire surface of the substrate, and filling the source opening, the drain opening, the capacitor opening and the connection pad opening with the transparent conductive layer; and (j) defining the pattern of the transparent conductive layer so that the transparent conductive layer is separated into a source block, a drain block and a connection pad block electrically isolated from each other, wherein the source block passes through the source The opening is electrically connected to the source metal layer, the drain block is electrically connected to the drain metal layer through the drain opening, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive The layer is electrically connected to the upper electrode of the capacitor. 4. The method of claim 3, wherein the method further comprises the steps of: When defining the first insulating layer in step (c), an opening in the capacitor insulating layer is formed in the capacitor region, exposing the lower electrode of the capacitor; and In step (d), the second insulating layer fills the opening of the capacitor insulating layer. 5. A thin film transistor flat panel display, comprising: a substrate; A thin film transistor, the thin film transistor includes: a gate electrode is formed on the substrate; A transistor insulating layer and a transistor semiconductor layer are sequentially formed on the gate electrode; A first doped silicon layer and a second doped silicon layer are formed on the semiconductor layer of the transistor, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer is formed on the first doped silicon layer; a drain conductive layer is formed on the second doped silicon layer; and a transistor protection layer covering the channel region, the source conductive layer, and the drain conductive layer; A gate contact, the gate contact comprising: A pad electrode is formed on the substrate, and the pad electrode is electrically connected to the gate electrode; a connection pad insulating layer is formed around the boundary of the pad electrode to form a connection pad opening; The connection pad opening penetrates the connection pad insulation layer to expose the pad electrode; Wherein, the sidewall of the transistor insulating layer is substantially aligned with the sidewall of the transistor semiconductor layer, and the sidewall of the source conductive layer is substantially aligned with the sidewall of the first doped silicon layer. 6. The thin film transistor flat panel display as claimed in claim 5, wherein there is a distance between the sidewall of the source conductive layer and the sidewall of the transistor insulating layer. 7. The thin film transistor flat panel display as claimed in claim 5, wherein the protective layer has a source opening on the source conductive layer, a drain opening on the drain conductive layer, and the thin film transistor liquid crystal display Also includes: a transparent source conductive layer block is electrically connected to the source conductive layer through the source opening; a transparent drain conductive layer block is electrically connected to the drain conductive layer through the drain opening; and A transparent connection pad conductive layer block is electrically connected to the pad electrode through the connection pad opening. 8. The thin film transistor flat panel display as claimed in claim 7, wherein the thin film transistor flat panel display further comprises a capacitor, and the capacitor comprises: a capacitor lower electrode, which has the same composition as the gate electrode; a first insulating layer covering the lower electrode of the capacitor; and A transparent conductive layer covers the first insulating layer. 9. The thin film transistor flat panel display as claimed in claim 7, wherein the thin film transistor flat panel display further comprises a capacitor, and the capacitor sequentially comprises: a capacitor lower electrode, which has the same composition as the gate electrode; a first insulating layer covering the lower electrode of the capacitor; A second insulating layer and a semiconductor layer are formed on the first insulating layer; a doped silicon layer, a capacitor top electrode, and a capacitor protection layer are formed on the semiconductor layer, and the capacitor protection layer has a capacitor opening, so that the capacitor top electrode is exposed in the capacitor opening; and A transparent conductive layer covers the first capacitor protection layer, and the transparent conductive layer fills the capacitor opening and is electrically connected with the upper electrode of the capacitor. 10. The thin film transistor flat panel display as claimed in claim 9, wherein the first insulating layer of the capacitor has a first insulating layer opening, so that the lower electrode of the capacitor is exposed, and the second insulating layer will fill the first insulating layer. Insulation opening. 11. A method for manufacturing a flat-panel thin-film transistor display, the display being manufactured on a substrate, the substrate including a first part and a second part, the first part including a transistor region for forming a transistor, the second Partly includes a connection pad area for forming a connection pad, the manufacturing method includes the following steps: (a) depositing a first metal layer on the substrate surface; (b) defining a pattern of the first metal layer for forming a gate electrode in the transistor region and a pad electrode in the connection pad region; (c) sequentially depositing an insulating layer, a semiconductor layer, a doped silicon conductive layer and a second metal layer on the substrate; (d) defining a channel region in the transistor region, and simultaneously removing the second metal layer and the doped silicon conductive layer in the channel region and outside the transistor region in the first part and in the second part, so that in the The remaining second metal layer in the transistor region forms a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region, and the semiconductor layer is exposed to the transistor Outside the area; (e) Depositing a protective layer on the substrate so as to cover the transistor region and the connection pad region, and the protective layer will fill in the channel region; and (f) defining the pattern of the protection layer, first defining a connection pad opening in the connection pad region, and removing the protection layer outside the first part, outside the second part and in the connection pad opening, so that the semiconductor layer is exposed within the area outside the first portion and the area outside the second portion and the connection pad opening; (g) using the protective layer as an etching mask, simultaneously remove the semiconductor layer and the insulating layer outside the first part and the second part and the connection pad opening that are not shielded by the protective layer, so that the substrate is exposed In the first part and the area outside the second part, the pad electrode is exposed in the connection pad opening. 12. The method of claim 11, wherein the method further comprises the steps of: When defining the protective layer pattern in step (f), define a source opening on the source metal layer, define a drain opening on the drain metal layer, remove the source opening and the drain opening The protection layer inside, so that the source metal layer and the drain metal layer of the transistor region are exposed; (h) forming a transparent conductive layer on the substrate so that the transparent conductive layer fills the source opening, the drain opening and the connection pad opening; and (i) defining the pattern of the transparent conductive layer so that the transparent conductive layer is separated into a source block, a drain block and a connection pad block which are electrically isolated from each other, wherein the source block passes through the source The opening is electrically connected to the source metal layer, the drain block is electrically connected to the drain metal layer through the drain opening, and the connection pad block is electrically connected to the pad electrode through the connection pad opening. 13. The method according to claim 12, wherein the substrate further includes a third portion, the third portion includes a capacitor area for forming a capacitor, and the manufacturing method further comprises the following steps: When defining the pattern of the first metal layer in step (b), a capacitor bottom electrode is further formed in the capacitor region; The insulating layer, the semiconductor layer, the doped silicon conductive layer, and the second metal layer are also formed in the capacitor region during step (c); In step (d), the second metal layer and the doped silicon conductive layer in the third part that do not cover the lower electrode of the capacitor are removed at the same time, so that the semiconductor layer outside the capacitor region is exposed, and the remaining in the capacitor region The second metal layer forms a capacitor upper electrode; When defining the protective layer pattern in step (f), a capacitor opening is formed in the capacitor region, exposing the upper electrode of the capacitor; and In step (h), the transparent conductive layer is also filled into the opening of the capacitor and is electrically connected to the upper electrode of the capacitor. 14. The method of claim 11, wherein the TFT-LCD is a planar rotation TFT-LCD. 15. The method of claim 11, wherein the semiconductor layer is an amorphous silicon layer or a polysilicon layer. 16. A thin film transistor flat panel display comprising: a substrate; A thin film transistor, the thin film transistor includes: a gate electrode is formed on the substrate; A transistor insulating layer and a transistor semiconductor layer are sequentially formed on the gate electrode; A first doped silicon layer and a second doped silicon layer are formed on the semiconductor layer of the transistor, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer is formed on the first doped silicon layer; a drain conductive layer is formed on the second doped silicon layer; and a transistor protection layer covering the channel region, the source conductive layer, and the drain conductive layer; A gate contact, the gate contact comprising: A pad electrode is formed on the substrate, and the pad electrode is electrically connected to the gate electrode; A connection pad insulating layer, a connection pad semiconductor layer, and a connection pad protection layer are all sequentially formed around the boundary of the pad electrode to form a connection pad opening; The connection pad opening penetrates the connection pad insulation layer, the connection pad semiconductor layer, and the connection pad protection layer to expose the pad electrode; A conductive layer is filled into the opening of the connection pad area to electrically connect the pad electrode; Wherein, the sidewall of the transistor insulating layer is substantially aligned with the sidewall of the transistor semiconductor layer, and the sidewall of the source conductive layer is substantially aligned with the sidewall of the first doped silicon layer. 17. The thin film transistor flat panel display as claimed in claim 16, wherein there is a distance between the sidewall of the source conductive layer and the sidewall of the transistor insulating layer. 18. The thin film transistor flat panel display as claimed in claim 16, wherein the thin film transistor flat panel display further comprises a capacitor, the capacitor comprises: a capacitor lower electrode, which has the same composition as the gate electrode; A capacitor insulating layer covering the lower electrode of the capacitor; A capacitor semiconductor layer, a capacitor doped silicon layer, a capacitor upper electrode, and a capacitor protection layer are formed on the capacitor semiconductor layer. The capacitor protection layer has a capacitor opening, so that the capacitor upper electrode is exposed to the capacitor opening. in; and A transparent conductive layer covers the capacitor protective layer, and the transparent conductive layer fills the capacitor opening and is electrically connected with the capacitor upper electrode. 19. The thin film transistor flat panel display as claimed in claim 16, wherein the transistor protective layer has a source opening on the source conductive layer, and has a drain opening on the drain conductive layer, and the thin film transistor LCD monitors also include: a transparent source conductive layer block is electrically connected to the source conductive layer through the source opening; a transparent drain conductive layer block is electrically connected to the drain conductive layer through the drain opening; and A transparent connection pad conductive layer block is electrically connected to the pad electrode through the connection pad opening. 20. A thin film transistor comprising: a substrate; a gate electrode is formed on the substrate; An insulating layer and a semiconductor layer are sequentially formed on the gate electrode; A first doped silicon layer and a second doped silicon layer are both formed on the semiconductor layer, and a channel region is separated between the first and the second doped silicon layer; a source conductive layer and a drain conductive layer are respectively formed on the first doped silicon layer and the second doped silicon layer; and a protective layer covering the channel region, the source conductive layer, and the drain conductive layer; Wherein, the sidewall of the insulating layer is substantially aligned with the sidewall of the semiconductor layer, and the sidewall of the source conductive layer is substantially aligned with the sidewall of the first doped silicon layer. 21. The thin film transistor as claimed in claim 20, wherein there is a distance between the sidewall of the source conductive layer and the sidewall of the insulating layer. 22. The TFT as claimed in claim 20, wherein the passivation layer has a drain opening to expose the drain metal layer. 23. The thin film transistor as claimed in claim 22, wherein the thin film transistor further comprises a transparent electrode formed on the passivation layer, filling the drain opening of the passivation layer, and electrically communicating with the drain metal layer. 24. A method for manufacturing a thin-film transistor flat panel display, the display is manufactured on a substrate, the substrate includes a first part and a second part, the first part includes a transistor region for forming a transistor, and the second part It includes a connection pad area for forming a connection pad, and the manufacturing method includes the following steps: (a) depositing a first metal layer on the substrate surface; (b) defining a pattern of the first metal layer for forming a gate electrode in the transistor region and forming a pad electrode in the connection pad region; (c) sequentially forming a first insulating layer, a second insulating layer, a semiconductor layer, a doped silicon conductive layer and a second metal layer on the substrate; (d) Define a channel region in the transistor region, and simultaneously remove the second metal layer and the doped silicon conductive layer in the channel and outside the transistor region, so that the remaining second metal layer in the transistor region is formed a source metal layer and a drain metal layer, and the source metal layer and the drain metal layer are separated by the channel region, and the semiconductor layer is exposed outside the transistor region; (e) depositing a protective layer over the entire surface of the substrate; (f) defining the pattern of the protective layer, removing the protective layer outside the first part, so that the semiconductor layer is exposed to the area outside the first part, and then, using the protective layer as an etching mask, removing the protective layer not covered by the protective layer masking the semiconductor layer and the second insulating layer such that the first insulating layer is exposed to regions outside the first portion; and (g) defining a pattern of the first insulating layer, forming a connection pad opening in the connection pad region to expose the pad electrode. 25. The method as claimed in claim 24, wherein the substrate further includes a capacitor area for forming a capacitor, and the manufacturing method further comprises the following steps: When defining the pattern of the first metal layer in step (b), a capacitor lower electrode is also formed in the capacitor region; When defining the protective layer pattern in step (f), define a source opening on the source metal layer, define a drain opening on the drain metal layer, remove the source opening and the drain opening the inner protection layer, so that the source metal layer and the drain metal layer of the transistor region are exposed, and the first insulating layer is also exposed in the capacitor region; (h) forming a transparent conductive layer on the substrate, the transparent conductive layer covers the capacitance area, and fills in the source opening, the drain opening and the connection pad opening; and (i) defining the pattern of the transparent conductive layer so that the transparent conductive layer is separated into a source block, a drain block and a connection pad block which are electrically isolated from each other, wherein the source block passes through the source The opening is electrically connected to the source metal layer, the drain block is electrically connected to the drain metal layer through the drain opening, the connection pad block is electrically connected to the pad electrode through the connection pad opening, and the transparent conductive layer forms a capacitor top electrode in the capacitor region.

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