CN1738036A - Integrated circuit or discrete component flat pen bump package structure - Google Patents

Abstract

The invention relates to an integrated circuit or discrete component planar encircling bump type packaging structure, which belongs to the technical field of integrated circuits or discrete components. It includes a base island (1), a chip (2), a functional output pin (3) and a plastic package (5), the functional output pin (3) is distributed on the outer ring of the base island (1), and the chip (2) Placed on the base island (1), it is characterized in that: the base island (1) outside the plastic package (5) and the functional output pin (3) protrude from the surface of the plastic package (5); the base island (1) There is a single base island or multiple base islands; the functional output pin (3) has a single turn or/and multiple turns; the chip (2) has a single or multiple turns. The invention has smooth production, improved yield, low cost, good quality, high reliability and high heat dissipation.

Description

Integrated circuit or discrete component planar surrounding bump package structure

The invention relates to an integrated circuit or a discrete component, in particular to a planar encircling bump package structure for an integrated circuit or a discrete component. It belongs to the technical field of packaging of integrated circuits or discrete components.

Background technique:

Before the present invention was made, the traditional integrated circuit or discrete component packaging forms mainly contained two kinds of quadrilateral non-footed surface mount packages (QFN) and ball array packages (BGA). They each had certain deficiencies, which are now described as follows : Quadruple leadless surface mount package Ball Array Package 1. The matching form of base island and chip A fully etched lead frame with tape is used, but limited by the capacity of the fully etched lead frame, only a single base island can be fabricated in the same package, and the capability of a single base island is limited. The use of plastic circuit substrates can achieve single-base island single chip, single-base island multiple array chips, single-base island multi-layer stacked chips, and multi-base island multiple array chips and multi-base island multi-layer in the same package. Stacked chips are placed, but the cost of the plastic circuit substrate is relatively high. 2. How to separate the output pins from the outside of the plastic package The lead frame with full etching and tape is used, but due to the limitation of the capacity of the full etching lead frame, it is only possible to achieve single-turn or single-row functional output pin distribution outside the plastic package. Due to the use of plastic circuit boards, the distribution of external function output pins can be single-turn, multi-turn, single-row, multi-row, etc.; but there is also the problem of high cost of plastic circuit boards. 3. The protruding performance of the external functional output pin of the plastic package Limited by the ability of the fully etched lead frame with adhesive tape, it is impossible to make the functional output pin outside the plastic package protrude from the bottom of the plastic package; therefore, the soldering ability between the functional output pin and the printed circuit board is relatively poor, and during the soldering process It is easy to cause the problem of solder paste short circuit. Limited by the capacity of the plastic circuit board, it is impossible to directly protrude the functional output pins outside the plastic package from the surface of the plastic package. Therefore, in order to make the output pins protrude, a high-cost solder ball planting process is added. 4. The coplanarity of base island and functional foot The lead frame with full etching and tape is easy to produce the problem that the functional output pin is sunken in the middle of the plastic package during the production process, resulting in a bad patch contact. The method of implanting solder balls at the bottom of the plastic circuit board is adopted, but the solder balls cannot be implanted on the base island, so that the base island and the solder balls often have uneven sizes, resulting in poor contact during placement. In addition, Solder balls also often drop the ball and cause the problem of missing balls. 5. The base island exposes the heat dissipation capacity of the bottom of the colloid The lead frame with full etching and adhesive tape can expose the base island for heat dissipation at the bottom of the plastic package, but cannot protrude from the bottom of the plastic package, and cannot use air to dissipate heat. Using a plastic circuit board can make the base island exposed at the bottom of the plastic package, and the plastic circuit board indirectly conducts heat to the bottom of the base island through leads, and the base island uses the surrounding air to dissipate heat, but the heat dissipation resistance of the air is relatively large , the heat dissipation efficiency is very poor, and the reliability of the plastic circuit board will be seriously affected due to heat accumulation on the plastic circuit board during the wiring process. 6. Chip Single chip: Taking a memory chip as an example, the storage capacity of a single chip is 128MB, and there is only a single chip on the Genesis Island, so the maximum storage capacity is only 128MB. Multiple array chips: For example, a storage chip and a power protection chip are placed on the same base island at the same time, so that the storage chip can be protected from sudden and unstable power supply. 7. Chip and output function pin Single-chip, single-turn or/and single-row: If a small number of I/O (input and output signals) are changed to multi-turn or/and multi-row function output pins for single-turn/row, the package size can be at least four times smaller than the original one-third. The key lies in the different chip or package forms, and the size savings of a single package are also different. Multiple array chips, circles or/and rows: It is possible to integrate one or more chips with different functions according to the needs of the product, and package them into an integrated circuit with multiple array chips, multiple circles or/and multiple rows of functional output pins; Compared with the independent packaging of a single chip, it can save the space of one base to multiple packages. The key is that the size of the package will vary depending on the number of chips arranged in parallel.

Invention content:

The purpose of the present invention is to overcome the above disadvantages and provide a planar encircled bump packaging structure for integrated circuits or discrete components with smooth production, improved yield, low cost, good quality, high reliability, and high heat dissipation.

The object of the present invention is achieved like this: a kind of integrated circuit or discrete component planar surrounding bump type package structure, comprises base island, chip, function output foot and plastic package body, and described function output foot is distributed on the outer surface of base island Circle, the chip is placed on the base island, characterized in that:

The base island outside the plastic package and the functional output pin protrude from the surface of the plastic package;

The base island has a single base island or multiple base islands;

The functional output pin has single-turn or/and multi-turn;

There are single or multiple chips.

Compared with the prior art, the present invention adopts planar bump array package (FBP BGA) and has the following advantages:

1. The matching form of base island and chip:

After the metal substrate is semi-etched and matched with the line finishing layer, it can also achieve single-base island single chip, single-base island multiple chips, and multiple base islands and multiple chips can also be placed in the same package; Moreover, the cost of the metal substrate is relatively low. The cost of the plastic circuit substrate is at least two times higher than the material cost of the metal substrate of the planar bump array package.

2. How to separate the output pins of the external functions of the plastic package:

The metal substrate can be etched twice to easily achieve various distribution methods of the external functional output pins of the plastic package, such as single-turn, multi-turn, etc., and the cost is low.

3. The protruding performance of the external functional output pin of the plastic package

The metal substrate is etched twice to easily achieve the function outside the plastic package. The output pin protrudes from the surface of the plastic package.

4. The coplanarity between the base island and the function output pin:

The metal substrate is etched twice to ensure the absolute coplanarity between the base island and the functional output pins, and there will be absolutely no problems of missing, missing, or recessed functional output pins.

5. The base island exposes the heat dissipation capacity of the bottom of the plastic package

The metal substrate is etched twice so that the base island for heat dissipation is directly exposed and protrudes from the bottom of the plastic package, and the base island and the functional output pin are welded on the printed circuit board together; therefore, while using air for heat dissipation, it also The heat energy converted by the chip due to electrical energy can be dissipated directly and quickly through the printed circuit board.

6. Multi-turn output function pin

According to the needs of the product, it can be packaged into an integrated circuit with multi-turn function output pins; compared with the independent packaging of a single chip, it can save the space of one or more packages.

Description of drawings:

Fig. 1 is a schematic cross-sectional view of the utility model.

Fig. 2 (a), (b) is respectively the plane and O-O elevation layout diagram of Embodiment 2 of the present invention.

Fig. 3 (a), (b) is respectively the plane and O-O elevation layout diagram of Embodiment 4 of the present invention.

Fig. 4(a), (b) are the plane and O-O elevation layout diagrams of Embodiment 13 of the present invention, respectively.

Fig. 5(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 14 of the present invention.

Fig. 6(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 15 of the present invention.

Fig. 7(a), (b) are respectively the plane and O-O elevation layout diagrams of Embodiment 16 of the present invention.

Detailed ways:

Referring to FIG. 1 , a planar encircled bump package structure for integrated circuits or discrete components is mainly composed of a base island 1 , a chip 2 , functional output pins 3 , gold wires 4 and a plastic package 5 . The functional output pins 3 are distributed on the outer circle of the base island 1, and the chip 2 is placed on the base island 1. The gold wire 4 is connected between the chip 2 and the functional output pin 3, and the base island 1, the chip 2, the functional output pin 3 and the gold wire 4 are all encapsulated with a plastic package 5, and the base island 1 outside the plastic package is And the functional output pin 3 protrudes from the surface of the plastic package body 5 . The functional output pin 3 sequentially includes a metal layer 3.1, an activation layer 3.2, a metal substrate layer 3.3, an activation layer 3.4 and a metal layer 3.5 from inside to outside. The surface of the functional output pin 3 protruding from the plastic package 5 is covered by the outer activation layer 3.4 and the outer metal layer 3.5. The base island 1 sequentially includes a metal layer 1.1, an activation layer 1.2, a metal substrate layer 1.3, an activation layer 1.4 and a metal layer 1.5 from inside to outside, and the surface of the base island 1 protruding from the plastic package 5 is covered by an outer activation layer 1.4 And outer metal layer 1.5 coating.

The base island 1 has a single base island or multiple base islands; the functional output pin 3 has a single-turn or/and multi-turn distribution; the chip 2 has a single or multiple chips.

In addition: above-mentioned embodiment 1 also can have several special cases:

1) The function output pin 3 and the base island 1 can also save the inner and outer activation layers 3.2, 3.4 and 1.2, 1.4.

2) Only the bottom end surface of the functional output pin 3 and base island 1 protruding from the plastic package 5 is plated by the outer activation layer 3.4, 1.4 and the outer metal layer 3.5, 1.5, while the rest is not plated.

3) The functional output pin 3 and the base island 1 omit the inner and outer activation layers 3.2, 3.4 and 1.2, 1.4, and the part of the functional output pin 3 and the base island 1 protruding from the plastic package is only covered by the outer layer of metal Layers 3.5, 1.5 are plated, while the rest of the surface part is not plated.

The specific embodiment of the present invention is described in further detail below in conjunction with accompanying drawing:

Embodiment 2: Single base island/multi-turn function output pin/single chip

Referring to Fig. 2, the base island has a single, and the functional output pin of the outer ring of a single base island has multiple turns; there is a single chip on a single base island.

Embodiment 3: Single base island/single-turn function output pin/multi-chip

The base island has a single base, the functional output pin of the outer circle of the single base island has a single circle, there are multiple chips on the single base island, and the arrangement of the multiple chips on the single base island is arranged or/and stacked.

Embodiment 4: Single base island/multi-turn function output pin/multi-chip

Referring to Fig. 3, the base island has a single, and the function output pin of the outer ring of a single base island has multiple turns; there are multiple chips on the single base island, and the arrangement of the multiple chips on the single base island is arranged or/and stack.

Embodiment 5: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, the function output pins of the outer rings of the multiple base islands have a single turn, and each of the multiple base islands has a single chip.

Embodiment 6: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, each of the multiple base islands has a single function output pin on the outer ring, and each of the multiple base islands has a single chip.

Embodiment 7: multi-base island/multi-turn function output pin/multi-chip

There are multiple base islands, each of the multiple base islands has multiple turns of function output pins on the outer circle, and each of the multiple base islands has a single chip.

Embodiment 8: multi-base island/single and multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pin of the outer ring of each base island in the multiple base islands has a single turn or multiple turns, and each base island in the multiple base islands has a single chip.

Embodiment 9: multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single circle. Each of the multiple base islands has multiple chips, and the arrangement of multiple chips on each base island There are permutations or/and stacks.

Embodiment 10: Multi-base island/single-turn function output pin/multi-chip

There are multiple base islands, and the function output pin of each base island outer ring in multiple base islands has a single circle. Islands can be arranged in rows or/and stacked.

Embodiment 11: Multi-base island/multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pins of the outer circle of each base island in the multiple base islands have multiple turns, and there are multiple chips on each base island among the multiple base islands, and the multiple chips have Islands can be arranged in rows or/and stacked.

Embodiment 12: multi-base island/single and multi-turn function output pin/multi-chip

There are multiple base islands, and the function output pins of the outer circle of each base island in the multiple base islands have a single circle or multiple circles. Each base island in the multiple base islands has multiple chips, and multiple chips The arrangements on each base island include permutation or/and stacking.

Embodiment 13: multi-base island/single-turn function output pin/single and multi-chip

Referring to Figure 4, there are multiple base islands, and the functional output pins of the outer rings of multiple base islands have a single circle. Some of the multiple base islands have a single chip on the base island, and some base islands have multiple chips. Chips, multiple chips are arranged or/and stacked on the base island.

Embodiment 14: multi-base island/single-turn function output pin/single and multi-chip

Referring to Fig. 5, there are multiple base islands, and the function output pin of each base island outer ring in multiple base islands has a single circle, and some base islands have a single chip on the multiple base islands, and some base islands have a single chip. There are multiple chips on the island, and the multiple chips are arranged or/and stacked on the base island.

Embodiment 15: multi-base island/multi-turn function output pin/single and multi-chip

Referring to Fig. 6, there are multiple base islands, and the function output pins of each base island outer ring in multiple base islands have multiple turns, some of the multiple base islands have a single chip on the base island, and some base islands have There are multiple chips on the island, and the multiple chips are arranged or/and stacked on the base island.

Embodiment 16: multi-base island/single and multi-turn function output pin/single and multi-chip

Referring to Fig. 7, there are multiple base islands, and the functional output pins of the outer circle of each base island in the multiple base islands have a single turn or multiple turns, and some of the multiple base islands have a single chip on the base island , some base islands have multiple chips, and the arrangement of multiple chips on the base island is arranged or/and stacked.

Claims (20)

1. An integrated circuit or discrete component planar encirclement bump type packaging structure, comprising a base island (1), a chip (2), a functional output pin (3) and a plastic package (5), the functional output pin ( 3) Distributed on the outer ring of the base island (1), the chip (2) is placed on the base island (1), characterized in that: The base island (1) and the functional output pin (3) outside the plastic package (5) protrude from the surface of the plastic package (5); The base island (1) has a single base island or multiple base islands; The function output pin (3) has single-turn or/and multi-turn; There are single or multiple chips (2). 2. An integrated circuit or discrete component planar bump package structure according to claim 1, characterized in that: the functional output pin (3) and the base island (1) sequentially include The metal layer (3.1, 1.1), the metal substrate layer (3.3, 1.3) and the metal layer (3.5, 1.5), the functional output pin (3) protruding from the plastic package (5) and the bottom surface of the base island (1) are all Plated by a metal layer (3.5, 1.5). 3. An integrated circuit or discrete component planar bump package structure according to claim 1, characterized in that: said functional output pin (3) and base island (1) sequentially include The metal layer (3.1, 1.1), the metal substrate layer (3.3, 1.3) and the metal layer (3.5, 1.5), the surface of the functional output pin (3) protruding from the plastic package (5) and the surface of the base island (1) are covered Metal layer (3.5, 1.5) coating. 4. An integrated circuit or discrete element planar bump package structure according to claim 1, characterized in that: said functional output pin (3) and base island (1) sequentially include The metal layer (3.1, 1.1), the activation layer (3.2, 1.2), the metal substrate layer (3.3, 1.3), the activation layer (3.4, 1.4) and the metal layer (3.5, 1.5), protrude from the plastic package (5) Both the functional output pin (3) and the base island (1) are plated by the outer activation layer (3.4, 1.4) and the outer metal layer (3.5, 1.5). 5. An integrated circuit or discrete element planar bump package structure according to claim 1, characterized in that: said functional output pin (3) and base island (1) sequentially include The metal layer (3.1, 1.1), the activation layer (3.2, 1.2), the metal substrate layer (3.3, 1.3), the activation layer (3.4, 1.4) and the metal layer (3.5, 1.5), protrude from the plastic package (5) The surfaces of the functional output pin (3) and the base island (1) are covered by an outer activation layer (3.4, 1.4) and an outer metal layer (3.5, 1.5). 6. According to one of claims 1 to 5, a planar encircled bump package structure for integrated circuits or discrete components, characterized in that: the base island has a single, and the function output of the outer circle of a single base island The feet have multiple turns; there is a single chip on a single base island. 7. An integrated circuit or discrete element planar encircled bump package structure according to any one of claims 1 to 5, characterized in that: the base island has a single, and the function output of the outer circle of a single base island The feet have a single circle, and there are multiple chips on the single-base island, and the arrangement of multiple chips on the single-base island can be arranged or/and stacked. 8. A planar encircled bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: the base island has a single, and the function output of the outer ring of a single base island The feet have multiple turns; there are multiple chips on the single-base island, and the arrangement of multiple chips on the single-base island is arranged or/and stacked. 9. A planar encircled bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and the outer rings of multiple base islands The function output pin has a single turn, and each of the multiple base islands has a single chip. 10. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The functional output pin of the outer ring of the base island has a single ring, and each of the multiple base islands has a single chip. 11. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The functional output pins of the outer ring of the base island have multiple turns, and each of the multiple base islands has a single chip. 12. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The function output pin of the outer ring of the base island has a single turn or multiple turns, and each of the multiple base islands has a single chip. 13. A planar encircled bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and the outer rings of multiple base islands The functional output pin has a single turn, and each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island can be arranged or/and stacked. 14. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The functional output pin of the outer ring of the base island has a single circle, and each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island is arranged or/and stacked. 15. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The functional output pins on the outer ring of the base island have multiple turns, each of the multiple base islands has multiple chips, and the arrangement of the multiple chips on each base island is arranged or/and stacked. 16. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The functional output pins of the outer ring of the base island can be single-turn or multi-turn, each of the multiple base islands has multiple chips, and the arrangement of multiple chips on each base island can be arranged or/and stacked. 17. A planar encircled bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and the outer rings of multiple base islands The functional output pin has a single turn, some of the base islands have a single chip, and some of the base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or/and stacked. 18. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The function output pin of the outer ring of the base island has a single circle, some of the base islands have a single chip, and some base islands have multiple chips, and the arrangement of the multiple chips on the base island can be arranged or arranged. / and stack. 19. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The function output pins of the outer ring of the base island have multiple turns, some of the multiple base islands have a single chip, and some base islands have multiple chips, and the arrangement of the multiple chips on the base island is arranged or arranged. / and stack. 20. A planar bump package structure for integrated circuits or discrete components according to any one of claims 1 to 5, characterized in that: there are multiple base islands, and each of the multiple base islands The function output pin of the outer circle of the base island has a single circle or multiple circles. Among the multiple base islands, some base islands have a single chip, and some base islands have multiple chips. The arrangement of multiple chips on the base island Ways are permutation and/or stacking.

Images