CN1731587A - Vertical type wide bandgap semiconductor device structure and making method - Google Patents

Abstract

The invention discloses a vertical semiconductor device structure and a manufacturing method. It mainly solves the problems of wide bandgap semiconductor materials, high defect density of devices and heat dissipation of high-power devices. A three-dimensional nanostructure is adopted, including a substrate, a vertical single crystal, an epitaxial layer, a metal layer, and a dielectric layer, wherein the vertical single crystal is perpendicular to the surface of the substrate, the epitaxial layer is parallel to the vertical single crystal, and the metal layer is parallel to the surface of the substrate , and there is at least one layer, the dielectric layer is parallel to each metal layer for insulation isolation, the interface between the metal layer and the epitaxial layer forms an ohmic contact or a rectifying contact, and the outer lead is connected on the metal layer. By growing a vertical single crystal on the substrate, epitaxial multi-layer epitaxial material on the surface of the vertical single crystal, and depositing a metal layer on the substrate to form ohmic contact and rectifying contact, the source and gate are drawn out on each metal layer , Drain outer lead. The invention has strong heat dissipation capability and high electrical performance, and can be used in the manufacture of high-power devices and microwave power devices.

Description

Vertical wide bandgap semiconductor device structure and manufacturing method

technical field

The invention belongs to the technical field of microelectronics, relates to semiconductor materials and device manufacturing technologies, and specifically relates to a structure of a semiconductor device and a manufacturing method thereof, which can be used to manufacture high-quality heterostructure devices, high-power devices, etc., and can effectively Reduce the defect density of the material and improve the heat dissipation performance of the device.

Background technique

In recent years, the third-generation wide-bandgap semiconductors represented by silicon carbide SiC and gallium nitride GaN have large bandgap width, high critical field strength, high thermal conductivity, high carrier saturation rate, and two-dimensional heterojunction interface. The excellent characteristics such as high electron gas concentration have attracted widespread attention. In theory, high electron mobility transistor HEMT, heterojunction bipolar transistor HBT, light-emitting diode LED, laser diode LD and other devices made of these materials will have excellent performance that cannot be compared with existing devices. It has conducted extensive and in-depth research and has achieved remarkable results.

However, a major obstacle facing the third-generation wide-bandgap semiconductor materials and related devices is that there is no natural single crystal material, and it is difficult to obtain high-quality materials. At the same time, as the integration and power density of high-power devices based on third-generation wide-bandgap semiconductor materials and microwave power devices are getting higher and higher, their heat dissipation problems are becoming more and more serious, making related devices and circuits The design and manufacture of these materials are also becoming more and more difficult.

Take GaN material as an example. In the late 1980s, Nakamura et al. proposed a two-step method to epitaxially grow GaN materials on sapphire substrates, see Nakamura S, GaN growth using GaN buffer layer, Jpn.J Appl Phys, 1991; 30(10): L 1705 ~L 1707. The solution is to first grow a GaN buffer layer on the sapphire substrate to reduce the high defect density caused by lattice mismatch between sapphire and GaN, and then re-grow GaN material on the buffer layer. Although this solution can obtain GaN materials with better quality than the single-step process, the lattice mismatch between the (0001) growth plane of the GaN material and the (0001) crystal plane of the sapphire substrate is as high as about 13.8%. The defect density of the GaN material grown by the scheme is still as high as 10 ⁸ -10 ¹⁰ /cm ² or more.

In 1993, Detchprohm and Amano et al. further proposed a plan to grow GaN materials on ZnO substrates, see Detchprohm T, Amano H, Hiramatsu K, et al.J.Cryst Growth, 1993, 128:384. The scheme is to first epitaxially layer a layer of ZnO material on the sapphire substrate as the substrate for the epitaxial growth of GaN material; GaN material. Although the ZnO material and the GaN material have similar crystal structures and lattice constants, the ZnO material grown by epitaxy has a higher defect density due to the large lattice mismatch between the ZnO material and the sapphire material. The defect density of the GaN material grown on the bottom is still very high.

In 1999, Xu and Wu et al. proposed a plan to improve heat dissipation by using flip-chip technology, see Xu J J, Wu YF, Keller S, et al.1-8GHz GaN based power amplifier using FC bonding.IEEE MicrowGuided Wave Lett, 1999, 9:277. This solution is a method of flipping the core of the active device and soldering the core to another substrate through bumps. This method is often used in the field of microwave circuits for the assembly of active devices and circuit substrates. For high-power microwave Circuit fabrication, this solution is often used for heat dissipation of devices. Although this solution improves the heat dissipation capability of the device to a certain extent, due to the inherent limitations of the planar process and the continuous improvement of the power density and integration of the device, this solution has been unable to meet the needs of further development of high-power devices. Therefore, to solve these problems, only to find new technical approaches.

content of the invention

The purpose of the present invention is to overcome the deficiencies of the above-mentioned prior art, to provide a structure of a vertical wide bandgap semiconductor device and its manufacturing method, to solve the problem of high defect density and high power of the third generation wide bandgap semiconductor materials and devices. The problem of device heat dissipation can meet the performance requirements of various devices and circuits based on the third-generation wide bandgap semiconductor materials.

The technical solution for realizing the object of the present invention is: on the vertical single crystal on the surface of the substrate, by controlling the materials used in the epitaxial layer and different technological processes, a three-dimensional nanostructure semiconductor device and circuit are produced. The device structure is mainly composed of a substrate, a vertical single crystal, an epitaxial layer, a metal layer, and a dielectric layer; the vertical single crystal is perpendicular to the surface of the substrate, the epitaxial layer is parallel to the vertical single crystal, and the metal layer is parallel to the surface of the substrate , and there is at least one layer, the dielectric layer is parallel to each metal layer for insulation and isolation; the interface between the metal layer and the epitaxial layer forms an ohmic contact or a rectifying contact, and an outer lead is drawn on each metal layer.

The method for making the three-dimensional semiconductor device is carried out as follows:

First, select the substrate, single crystal, epitaxy, metal, and dielectric material according to the device type, and perform surface treatment on the substrate material to make it have a flat surface; secondly, use the colloidal crystal method on the surface-treated substrate material or photolithographic mask method to make the required catalyst template; third, use single crystal material on the substrate material to utilize vapor phase-liquid phase-solid phase VLS, vapor phase-solid phase VS, liquid phase-solid phase LS Mechanism to grow vertical single-crystal nanostructures; fourth, epitaxially grow at least one epitaxial layer on the side of the vertical single crystal by molecular beam epitaxy MBE or metal organic chemical vapor deposition MOCVD technology; fifth, use metal layer materials and dielectric The material forms at least one metal layer and a dielectric layer on the surface of the vertical epitaxial layer through deposition, corrosion and other processes to form the ohmic contact or rectifying contact required by the device; sixth, through directional etching and deposition technology in parallel to the substrate The outer leads of the source, gate and drain are respectively drawn out from each metal layer on the surface of the material to form a basic device unit.

Utilize the method of the present invention, repeat above-mentioned fifth step, can grow a plurality of devices on each vertical single crystal, then the device that constitutes circuit will form a kind of three-dimensional network distribution at this moment, the manufacture of this form of circuit and The design method will be different from the existing planar manufacturing process and design method, which will promote the development of semiconductor manufacturing and design technology from the traditional 2D field to the 3D field.

The above-mentioned semiconductor device structure, wherein the vertical single crystal can be a columnar single crystal, or a ribbon single crystal or other structures with vertical morphology, the side of the vertical single crystal is the substrate for growing the epitaxial layer, and the epitaxy has at least One layer of epitaxial layer.

The above-mentioned semiconductor device structure, wherein the surface of the outermost epitaxial layer forms an alternating structure of multi-layer metal layers and dielectric layers sequentially from bottom to top, that is, the first metal layer and the first dielectric layer, the second metal layer and the second dielectric layer , the third metal layer.

The semiconductor device structure above, wherein the interface between the metal layer and the outermost epitaxial layer forms an ohmic contact or a rectifying contact is formed by the first metal layer and the outermost epitaxial layer forming an ohmic contact to form a source; the second metal layer and the outermost The epitaxial layer forms a rectifying contact to form a gate; the third metal layer and the outermost epitaxial layer form an ohmic contact to form a drain.

If the above-mentioned semiconductor device structure uses a conductive substrate material, the conductive substrate can be used to replace the first metal layer to form two metal layers, that is, the conductive substrate and the outermost epitaxial layer form an ohmic contact to form a source.

Because the present invention adopts the three-dimensional device boundary structure, the surface area of the vertical single crystal array grown on the liner material per unit area is much larger than the surface area of the substrate material, so the same device density, device type and the same In the environment, its heat dissipation capability will be much higher than that of the circuit or device obtained by the planar process; at the same time, since the device is fabricated on a vertical single crystal with a very low defect density, if the material for epitaxy has the same or similar thermal conductivity as the vertical single crystal Crystal structure, lattice constant, thermal expansion coefficient and other parameters, the lattice mismatch at the interface between the epitaxial layer and the vertical single crystal will be greatly reduced, and the defect density in the epitaxial layer material will also be greatly reduced, so that it is difficult to obtain by other methods. high-quality epitaxial single crystal material; in addition, due to the selection of high thermal conductivity substrate material and vertical single crystal material in the manufacturing process of the device, and the dielectric material between the metal layers can be etched away using air as the medium, the use of air Heat dissipation by convection can further improve the heat dissipation capacity of devices and circuits.

Description of drawings

Fig. 1 is the structural sectional view of device of the present invention

Fig. 2 is the fabrication flowchart of device of the present invention

Fig. 3 is the sectional view of the AlGaN/GaN HFET single-tube device based on the ZnO nano columnar single crystal of the present invention

Fig. 4 is the sectional view of the AlGaN/GaN HFET single-tube device based on the ZnO nanoribbon single crystal of the present invention

Fig. 5 is the sectional view of the AlGaN/GaN microwave power device based on the arrayed ZnO nano columnar single crystal of the present invention

Detailed ways

Referring to Fig. 1, the device structure of the present invention is composed of a substrate, a vertical single crystal, an epitaxial layer, a metal layer, and a dielectric layer.

The substrate is the base of the entire device, and various devices are fabricated on its surface. The vertical single crystal grows vertically on the surface of the substrate, and the vertical single crystal can be a columnar single crystal with a hexagonal cross section, or a ribbon single crystal with a quadrangular cross section or other structures with vertical morphology. The side of the vertical single crystal is used as a substrate for growing epitaxial layers, and multiple layers of epitaxial layers with different thicknesses are epitaxially extended on the side of the vertical single crystal. Each epitaxial layer is parallel to the side of the vertical single crystal to form a vertical epitaxial layer perpendicular to the substrate. The surface of the outermost epitaxial layer is an alternating structure of multiple metal layers and dielectric layers from bottom to top, for example, the first metal layer 1 and the first dielectric layer 1, the second metal layer 2 and the second dielectric layer 2, the third Metal layer 3. The interface between different metal layers and the outermost epitaxial layer forms an ohmic contact or a rectifying contact. For example, the first metal layer forms an ohmic contact with the outermost epitaxial layer to form a source; the second metal layer forms a rectifying contact with the outermost epitaxial layer. The contact forms the gate; the third metal layer forms an ohmic contact with the outermost epitaxial layer to form the drain. The role of each dielectric layer is to insulate and isolate each metal layer, and to support the deposition of the metal layer. Outer leads of the source, gate and drain are respectively drawn out on each metal layer.

Referring to Fig. 2, the specific steps of making the three-dimensional semiconductor device are:

The first step is to select the epitaxial layer material first, then select the vertical single crystal material, then select the substrate material, and finally select the metal layer material and dielectric material according to the outermost epitaxial layer material;

The selection of the epitaxial material: first select the material according to the requirements of the device and circuit, that is, select the epitaxial layer material with high thermal conductivity for the device and circuit with high heat dissipation capability, and select the epitaxial layer material with high mobility for the circuit with high speed requirement ; Then determine the growth crystal direction of the epitaxial layer material to optimize the device performance.

The material selection of the vertical single crystal: first, select the vertical single crystal material with the same crystal structure according to the selected epitaxial layer material; secondly, select the vertical single crystal material with the smallest lattice mismatch between the side surface and the growth plane of the epitaxial layer and determine the vertical single crystal material. The growth direction of the crystal; finally, a vertical single crystal material with high thermal conductivity is selected.

The selection of the substrate material: first, according to the selected vertical single crystal material, select the substrate material that meets the vertical single crystal growth conditions; secondly, select the substrate material with high thermal conductivity.

The selection of the metal material: according to the selected outermost epitaxial layer material, select a metal material that can form a good ohmic contact or rectifying contact with it.

The selection of the dielectric material: firstly, select the medium with insulating ability; secondly, select the dielectric material with high thermal conductivity.

According to the principle of selecting various materials, the epitaxial layer material selected by the present invention can be GaN, AlGaN, ZnO, GaAs, AlGaAs, etc.; the vertical single crystal material selected can be ZnO, GaN, etc. according to the difference of the epitaxial layer material; The outer substrate material can be polycrystalline sapphire, single crystal sapphire, single crystal GaN, etc.; the selected metal layer can be Al, Au, Ti/Ag, etc. according to the epitaxial layer material and contact type; the selected dielectric material can be SiO ₂ , Si ₃ N ₄ , air, etc.

The second step is to carry out surface treatment on the selected substrate material to make it have a flat and smooth surface;

The third step is to make a catalyst template on the surface-treated substrate material according to the needs of the device and the circuit by using the colloidal crystal method or the method of photolithography mask;

The fourth step is to use the vertical single crystal material to grow vertical single crystals on the substrate material using vapor-liquid-solid VLS, vapor-solid VS, and liquid-solid LS mechanisms; the distribution of vertical single crystals , density, geometry and other parameters can be controlled by growth conditions, catalyst type, substrate crystal orientation, etc.;

The fifth step is to use the epitaxial layer material to epitaxially grow at least one epitaxial layer on the surface of the vertical single crystal by MBE or MOCVD, and control the thickness, conductivity type, composition and other parameters of the epitaxial layer by controlling the epitaxial time, environment and other factors to adjust the device characteristics;

The sixth step is to use metal layer materials and dielectric materials on the substrate surface perpendicular to the epitaxial layer to form three layers of metal layers and two layers of dielectric layers through electron beam evaporation, thermal evaporation and corrosion processes to make ohmic contacts or rectifiers. Contact, and according to the heat dissipation needs, the dielectric layer can be etched away by etching to improve the heat dissipation capacity of the device;

In the seventh step, the outer leads of the source, gate and drain are respectively drawn out on each metal layer parallel to the surface of the substrate material by directional etching and deposition.

Example 1

The invention manufactures a vertical single-tube AlGaN/GaN HFET device based on ZnO nano columnar single crystal.

Epitaxial layer material selection: AlGaN, GaN.

Vertical single crystal material selection: ZnO.

Substrate material selection: (2-1-10) crystal face of single crystal sapphire.

Metal material selection: Au, Ti/Ag, Al.

Dielectric material selection: SiO ₂ .

Referring to Figure 3, the structure and manufacturing process of the device in this example are as follows:

1. Growth of ZnO nano-columnar single crystal

The first step is the fabrication of monolayer self-assembled submicron sphere arrays.

Select sapphire as the substrate. The colloidal crystal method is used to fabricate the submicron sphere array, and the selected colloidal crystal is polystyrene submicron sphere, and the diameter of the polystyrene sphere is about 895 nm. First, ultrasonically degrade the substrate for 20 minutes, and then perform annealing treatment at about 1000 degrees Celsius for about 3 hours in an air atmosphere to obtain a flat and hydrophilic substrate surface; then drop a few drops on the surface For the solution containing polystyrene spheres, wait for a few minutes to make the solution diffuse evenly, slowly put it into deionized water, and take it out after standing for a few minutes to obtain a monolayer self-assembled submicron sphere array.

The second step is the fabrication of the catalyst template.

First, gold particles are sputtered or thermally evaporated onto the single-layer self-assembled submicron sphere array obtained in the first step; then, the polystyrene spheres are etched away with toluene solution to obtain the required catalyst on the surface of the substrate material template.

The third step is to grow ZnO nano columnar single crystal.

In this example, ZnO nano-columnar single crystals are grown by VLS mechanism. Its size is controlled by growth temperature, pressure, time, etc. The raw materials used include ZnO powder and graphite powder of equal mass, wherein the graphite powder is used to reduce the reaction temperature required for growth. First, mix the raw materials and put them on the alumina boat in the center of the alumina test tube, and at the same time, the substrate material with the catalyst template is placed in the downstream position of the alumina test tube air flow; then, use a horizontal tube furnace at 50 per minute Heat the aluminum test tube to 950°C at a rate of 20°C for 20 to 30 minutes with Ar as the carrier gas; finally, close the tube furnace and cool to room temperature in an argon atmosphere.

The obtained ZnO nano-column single crystal is perpendicular to the surface of the substrate material and has a hexagonal columnar crystal shape, and the crystal orientations of the six sides of the ZnO nano-columnar single crystal are [2-1-10] or [0001]. The ZnO nano-columnar single crystal has a height of about 1500 nm and a diameter of about 200 nm.

The obtained sample is ultrasonically degraded in ethanol to reduce the density of the ZnO nano-columnar single crystal, and obtain the desired single ZnO nano-columnar single crystal.

2. Epitaxial growth of GaN and AlGaN epitaxial layers

In this example, GaN and AlGaN epitaxial layers are epitaxially grown by MBE method.

Using the MBE/MOCVD method, a non-doped GaN epitaxial layer is first epitaxially grown on the surface of the columnar ZnO nano-columnar single crystal;

Then, an n-type doped AlGaN epitaxial layer is epitaxially deposited on the surface of the GaN epitaxial layer.

3. Production of the first metal layer, the second metal layer, the third metal layer and the dielectric layer

First, the first metal layer is formed on the substrate by vacuum and electron beam evaporation of Al and Ti/Ag, and the first metal layer forms an ohmic contact with the AlGaN epitaxial layer to form a source.

Next, deposit a layer _of SiO on the first metal layer parallel to the substrate to form an insulating layer;

Then, a second metal layer is formed on the dielectric layer by vacuum and electron beam evaporation of Au, and the second metal layer forms a rectifying contact with the AlGaN epitaxial layer to form a gate.

Next, deposit a layer _of SiO on the second metal layer parallel to the substrate to form an insulating layer;

Finally, the third metal layer is fabricated by the same method as that of the source electrode, and the third metal layer forms an ohmic contact with the AlGaN epitaxial layer to form the drain electrode.

4. Device formation

First, use directional etching technology to etch the periphery of the ZnO nano-columnar single crystal to form a stepped structure with different heights on each metal layer parallel to the substrate;

Then, deposit Cu or Al on the corresponding steps to form external electrodes and connect external leads.

Compared with the HFET device prepared by MOCVD epitaxy on sapphire, the defect density of the material of the HFET device prepared by this method is significantly reduced, so the performance of the device is greatly improved.

Example 2

The invention manufactures a vertical single-tube AlGaN/GaN HFET device based on ZnO nanoribbon single crystal.

Epitaxial layer material selection: AlGaN, GaN.

Vertical single crystal material selection: ZnO.

Substrate material selection: polycrystalline sapphire.

Metal material selection: Au, Ti/Ag, Al.

Dielectric material selection: Si ₃ N ₄ .

Referring to Figure 4, the structure and manufacturing process of the device in this example are as follows:

1. Growth of ZnO nanoribbon single crystal

In this example, the ZnO nanoribbon single crystal is grown through the VS mechanism, and the selected substrate is sapphire polycrystalline material. The raw materials used are ZnO powder and 1% Li ₂ O powder. First, the raw materials are mixed and placed on the alumina boat in the center of the alumina test tube, while the sapphire polycrystalline substrate material is placed at the downstream position of the alumina test tube airflow, and the tube furnace is evacuated to about 10 ^-3 Torr to remove residual oxygen; then, use a horizontal tube furnace to heat it to 1350 degrees at a rate of 20 degrees per minute, and keep it at a pressure of 200 mbar for 120 minutes, during which Ar is the carrier gas; finally, close the tube furnace and cooled to room temperature in an argon atmosphere.

The obtained nanoribbon-shaped single crystal is perpendicular to the surface of the substrate material, and its appearance is a quadrilateral ribbon-shaped crystal. The crystal directions of the sides of the ZnO nanoribbon-shaped single crystal are [01-10] and [0001] directions, and the nanoribbon-shaped single crystal The height is about 10 microns and the width is 2 microns.

The obtained sample was ultrasonically degraded in ethanol to reduce the density of the ZnO nanoribbon single crystal, and obtain the desired single ZnO nanoribbon single crystal.

2. Epitaxial growth of GaN and AlGaN epitaxial layers

In this example, GaN and AlGaN epitaxial layers are epitaxially grown by MBE method.

Using the MBE/MOCVD method, a non-doped GaN epitaxial layer is first epitaxially grown on the surface of the ZnO nanoribbon single crystal;

Secondly, a non-doped AlGaN epitaxial layer is epitaxially deposited on the surface of the GaN epitaxial layer;

Then, an n-type doped AlGaN epitaxial layer is epitaxially deposited on the surface of the AlGaN epitaxial layer.

3. Production of the first metal layer, the second metal layer, the third metal layer and the dielectric layer

First, the first metal layer is formed on the substrate by vacuum and electron beam evaporation of Al and Ti/Ag, and the first metal layer forms an ohmic contact with the AlGaN epitaxial layer to form a source.

Next, a layer of Si ₃ N ₄ is deposited on the first metal layer parallel to the substrate to form an insulating layer.

Then, a second metal layer is formed on the dielectric layer by vacuum and electron beam evaporation of Au, and the second metal layer forms a rectifying contact with the AlGaN epitaxial layer to form a gate.

Next, deposit a layer of Si ₃ N ₄ on the second metal layer parallel to the substrate to form an insulating layer;

Finally, the third metal layer is fabricated by the same method as that of the source electrode, and the third metal layer forms an ohmic contact with the AlGaN epitaxial layer to form the drain electrode.

4. Device formation

Firstly, the directional etching technique is used to etch the periphery of the ZnO nanoribbon single crystal to form a stepped structure with different heights on each metal layer parallel to the substrate.

Then, deposit Cu or Al on the corresponding steps to form external electrodes and connect external leads.

Example 3

The invention manufactures an air-isolated vertical mesh AlGaN/GaN microwave power device based on arrayed ZnO nano-column single crystals.

Epitaxial layer material selection: AlGaN, GaN

Vertical single crystal material selection: ZnO

Substrate material selection: n-type doped GaN conductive material;

Metal material selection: Au, Ti/Ag, Al

Medium material selection: air

Referring to Figure 5, the structure and production process of this example are as follows:

1. Growth of arrayed ZnO nanocolumnar single crystals

The first step, catalyst template making

First, a thin layer of Au catalyst is deposited on the GaN substrate by thermal evaporation;

Then, according to the distribution density and heat dissipation requirements of the device, design and make a photolithography mask;

Finally, a layer of photoresist is covered on the surface of the Au catalyst layer, photolithography is carried out and the remaining photoresist is etched away, leaving a network-shaped distribution of the catalyst layer.

The second step is the growth of ZnO nano columnar single crystal array. The steps adopted are identical to Example 1.

The difference from Example 1 is that no ultrasonic degradation in ethanol is required after the nano-columnar single-crystal array is finally obtained, so as to maintain the integrity of the nano-columnar single-crystal array.

2. Epitaxial growth of GaN and AlGaN materials

The epitaxial technology of GaN and AlGaN materials is the same as that adopted in Example 1.

3. Fabrication of the first metal layer, the second metal layer and the dielectric layer

First, a layer of _SiO2 is deposited on the substrate to form an insulating layer.

Next, a first metal layer is formed on the dielectric layer by vacuum and electron beam evaporation of Au, and the first metal layer forms a rectifying contact with the AlGaN epitaxial layer to form a gate.

Then, deposit a layer of SiO ₂ on the second metal layer parallel to the substrate to form an insulating layer.

Finally, a second metal layer is formed on the Al and Ti/Ag dielectric layer by vacuum and electron beam evaporation, and the second metal layer forms an ohmic contact with the AlGaN epitaxial layer to form a drain.

In this example, the source electrode is formed by the ohmic contact formed by the n-type GaN conductive substrate and the epitaxial layer material.

After each metal layer is manufactured, the SiO ₂ dielectric material between the metal layers is removed by selective etching to form an air isolation structure.

4. Device formation

First, the periphery of the ZnO nano-columnar single-crystal array is etched by directional etching technology to form stepped structures with different heights on each metal layer parallel to the substrate.

Second, deposit Cu or Al on the corresponding steps to form external electrodes and connect external leads.

All the device units on the ZnO nano-column single crystal of the device constructed by this method are connected in parallel, and the total power of the prepared microwave power device is the sum of the power of all devices grown on the ZnO nano-column single crystal. Therefore, its power density is the density of ZnO nano-columnar single crystal multiplied by the power of each device.

The microwave device formed by this method has a larger surface area when the device density is the same as that of the microwave power device produced by the traditional planar process. At the same time, the heat dissipation capacity of the device will be greatly improved because the devices are separated by air.

For those skilled in the art, after understanding the content and principles of the present invention, they can make various amendments and changes in form and details according to the methods of the present invention without departing from the principles and scope of the present invention. But these amendments and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims (6)

1. A vertical wide bandgap semiconductor device structure is characterized in that a three-dimensional nanostructure is adopted, including a substrate, a vertical single crystal, an epitaxial layer, a metal layer, and a dielectric layer; the vertical single crystal is perpendicular to the substrate surface, The epitaxial layer is parallel to the vertical single crystal, the metal layer is parallel to the surface of the substrate, and there is at least one layer, and the dielectric layer is parallel to each metal layer for insulation isolation; the interface between the metal layer and the epitaxial layer forms an ohmic contact or Rectify the contacts and lead out the outer leads on each metal layer. 2. semiconductor device structure according to claim 1, it is characterized in that vertical single crystal can adopt columnar single crystal, also can ribbon single crystal or other have the nanostructure of vertical shape, the side of this vertical single crystal is growth epitaxy layers of the substrate, in turn epitaxially have at least one epitaxial layer. 3. The semiconductor device structure according to claim 1 or 2, characterized in that the surface of the outermost epitaxial layer forms an alternating structure of multilayer metal layers and dielectric layers sequentially from bottom to top, that is, the first metal layer and the first Dielectric layer, second metal layer and second dielectric layer, third metal layer. 4. The semiconductor device structure according to claim 1 or 3, characterized in that the interface between the metal layer and the epitaxial layer forms an ohmic contact or a rectifying contact is formed by the first metal layer and the outermost epitaxial layer forming an ohmic contact, forming a source ; A rectifying contact is formed by the second metal layer and the outermost epitaxial layer to form a gate; an ohmic contact is formed by the third metal layer and the outermost epitaxial layer to form a drain. 5. The semiconductor device structure according to claim 1 or 3, characterized in that the first metal layer can be replaced by a conductive substrate, that is, the conductive substrate and the outermost epitaxial layer form an ohmic contact to form a source. 6. make the method for claim 1 semiconductor device, carry out as follows: The first step is to select the substrate material, vertical single crystal material, epitaxial layer material, metal layer material and dielectric material according to the device type, and perform surface treatment on the selected substrate material to make it have a flat surface; The second step is to make a catalyst template on the surface-treated substrate material according to the needs of the device and the circuit by using the colloidal crystal method or the method of photolithography mask; The third step is to use vertical single crystal materials to grow vertical single crystal nanostructures on the substrate material by using vapor-liquid-solid VLS, vapor-solid VS, and liquid-solid LS mechanisms; The fourth step is to use the epitaxial layer material to epitaxially grow at least one epitaxial layer on the surface of the vertical single crystal by molecular beam epitaxy MBE or metal organic chemical vapor deposition MOCVD; The fifth step is to use the metal layer material and the dielectric material to form at least one layer of metal layer and dielectric layer on the substrate surface perpendicular to the epitaxial layer through deposition and corrosion processes to form the ohmic contact or rectifying contact of the device; In the sixth step, the outer leads of the source, gate and drain are respectively drawn out on each metal layer parallel to the surface of the substrate material by directional etching and deposition to form basic device units.

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