CN106876467A - MISFET devices based on vertical-channel and preparation method thereof - Google Patents

Abstract

The invention discloses a MISFET (metal-insulator dielectric semiconductor field effect transistor) device based on a vertical channel and a preparation method thereof. The MISFET device includes a source, a drain, a gate and an MIS structure, the axis of the MIS structure is substantially perpendicular to a selected plane, the MIS structure includes a semiconductor structure and an insulating medium arranged around the semiconductor structure, and in the A channel is formed at the interface between the semiconductor structure and the insulating medium, the source and the drain are electrically connected through the channel, and the gate is distributed between the source and the drain. The MISFET device of the invention has the advantages of good gate control capability, high operating frequency, low process difficulty, easy manufacture, high yield and the like.

Description

MISFET device based on vertical channel and its preparation method

technical field

The invention relates to a semiconductor device, in particular to a vertical channel-based MISFET (Vertical Channel Heterostructure Metal-Insulator-Semiconductor Field-effect Transistor, VC-MISFET) device and a preparation method thereof.

Background technique

With the development of microelectronics technology, CMOS devices and integrated circuits have entered the so-called post-Moore era, that is, the development of integrated circuits has gradually deviated from the curve of "Moore's Law". Especially when the gate length and channel length of the device are getting shorter and shorter, and the gate dielectric layer is getting thinner and thinner, the "short channel effect" and "DIBL effect" (Drain Induced Barrier Lowering, the potential barrier introduced by the drain terminal) Reduced) and source-drain direct tunneling, etc., making device size reduction more and more difficult. And because the gate length is shortened, the gate control ability is reduced, the subthreshold swing of the device and the switch current ratio are reduced, and a series of problems such as increased power consumption are brought about. In order to solve the above problems, researchers have proposed solutions such as Si-based Fin-FETs, Si-based vertical channel devices, and nanowire-based vertical devices. But these solutions still have some drawbacks. For example, Fin-FET still has to rely on photolithography to obtain smaller gate lengths. As another example, devices based on Si nanowires must be locally doped, which increases the difficulty of the process. For another example, Si-based vertical channel devices can first form multiple layers of different doping types and then etch to form a vertical channel structure. However, this undoubtedly increases the complexity of the process, and the Si material system due to its material properties Due to the limitation, the performance in terms of high pressure resistance, high temperature resistance, radiation resistance, etc. is not ideal.

Contents of the invention

The main purpose of the present invention is to provide a kind of MISFET (Metal-Insulator-Semiconductor Field-effect Transistor, metal-insulator dielectric or oxide semiconductor field-effect transistor) device and preparation method thereof based on vertical channel, to overcome prior art insufficient.

In order to realize the above-mentioned purpose of the invention, the present invention has adopted following technical scheme:

An embodiment of the present invention provides a MISFET device based on a vertical channel, including a source, a drain, a gate, and an MIS structure, wherein the MIS structure includes at least one semiconductor structure and an insulating medium surrounding the semiconductor structure, and A channel is formed at the interface between the semiconductor structure and the insulating medium, the axis of the channel is substantially perpendicular to a selected plane, the source and the drain are electrically connected through the channel, and the gate distribution between source and drain.

In some preferred implementations, the MISFET device includes a plurality of semiconductor structures distributed in an array, and a channel array composed of a plurality of channels is formed between the plurality of semiconductor structures and the insulating medium.

In some preferred implementations, at least one of the source, drain and gate is parallel to the selected plane. Further, the source and the drain form ohmic contacts with the semiconductor structure.

Further, the material of the semiconductor structure may be selected from group III-V semiconductors.

The embodiment of the present invention also provides a method for manufacturing a vertical channel-based MISFET device, which includes:

An MIS structure is formed on the main plane of the substrate, the MIS structure includes at least one semiconductor structure and an insulating medium disposed around the semiconductor structure, and a channel is formed at the interface between the semiconductor structure and the insulating medium, and the channel's the axis is substantially perpendicular to a selected plane;

The source, the gate and the drain are made, and the source and the drain are electrically connected through the channel, and the gate is distributed between the source and the drain.

In some preferred embodiments, the preparation method further includes: forming a plurality of semiconductor structures and an insulating medium distributed in an array on the main plane of the substrate, and forming a space between the plurality of semiconductor structures and the insulating medium A channel array composed of a plurality of channels.

In some preferred implementations, at least one of the source, drain and gate is parallel to the selected plane. Further, the source and the drain form ohmic contacts with the semiconductor structure.

Further, the material of the semiconductor structure may be selected from group III-V semiconductors.

Compared with the prior art, the present invention has at least the following advantages:

(1) The gate of the MISFET device of the present invention can fully surround the channel, so the gate control capability can be improved to the greatest extent.

(2) The gate length of the MISFET device of the present invention is determined by the thickness of the deposited gate metal, so its limit thickness can reach the thickness of a monoatomic layer, that is, it can break through the limit of photolithography, and then can greatly improve the operating frequency of the device.

(3) Because the MISFET device of the present invention can form an ohmic contact through high-temperature alloying, the MISFET device of the present invention does not need to do local doping of the semiconductor at the source and drain contacts, which simplifies the process;

(4) When the MISFET device of the present invention is manufactured, it is not necessary to consider the overlap problem of gate, drain and source wires like the existing planar structure device, which can greatly simplify the process difficulty and improve the yield.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic diagram of a three-dimensional structure of a vertical channel-based MISFET device in a typical embodiment of the present invention.

FIG. 2 is a front view of a vertical channel-based MISFET device in an exemplary embodiment of the present invention.

FIG. 3 is a top view of a vertical channel-based MISFET device in an exemplary embodiment of the present invention.

FIG. 4 is a left side view of a vertical channel-based MISFET device in an exemplary embodiment of the present invention.

FIG. 5 is a front view of a vertical channel-based MISFET device in another exemplary embodiment of the present invention.

FIG. 6 is a top view of a vertical channel-based MISFET device in another exemplary embodiment of the present invention.

FIG. 7 is a left side view of a vertical channel-based MISFET device in another exemplary embodiment of the present invention.

detailed description

A vertical channel-based MISFET device (VC-MISFET) provided by an aspect of the embodiments of the present invention may include a source, a drain, a gate, and an MIS structure, and the MIS structure includes at least one semiconductor structure and a surrounding semiconductor structure An insulating medium is provided, and a channel is formed at the interface between the semiconductor structure and the insulating medium, the axis of the channel is substantially perpendicular to a selected plane, and the source and drain are electrically connected through the channel , the gate is distributed between the source and the drain.

The aforementioned "substantially perpendicular to" means that the axis of the channel forms an angle of 90° or close to 90° with the selected plane, that is, the channel can stand vertically or be inclined relative to the selected plane Standing manner set.

Further, the axis of the MIS structure is substantially perpendicular to the selected plane.

Wherein, the MIS structure may be columnar, and its radial section may be one of circular, regular hexagonal, triangular or other closed polygons. That is, the MIS structure may be in the shape of a column, a prism, or the like.

Further, the semiconductor is columnar, and its radial cross-sectional shape may include regular or irregular shapes such as polygons or circles, but is not limited thereto.

Further, the semiconductor structure is a nanocolumn, which can make the device have better performance.

In some preferred implementations, the insulating medium is arranged coaxially with the semiconductor structure.

Further, the source and the drain are arranged at intervals along the axial direction of the channel, and the gate is arranged between the source and the drain. In this way, the source, drain, and gate are non-coplanar, so there is no need to consider issues such as overlap of gate, drain, and source leads during fabrication, which greatly simplifies the process difficulty.

In some implementations, the source and drain may be disposed at both ends of the channel, respectively. Also, the positions of the source and the drain can be interchanged.

Further, the source and the drain form an ohmic contact with the semiconductor structure, so that the source and the drain can be electrically connected through a channel.

In some preferred embodiments, the distance between the gate and the source is smaller than the distance between the gate and the drain, so as to obtain a larger breakdown voltage.

In some preferred embodiments, the gate is disposed around the channel. Further, the gate is arranged around the MIS structure. That is to say, the gate realizes a full-angle surround of the channel, so that the gate control capability can be maximized.

In some preferred embodiments, at least one of the source, the drain and the gate is parallel to the selected plane, so that the MISFET device does not need to consider the gate as in the existing planar structure device when making the MISFET device. The overlapping problem of lead wires of electrodes, drain electrodes, and source electrodes can greatly simplify the process difficulty and improve the yield.

Further preferably, the source, the drain and the gate are all parallel to the selected plane, which can further simplify the manufacturing process of the source, the drain and the gate, and reduce the manufacturing cost.

Further, in order to avoid large gate-source and gate-drain parasitic capacitances, the overlapping area between the gate and the source and between the gate and the drain (which can also be considered as the gate and the source and/or Or the overlapping area of the orthographic projection of the drain on the selected plane) should be as small as possible.

Further, the length and diameter of the channel can be set correspondingly according to actual needs.

In some more specific embodiments, the length of the channel can reach the nanometer scale, and when it is smaller than a qualified value, the device will have better performance, for example, to produce performance such as ballistic transport.

Further, the length of the gate (that is, the thickness in the axial direction of the channel) can be controlled by the deposition thickness of the gate metal, so it can be extremely small, and can even reach the thickness of a single electron layer, which is a breakthrough in photolithography. Therefore, the operating frequency of the device can be greatly increased and extended to the terahertz band.

Similarly, for the source and drain, the length (that is, the thickness in the axial direction of the channel) can also be controlled by the deposition thickness of the source metal and the drain metal.

In some preferred implementations, the MISFET device includes a plurality of semiconductor structures distributed in an array, and a channel array composed of a plurality of channels is formed between the plurality of semiconductor structures and the insulating medium (also can be called channel clusters), which can increase the device current. Apparently, by controlling the number of the channel arrays, etc., precise control of the device current can also be realized. Further, the channel array may adopt a dot matrix structure known in the industry.

In some embodiments, at least one of the source electrode and the drain electrode and the gate electrode may or may not remain an isolation insulating dielectric layer. Preferably, there is no isolation insulating dielectric layer between any one of the source electrode and the drain electrode and the gate electrode. Further, the material of the isolation insulating dielectric layer can be selected from commonly used materials in the industry such as silicon dioxide, silicon nitride, and aluminum oxide.

In some specific implementation cases, the source electrode includes a source contact ring, and the source contact ring is arranged around the channel. Further, the source contact ring may also be electrically connected to the source lead pad via a connection wire.

In some more specific implementation cases, the drain includes a drain contact ring, and the drain contact ring is disposed around the channel. Further, the drain contact ring may also be electrically connected to the drain lead pad via a connection wire.

In some more specific implementation cases, the gate includes a gate contact ring, and the gate contact ring is arranged around the channel. Further, the gate contact ring may also be electrically connected to the gate lead pad via connecting wires.

Furthermore, at least one of the aforementioned source contact ring, drain contact ring and gate contact ring is arranged coaxially with the channel.

Furthermore, at least one of the aforementioned source contact ring, drain contact ring and gate contact ring is parallel to the selected plane.

In some preferred implementations, the gate can also have a field plate structure.

In some more specific implementation cases, the MISFET device may further include a substrate, the selected plane is the main plane of the substrate, and the channel is formed on the main plane of the substrate.

Further, the substrate may be selected from commonly used substrates in the industry, such as sapphire substrates, GaN substrates, SiC substrates, etc., and is not limited thereto.

The MISFET device based on the vertical channel can be manufactured by conventional semiconductor device processing technology.

In summary, compared with the existing planar HEET, the MISFET device based on the vertical channel of the present invention has the following advantages: First, the gate electrode length of the device is determined by the thickness of the metal, and does not need to be defined by photolithography. Therefore, it can Break through the limitation of photolithography resolution and obtain extremely small gate length. It is of great significance to improve the frequency characteristics of the device. Second, since the gate electrode surrounds the channel at 360°, the gate control capability can be greatly improved, thereby obtaining extremely high transconductance and reducing off-state current. Compared with the existing vertical channel Si-based device or vertical Si-based nanowire device, it also has the following advantages: the device does not need a local doping process, which can greatly reduce the device process cost.

Another aspect of the embodiments of the present invention also provides a method for manufacturing the aforementioned vertical channel-based MISFET device, which may include:

An MIS structure is formed on the main plane of the substrate, the MIS structure includes at least one semiconductor structure and an insulating medium disposed around the semiconductor structure, and a channel is formed at the interface between the semiconductor structure and the insulating medium, and the channel's the axis is substantially perpendicular to a selected plane;

The source, the gate and the drain are made, and the source and the drain are electrically connected through the channel, and the gate is distributed between the source and the drain.

Further, in the preparation method, the semiconductor structure can be formed by growth on the main plane of the substrate by epitaxial growth methods known in the industry such as MOCVD and PECVD.

Further, in the preparation method, the aforementioned source, drain, gate, etc. can be formed by means of metal sputtering, atomic layering, and the like. The materials of these electrodes can also be selected from metal or non-metal materials commonly used in the industry, especially metal materials, such as Au, Ni, Ti and so on.

Further, in the preparation method, the aforementioned insulating dielectric layer and the like may also be formed by physical and/or chemical deposition methods known in the industry.

Further, in the preparation method, n-type doping can be performed on the semiconductor structure to increase the electron concentration of the channel in the MIS structure.

Further, the preparation method may further include: forming a plurality of semiconductor structures and an insulating medium distributed in an array on the main plane of the substrate, and forming a plurality of said semiconductor structures and the insulating medium between the plurality of semiconductor structures and the insulating medium. A channel array composed of channels.

Further, the preparation method further includes: forming an ohmic contact between the source electrode and the drain electrode and the semiconductor structure.

The technical solutions in the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Please refer to FIG. 1 which shows a vertical channel-based MISFET (VC-MISFET) device in a typical embodiment of the present invention, which includes a substrate, a MIS structure source, drain, gate, and the like.

Further, the MIS structure may be a columnar structure, which may be a coaxial structure mainly composed of an insulating medium a and a semiconductor structure b. A channel (not shown in the figure) is formed at the interface between the insulating medium a and the semiconductor structure b. The axis of the channel is arranged perpendicular to the main plane of the substrate.

Wherein, the gate surrounds the channel, especially the MIS structure, and is located between the source and drain electrodes.

Wherein, the source and the drain are respectively arranged at the upper and lower ends of the channel, and form ohmic contact with the first semiconductor, so that the source and the drain can be electrically connected through the channel.

Further, an isolation insulating dielectric layer may also be distributed between the gate and the drain and/or source, and the material of the dielectric layer may be Si ₃ N ₄ , etc., but is not limited thereto. But more preferably, there is no insulating dielectric layer between the gate and the drain and source.

Further, the drain may include a drain contact ring c1, and the drain contact ring c1 may be electrically connected to the drain lead pad c2 through a drain connection line c3.

Further, the gate may include a gate contact ring e1, and the gate contact ring e1 may be electrically connected to the gate lead pad e2 through a gate connection line e3.

Further, the source may include a source contact ring g1, and the source contact ring g1 may be electrically connected to the source lead pad g2 through a source connection line g3.

Further, the material of the aforementioned semiconductor channel may be a group III-V semiconductor material such as GaN or the like.

Further, the materials of the aforementioned gate, source, and drain can be selected from suitable metal materials known in the industry.

Further, the material of the aforementioned insulating medium may be Si ₃ N ₄ or various applicable metal oxides.

A kind of method for preparing described VC-MISFET device in a typical embodiment of the present invention may comprise the steps:

(1) Forming an MIS structure mainly composed of insulating medium a and semiconductor structure b on the main plane of the selected substrate.

(2) Forming the drain, including the drain contact ring c1 surrounding the channel.

(3) Depositing an isolation insulating dielectric layer between the gate and the drain.

(4) Forming the gate, including the gate contact ring e1 surrounding the channel.

(5) Depositing an isolation insulating dielectric layer between the gate and the source.

(6) Forming the source, including the source contact ring g1 surrounding the channel.

(7) Remove the insulating dielectric layer between the gate and the drain, and between the gate and the source outside the wiring pad.

(8) Etching and forming contact holes of the source, gate, and drain lead pads.

(9) Make source, gate, and drain leads.

Further, the drain connection line c3 , the gate connection line e3 , and the source connection line g3 are all non-parallel.

Referring to FIGS. 2-4 again, a vertical channel-based MISFET in a typical embodiment of the present invention may include a substrate 3 , an MIS structure, a source 4 , a gate 5 , and a drain 6 .

Further, the MIS structure includes an insulating medium 2 and a semiconductor structure 1 , and the insulating medium 2 is arranged around the semiconductor structure 1 .

Further, the insulating medium 2 as the shell and the semiconductor structure 1 as the core together form a columnar coaxial MIS structure, and a channel (not shown in the figure) is formed at the interface between the insulating medium 2 and the semiconductor structure 1, the The channel is vertically arranged on the main plane of the substrate.

Further, the source and the drain are respectively located at two ends of the columnar coaxial MIS structure, form ohmic contacts with the semiconductor, and are electrically connected through the channel.

Further, the source, gate, and drain metals are all parallel to the main plane of the substrate, and the gate is located between the source and the drain.

In the MISFET device of this typical implementation case, the semiconductor structure, the material of the insulating medium, the diameter, the length, the shape, etc. may be determined according to actual needs. For example, the semiconductor can be InP nanowires with a diameter of 100nm, and the insulating medium can be Si ₃ N ₄ with a thickness of about 10nm. The two form a coaxial MIS structure, and n-type doping can also be performed in InP. The radial cross section of the insulating medium and the semiconductor can be circular or the like. Furthermore, the length of the channel, that is, the distance between the source and the drain can also be determined according to actual needs, for example, it can be 50 nm. Wherein, the length of the gate of the MISFET device, the distance between the source and the drain, and the distance between the gate and the source can also be determined according to actual needs. For example, the length of the gate can be 5nm, and the distance between the source and the drain can be 30nm. The distance between the gate and the source can be 15nm. Wherein, the drain electrode may be located at the top side of the MISFET device, and the source electrode may be located at the bottom side of the MISFET device. Furthermore, the thickness of the source and the drain can be reasonably designed according to the total output current requirement of the device.

In another typical implementation case of the present invention, a vertical channel-based MISFET (VC-MISFET) device may have the structures shown in FIGS. The definition is the same as above.

Further, the VC-MISFET device includes a substrate, an MIS structure, a source and a drain, and the like.

The MIS structure includes several semiconductor structures b and insulating medium a, the insulating medium is arranged around these semiconductor structures, and these semiconductor structures and the insulating medium form a channel array composed of several channels. These channels are arranged perpendicular to the main plane of the substrate.

Wherein, the semiconductor structure b may be a columnar structure. These semiconductor structures b are all arranged perpendicular to the main plane of the substrate.

Wherein, the gate is arranged around each channel and is located between the source and drain electrodes.

The source and drain can be respectively arranged at the upper and lower ends of each channel, and form ohmic contact with each semiconductor structure, so that the source and drain can be electrically connected through each channel.

The foregoing semiconductor structure may be GaN grown along the c-axis, and its diameter may be determined according to actual needs, for example, it may be 0-2 μm (not 0).

The aforementioned insulating medium may be Si ₃ N ₄ , and its radial thickness may be 10-25 nm.

The length of the aforementioned channel, that is, the distance between the source and the drain can be determined according to actual needs, for example, it can be 100 nm.

The foregoing channel array may be in the form of a lattice, for example, may be distributed as a 3*3 square lattice.

The radial cross section of the aforementioned insulating medium and semiconductor structure may be in the shape of a circle or the like.

In the MISFET device of this typical implementation case, the gate length of the device, the distance between the source and the drain, and the distance between the gate and the source can also be determined according to actual needs. For example, the gate length can be 10nm, and the distance between the source and the drain It can be 60nm, and the gate-source distance can be 30nm. Wherein, the drain can be located at the bottom side of the MISFET device, and the source can be located at the top side of the MISFET device. In addition, the thickness of the source and drain can be reasonably designed according to the total output current requirement of the device.

The present invention is not limited to the foregoing embodiments. In fact, there may be many variant implementations of different types of designs utilizing the technical features of the present invention. For example, in the foregoing embodiments, an aluminum oxide dielectric layer and the like may also be disposed between the gate and the drain and between the source and the gate.

It should be noted that, in this document, the terms "comprising", "comprising" or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

It should be understood that the above description is only a specific embodiment of the present invention, and those of ordinary skill in the art can make some improvements and modifications without departing from the principle of the present invention, and these improvements and modifications are also It should be regarded as the protection scope of the present invention.

Claims (10)

1. a kind of MISFET devices based on vertical-channel, including source electrode, drain electrode, grid and MIS structure, it is characterised in that： The MIS structure includes at least semiconductor structure and the dielectric set around semiconductor structure, and in the semiconductor The interface of structure and dielectric is formed with raceway groove, and the axis of the raceway groove is basically perpendicular to a selected plane, the source electrode Electrically connected through the raceway groove with drain electrode, the grid is distributed between source electrode and drain electrode.

2. MISFET devices based on vertical-channel according to claim 1, it is characterised in that：The MISFET devices bag Include and be formed with by a plurality of between a plurality of semiconductor structures of array distribution, and a plurality of semiconductor structures and dielectric The channel array of described raceway groove composition.

3. MISFET devices based on vertical-channel according to claim 1 and 2, it is characterised in that：The MIS structure Axis is basically perpendicular to the selected plane；Preferably, the semiconductor structure is coaxially disposed with dielectric；Preferably, institute MIS structure is stated for column；Preferably, the radial cross-sectional shape of the MIS structure includes polygon or circle；Preferably, it is described Semiconductor structure is column；Preferably, the radial cross-sectional shape of the semiconductor structure includes polygon or circle；Preferably, The semiconductor structure is nano-pillar.

4. MISFET devices based on vertical-channel according to claim 1, it is characterised in that：The source electrode, drain electrode with The semiconductor structure forms Ohmic contact；Preferably, the source electrode and drain electrode are along raceway groove axial direction interval setting；It is preferred that , the distance between the grid and source electrode are less than the distance between the grid and drain electrode；Preferably, the source electrode and drain electrode It is respectively provided with the raceway groove two ends；Preferably, the grid is set around the MIS structure；Preferably, the source electrode, leakage At least one of pole and grid are parallel to the selected plane；Preferably, the source electrode, drain electrode and grid are each parallel to described Selected plane.

5. MISFET devices based on vertical-channel according to claim 1, it is characterised in that：The source electrode includes source electrode Contact ring, the source contact ring is set around the raceway groove；Preferably, the source contact ring is through connecting line and source lead Disk is electrically connected；Preferably, the drain electrode includes drain contact ring, and the drain contact ring is set around the raceway groove；Preferably, The drain contact ring is electrically connected through connecting line with drain lead disk；Preferably, the grid includes gate contact ring, the grid Pole contact ring is set around the raceway groove；Preferably, the gate contact ring is electrically connected through connecting line with grid lead disk；It is preferred that , at least one of the source contact ring, drain contact ring and gate contact ring are coaxially disposed with the MIS structure；It is excellent Choosing, at least one of the source contact ring, drain contact ring and gate contact ring are parallel to the selected plane.

6. MISFET devices based on vertical-channel according to claim 1, it is characterised in that：In the source electrode and drain electrode At least one also retain between grid or do not retain isolated insulation dielectric layer；Preferably, appointing in the source electrode and drain electrode Without isolated insulation dielectric layer between one and grid；And/or, the grid has field plate structure；And/or, the MISFET Device also includes substrate, and the selected plane is the substrate principal plane, and the semiconductor structure forms flat in substrate master On face；And/or, the material of the semiconductor structure is selected from III~V races semiconductor.

7. a kind of preparation method of the MISFET devices based on vertical-channel, it is characterised in that including：

In MIS structure is formed on substrate principal plane, the MIS structure includes at least semiconductor structure and around semiconductor structure The dielectric of setting, and it is formed with raceway groove, the axis of the raceway groove in the interface of the semiconductor structure and dielectric It is basically perpendicular to a selected plane；

Source electrode, grid and drain electrode are made, and the source electrode is electrically connected through the raceway groove with drain electrode, the grid is distributed in source electrode And drain electrode between.

8. preparation method according to claim 7, it is characterised in that including：Array point is formed on the substrate principal plane A plurality of semiconductor structures and dielectric of cloth, and make to be formed by plural number between a plurality of semiconductor structures and dielectric The channel array of individual described raceway groove composition.

9. preparation method according to claim 7, it is characterised in that：The axis of the MIS structure is basically perpendicular to described Selected plane；Preferably, the semiconductor structure is coaxially disposed with dielectric；Preferably, the MIS structure is column；It is excellent Choosing, the radial cross-sectional shape of the MIS structure includes polygon or circle；Preferably, the semiconductor structure is column；； Preferably, the radial cross-sectional shape of the semiconductor structure includes polygon or circle；Preferably, the semiconductor structure is to receive Meter Zhu.

10. preparation method according to claim 7, it is characterised in that：The source electrode, drain electrode and the semiconductor structure Into Ohmic contact；Preferably, the source electrode and drain electrode are along raceway groove axial direction interval setting；Preferably, the grid and source electrode The distance between less than the grid with drain electrode the distance between；Preferably, the source electrode and drain electrode is respectively provided with the raceway groove At two ends；Preferably, the grid is set around the MIS structure；Preferably, in the source electrode, drain electrode and grid at least One is parallel to the selected plane；Preferably, the source electrode, drain electrode and grid are each parallel to the selected plane；Preferably, The source electrode includes source contact ring, and the source contact ring is set around the raceway groove；Preferably, the source contact ring warp Connecting line is electrically connected with source lead disk；Preferably, the drain electrode includes drain contact ring, and the drain contact ring is around described Raceway groove is set；Preferably, the drain contact ring is electrically connected through connecting line with drain lead disk；Preferably, the grid includes Gate contact ring, the gate contact ring is set around the raceway groove；Preferably, the gate contact ring is through connecting line and grid Lead wire tray is electrically connected；Preferably, at least one of the source contact ring, drain contact ring and gate contact ring with it is described MIS structure is coaxially disposed；Preferably, the source contact ring, drain contact ring are parallel with least one of gate contact ring In the selected plane；And/or, the material of the semiconductor structure is selected from III~V races semiconductor.