CN1711674A - Two-stage power conversion circuit - Google Patents

Abstract

A power conversion circuit is provided. The circuit includes: an isolated onboard power module operable to convert a nominal input voltage into an intermediate bus voltage; the onboard power module is unregulated and controlled in an open-loop manner; and a plurality of tightly regulated point-of-load converters operable to convert the intermediate bus voltage into respective point-of-load voltages, thereby providing power to respective loads.

Description

Two-stage power conversion circuit

cross reference

This application is based on filings on November 11, 2002, December 23, 2002, February 14, 2003, and June 9, 2003 (according to IR-2412 PROV, IR-2412 PROVII, IR-2412 PROV III, respectively and IR-2412 PROV IV), and claim priority thereto. The disclosures of the above applications are incorporated herein by reference.

field of invention

The present invention relates to power conversion circuits, such as two-stage power conversion circuits used in networking and communication applications.

Background Information

In today's information age, the desire for information bandwidth in network and communication applications is increasing day by day. With the increasing demand for bandwidth comes an increasing need for quality of service (QoS) to better ensure data integrity and maximize system up-time. In order to achieve the above purpose, intelligent routing management is often used. For example, in packet distribution routing, data streams are reassembled into small packets, each small packet is routed through a separate data path en route to the final destination, and at that final destination, the packet is finally Reassembled into the original data stream. Such routing can only be achieved via complex packet processing, which will require faster and more powerful NPUs & ASICs.

The increase in data processing requirements has undoubtedly affected the design of internal hardware designs, especially in the area of on-board power distribution. Since the standard size of communication boards remains relatively constant, power distribution systems must be implemented in increasingly shrinking spaces as future designs require more and more processors to be added to the board. At the same time, an increase in the number of components always increases power consumption. In order to fit a power supply into a smaller space and meet increasing power demands, the power distribution design should be optimized to ensure efficiency. Designing a more efficient power supply produces less loss and thus less heat.

Many of today's networking and communication systems use power architectures that receive a 48V nominal input from an integral AC/DC rectification module. The 48V input is the nominal input, but various systems will accept power input within a range on either side of the nominal value. For example, the general telecom voltage range is from 36Vin to 75Vin, and the ETSI (European Telecommunications Standard Input) voltage range is from 36V to 60V. Other systems operate within +/-10% of the regulated 48V bus. Regardless of which power distribution method is used, the input voltage should be distributed to the point-of-load in the most electrically efficient and cost-effective manner possible.

To meet these more stringent demands, two-stage power conversion is becoming the new standard for onboard power delivery. Traditionally, multiple isolated power converters 105a, . . . , 105n-1, 105n called "bricks" are used to power various low The load provides power, as shown in Figure 1. The lower current peripheral output is supplied by converting the intermediate power generated by one of the above "blocks" via POLs 110a...110n.

Next, in an effort to increase the simplicity and flexibility of onboard power distribution designs, fully regulated converters are used to generate an intermediate bus voltage, which is then converted via point-of-load power converters (POLs) to point-of-load voltage. For example, in one approach, a separate isolated converter is used to convert the -48Vin nominal input to an intermediate bus voltage of 3.3V. This intermediate bus voltage is provided directly to the most power-hungry loads on the board, while the less power-hungry loads receive power via their respective POL converters. In another approach, as shown in FIG. 2 , the nominal -48V is converted to an intermediate bus voltage 205 of 12V via a single isolated converter 210 . Next, the intermediate bus voltage 205 is converted to various point-of-load voltages via respective POLs 215a, 215b, 215c..., 215n. In order to maximize throughput efficiency and minimize the cost of any two-stage scheme, each power conversion stage must be carefully optimized. However, the throughput efficiency of these schemes is generally lower compared to power distribution designs using multiple isolated converters.

Contents of the invention

It is an object of the present invention to overcome the deficiencies of conventional two-stage power distribution schemes by providing a cost and space efficient power distribution design using fewer components while meeting the increasing power demands in many of today's applications. To accomplish this, the exemplary embodiment of the present invention takes advantage of the fact that, when using tightly regulated POL converters, precise control of the intermediate bus voltage with isolated converters is not necessary . Instead, efficient performance can be obtained by running the converter open-loop in an unregulated regulation.

By running the isolated DC bus converter in an unregulated open-loop manner with a 50% duty cycle, the control and circuit design required to control the power conversion described above becomes very simple and efficient because the open-loop design does not require traditional Sophisticated closed-loop control and overvoltage protection circuits for tightly tuned power conversion designs. Therefore, such a control circuit can be realized in a single integrated circuit in a small space. Power conversion performance is achieved using minimized voltage and current stresses, which enables more efficient power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) with lower figures of merit (FOMs). Furthermore, the fixed 50% duty cycle improves reliability by allowing the use of a simple, highly efficient self-driven secondary synchronous rectification circuit while minimizing the need for input and output filtering.

To control the simple and novel open-loop control scheme introduced in this paper, two exemplary integrated circuit controllers are provided, one for the half-bridge converter and the other for the full-bridge converter. Exemplary half-bridge converters according to the present invention can be used to convert nominal input power over a range (for example, in the range of 60-160W), while full-bridge converters according to the present invention can operate between, for example, 120-160W. Convert rated power input within the range of 160W. Due to the fixed duty cycle, the output voltage is proportional to the product of the nominal input voltage and the factor K. For a half-bridge converter according to the invention, K may eg be equal to 1/2 divided by the turns ratio of the transformer. For the full-bridge converter of the present invention, K may eg be equal to 1 divided by the turns ratio of the transformer. Therefore, the full bridge topology offers greater flexibility relative to output voltage selection.

Brief description of the drawings

Figure 1 is a block diagram showing a conventional two-stage power conversion architecture;

Figure 2 is a block diagram showing another conventional two-stage power conversion architecture;

Figure 3 is a block diagram showing a first exemplary power converter architecture of the present invention;

FIG. 4 is an exemplary power conversion circuit for an on-board power module according to the present invention;

The graph of Fig. 5 shows the dead time of the half-bridge driver IC of the present invention;

FIG. 6 is a block diagram of the half-bridge driver IC in FIG. 4;

Figure 7 is a view showing the front and back of an exemplary power conversion board according to the present invention;

The graph of Figure 8 shows the relationship between power conversion efficiency and output load current;

Fig. 9 is another exemplary power conversion circuit for an onboard power module according to the present invention;

Figure 10 is a graph showing a hiccup waveform;

FIG. 11 shows a method for configuring the half-bridge driver IC in FIG. 4 to operate in a self-oscillating mode or a synchronous mode.

A detailed description

Referring now to FIG. 3, there can be seen a first exemplary half-bridge 2-stage power conversion architecture 300 according to the present invention. The power conversion architecture 300 includes a single isolated unregulated Board Mounted Power Module (BMP) 305 operating in an open-loop fashion. BMP 305 is operable to convert nominal input voltage 320 to intermediate bus voltage 325 . The intermediate bus voltage 325 is then fed to different point-of-load (POL) converters 310a, 310b..., 310n, which convert the intermediate bus voltage 325 into respective point-of-load voltages 330a, 330b..., 330n for powering different loads on the board (not shown).

Referring now to FIG. 4 , there can be seen an exemplary half-bridge converter circuit 405 for use in the BMP power module 305 of FIG. 3 . The half-bridge converter circuit 405 includes a main open-loop inversion circuit (inversion circuit) 410 , a main bias circuit 430 , a secondary rectification and filtering circuit 425 and a secondary bias circuit 420 .

The main open-loop inversion circuit 410 includes a main half-bridge controller IC (Integrated Circuit )415. Diode D1 is connected between Vdd and terminal (Vb) of controller IC 415; resistor R1 is connected between Vdd and terminal (CT) of controller IC 415; capacitor C1 is connected between Vdd and terminal (CT) of controller IC 415 Between terminals (CS), (G); Capacitor C2 is connected between terminal (CT) of controller IC415 and ground, and capacitor C2 is also connected to terminal (CS) of controller IC415, (G); Capacitor C3 is connected between the terminals (Vb), (Vs) of the controller IC 415; and the terminal (Vcc) is connected to Vdd. The main open-loop inversion circuit 410 also includes power MOSFETS M1, M2 (e.g. two IRF6603 30V n-channel DirectFET (Direct Solder Field Effect Transistor) power MOSFETS with gate clamped to a bias voltage of e.g. 7.5 volts drive voltage), the power MOSFETS M1, M2 are connected to each other in a half-bridge configuration between the 48 volt nominal input 320 and ground at node N1, which is also connected to the terminal (Vs) of the controller IC 415. The gates of MOSFETS M1, M2 are connected to terminals (HO), (LO), respectively. Capacitors C5 and C6 connected in series are connected in parallel with capacitor C4 and half-bridge MOSFETS M1, M2 between the 48 volt nominal input 320 and ground. The main winding I1 is connected between the node N2 and the terminal (Vs) of the controller IC 415.

MOSFET selection is critical to meeting electrical and thermal efficiency requirements to maintain a small integrated solution footprint while keeping component count to a minimum. The power MOSFETS M1, M2 may comprise next-generation MOSFET technology and may be configured to work with the half-bridge controller IC 415 in a half-bridge configuration. DirectFET packaging can also be used to virtually eliminate packaging resistance to achieve low overall on-state impedance. Also, since the DirectFET process uses plastic encapsulation, DirectFET MOSTFETS are very efficient when top-side cooling is used. The main bias circuit 430 includes a dual FET package 435 (e.g., IRF7380 n-channel FETs) containing main bias MOSFETS M3, M4; resistors R2, R3 connected in parallel between the 48 volt nominal input 320 and MOSFET M3; Resistor R4 connected between 48 volt nominal input 320 and MOSFET M4; Zener diodes D4, D5 connected in series between resistor R4 and ground; Diode D3 connected between node N3 and Vdd; a diode D2; and a main bias winding I2 connected between the diode D2 and ground. In this way, the primary side bias is obtained from the steady-state transformer through the start-up linear regulator.

The secondary rectification and filtering circuit 425 includes a secondary winding I3 magnetically coupled to the primary winding I1 of the primary open-loop inversion circuit 410 . The secondary winding I3 is connected between MOSFETS M5, M6 coupled to each other at node N4. Resistor R5 and capacitor C7 are coupled in parallel with each other and diode d6 is connected in parallel with the source and drain terminals of MOSFET M5. Likewise, resistor R6 and capacitor C8 are mutually coupled in parallel with diode D7, which is connected in parallel with the source and drain terminals of MOSFET M6. The gate nodes of M5, M6 are respectively connected to node N4 through respective resistors R7, R8. The inductor I4 is connected to the center-tapped node N5, and the capacitors C9, C10, C11 are connected in parallel with each other between the inductor I4 and the node N4. The secondary rectification and filtering circuit 425 is also configured with two secondary MOSFETS M7, M8. The gate nodes of MOSFETS M7, M8 are connected to each other. The source nodes of MOSFETS M7, M8 are connected to the gate nodes of MOSFETS M5, M6 respectively, and the drain nodes of MOSFETS M7, M8 are connected to the drain nodes of MOSFETS M6, M5 respectively. The MOSFETs M7, M8 on the secondary side can be implemented using (for example) IRF6603 DirectFET MOSFETs and can be configured in a self-driven synchronous rectification topology.

Secondary bias circuit 420 includes a secondary bias winding I5 magnetically coupled to primary bias winding I2 of primary bias circuit 430 . Diodes D8, D9 are connected in series with each other between nodes N4 and N6; capacitor C12 is connected to node N7; bias winding I5 is connected between capacitor C12 and node N4; resistor R8 and zener diode D10 are connected between nodes N6 and N4 is connected in series; capacitor C13 and resistor R9 are connected in parallel between node N4 and gates of MOSFETS M7 and M8. In this manner, secondary bias circuit 420 is designed to allow the outputs of two bus converters to be connected in parallel, each bus converter operating at a different nominal input voltage. In this way, secondary bias circuit 420 allows half-bridge converter circuit 405 to continue operating even if one of the two bus converters fails.

Referring now to FIG. 7 , therein can be seen the front and back of an exemplary power board 705 in accordance with the present invention. The power board is capable of delivering 150W at an output voltage of 8V with an efficiency higher than 96% in the form factor of a 1/8 converter BMP. It has 3-5% higher efficiency and less than 50% size than conventional fully regulated, on-board power converters. In order to minimize the power consumption of the printed circuit board (PCB), the power board 705 may have a multi-layer PCB construction, such as an 8-layer PCB construction. Its topmost and bottommost layers may include, for example, 2 oz of copper, and its inner six layers may include, for example, 4 oz of copper. The power board 705 may also include a transformer with a flat PQ core that provides voltage conversion and isolation between the main open loop inverter circuit 410 and the secondary rectification and filtering circuit 425 . The core used for the transformer can be selected according to the maximum input voltage and frequency. FR3 material can be used because it has low loss at high frequencies. A very small air gap can be provided in the transformer to reduce the turn-off time of the main side MOSFETs M1, M2 at light loads. A small output inductor of 160nH with a 1mm air gap can be used to limit the ripple of the output and input currents to less than four amps.

The half-bridge controller IC 415 is operable to provide high-side and low-side drive signals for the main driver MOSFETS M1, M2 (which has a 50% duty cycle and a minimum number of external components). The gate drive capability of the half-bridge controller IC 415 is optimized to directly drive the new generation power MOSFETS M1, M2 without any additional drivers or buffers. The high-side nominal input voltage 320 may be as high as, for example, 100V, even though the example circuit of FIG. 4 operates with a nominal input voltage of 48V. Therefore, this architecture allows a wide range of rated input voltages (eg, between 24V and 48V), which can be used in telecom, networking and computing applications. Also, the primary side bias voltage can be varied in the range of, for example, 10-15V to further optimize circuit performance.

The pulse width difference between the high-side and low-side drive signals should be less than a predetermined threshold, eg, less than 25 ns, to prevent flux imbalances that may be of concern in certain applications. The switching frequency and dead time between high-side and low-side drive signals can be changed by adjusting the values of resistor R1 and capacitor C2 for different applications. The switching frequency is determined by the following formula:

${\mathrm{<span\; class="notranslate">\; f</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C"\; filenames="A20038010303800231.png"\; state="\{\{state\}\}">C</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}$

External resistor R1 and capacitor C2 also determine the dead time between the high-side and low-side drive signals. Referring now to FIG. 5, there can be seen a graph of the value of resistor R1 versus dead time for a given capacitance value of capacitor C2. The dead time should be longer than the cut-off time of the primary side MOSFETSM1, M2 to prevent shoot-through current. The turn-off time of the main power MOSFETS can be estimated by the following equation:

${\mathrm{<span\; class="notranslate">\; t</span>}}_{\mathrm{<span\; class="notranslate">\; off</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; gd</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; gs</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}}$

where Qgd is the gate-drain charge (ie, "Miller charge") of the MOSFET, Qgs2 is the post-threshold gate charge, and Ig is the driver current.

During the dead time, the body diodes of the secondary MOSFETS M7, M8 conduct. Therefore, the dead time should be set as short as possible in order to maximize the efficiency, and at the same time be able to provide enough time for the main side MOSFETS M1, M2 to turn off under the worst case operating conditions.

Referring now to FIG. 6, further details of the exemplary half-bridge controller IC 415 of FIG. 4 can be seen. The entire controller IC 415 operates at a bias voltage (eg, 10 to 15 volts) generated by the bias module 610. The half-bridge controller IC 415 includes undervoltage lockout (UVLO) modules 605, 650 assigned to Vcc and Vb, respectively. An undervoltage lockout feature ensures that all timing signals are kept within specification. The oscillator module 615 provides a signal S1 like 555 with a 50% duty cycle. The internal soft-start module 630 ensures that the duty cycle of the signals S2, S3, S4 gradually increases from zero to 50%, so as to weaken the inrush current during the start-up process. The high-side driver 655 and the low-side driver 660 are capable of providing, for example, one ampere of current on the high-side and low-side driver signals (HO), (LO) via MOSFETS 665, 670, 675, 680. The half-bridge controller IC 415 also includes a current limiting function via current sources 640,645 and MOSFETS 690,695.

As mentioned above, the half-bridge controller IC 415 can be used to control an unregulated isolated DC bus converter operating in an open-loop manner, such as a DC bus converter used in a 48V two-stage on-board power distribution system. The half-bridge controller IC 415 is optimized in terms of performance, compactness, and cost, and the entire controller IC 415 can be integrated into a single package (eg, a single S08 package).

Referring now to FIG. 9 , there can be seen an exemplary full bridge converter circuit 900 for use in the BMP power module 305 of FIG. 3 . The full-bridge converter circuit 900 includes a main open-loop inversion circuit 910 , a main bias circuit 915 and a secondary rectification and filtering circuit 425 .

The main open-loop inversion circuit 910 includes terminals (CS), (D), (CT), (G1), (LO1), (Vcc), (VB1), (HO1), (VS1), (G2), Main full-bridge controller IC 905 for (LO2), (VS2), (HO2) and (VB2). A diode D1 is connected between Vcc and a terminal (VB1) of the controller IC 905; a diode D2 is connected between Vcc and a terminal (VB2) of the controller IC 905; a resistor R1 is connected between Vcc and a terminal (VB2) of the controller IC 905; terminal (CT); capacitor C1 is connected between Vcc and terminal (G1) of controller IC 905; capacitor C2 is connected between terminal (CT) of controller IC 905 and ground; capacitor C15 is connected between between the terminals (Vb1) and (VS1) of the controller IC 905; the terminal (Vcc) is connected to Vcc; the capacitors C17 and C18 are connected in parallel with each other between the 48 volt rated input 320 and ground; the capacitor C16 is connected at the control Between the terminals (VS2) and (VB2) of the device IC 905. The main open-loop inversion circuit 905 also includes power MOSFETS M9, M10, M11 and M12 (eg, four IRF6603 30V n-channel DirectFET power MOSFETS). MOSFETs M9, M10 and M11, M12 are interconnected in a full bridge configuration at nodes N9 and N10 respectively between the 48 volt nominal input 320 and ground. Node N9 is also connected to a terminal (VS1) of the controller IC 905, and node N10 is also connected to a terminal (VS2) of the controller IC 905. The gates of MOSFETs SM9, M10, M11, M12 are connected to terminals (HO1), (LO1), (HO2) and (LO2), respectively. The main winding I7 is connected between nodes N9 and N10.

Main bias circuit 915 includes: main bias MOSFETS M15, M16; resistors R16, R17 connected in parallel between 48 volt rated input 320 and MOSFET M15; resistors connected between 48 volt rated input 320 and MOSFET M4 R18; series connected zener diodes D13, D14 connected between resistor R18 and ground; diode D15 connected to MOSFET M16; main bias winding 19 connected between diode D15 and ground; in controller IC 905 A resistor R14 and a capacitor C22 connected in parallel to each other between the terminal (CS) of the controller IC 905 and the ground; a resistor R15 and R13 connected in series at the node N1 between the terminal (CS) of the controller IC 905 and the ground; Resistor R19 connected between terminals (CS) and (rm); diodes D16, D17 connected in series between node N11 and ground; diodes D18, D19 connected in series between node N11 and ground; and a coil I10 connected between series connected diodes D16, D17 and D18, D19.

The secondary rectification and filtering circuit 920 includes a secondary winding I11 magnetically coupled to the primary winding I7 of the primary open-loop inversion circuit 910 . The secondary winding I11 is connected between MOSFETS SM17, M18 coupled to each other at node N12. The gate nodes of MOSFETS M17 and M18 are connected to node N12 through resistors R11 and R10 respectively. The inductor I8 is connected to the center tap node N13, and the capacitors C19, C20 and C21 are connected in parallel with each other between the inductor I8 and the node N12. The secondary rectification and filtering circuit 425 is also configured with two secondary MOSFETS M13, M14. Gate nodes of MOSFETS M13, M14 are connected to each other. Zener diode D20 and capacitor C23 are connected in parallel with each other between the gate nodes of MOSFETS M13, M14 and node N12. Resistor R12 is connected between gate nodes of MOSFETS M13, M14 and coil I8. The source nodes of MOSFETS M13, M14 are respectively connected to the gate nodes of MOSFETS M17, M18, and the drain nodes of MOSFETS M13, M14 are respectively connected to the drain nodes of MOSFETS M18, M17. The secondary side MOSFETs M13, M14 can be implemented using eg IRF6603 DirectFET MOSFETs and configured in a self-driven synchronous rectification topology.

The full-bridge controller and driver IC 905 is similar to the half-bridge controller 415 in Figure 4, but with an improved current limit functional mode and flexible soft-start capability. The current limit function has a hiccup mode in which the period of the hiccup can be externally controlled by a capacitor. The primary side current is sensed with a current transformer having a high turns ratio (eg 150 to 1 turns ratio). The sensed AC current information is rectified and then provided as input to the current sense pin (CS) of the driver IC 905 after RC filtering.

Since this controller IC 905 is designed for a full bridge circuit, it provides four gate drive signals for MOSFETS M9, M10, M11 and M12 respectively. The controller turns on each branch alternately with a 50% duty cycle. The difference in conduction period between the above two branches should be less than (for example) 25 ns to prevent imbalance of the magnetic flux. The turn-on and turn-off timing differences between the two MOSFETS should also be less than 25ns.

Referring now to FIG. 10 , there is shown a waveform diagram of the output voltage during ramp mode with a current limit setting of 21A, a current load setting of 22A, and a nominal input voltage of 48 volts. As shown in Figure 10, the controller IC 905 attempts to turn on the above-mentioned converter once in a predetermined period. For example, the aforementioned predetermined period can be set to (for example) 500 ms by adjusting the value of the capacitor C14.

Both the half-bridge controller IC 415 and the full-bridge controller IC 905 are designed to allow easy external synchronization over the range of ride frequencies. To do this, the timing resistor R1 needs to be removed, and the timing capacitor C2 is connected between the IC 415, 905 and the external synchronization source, as shown in Figure 11. In self-oscillating mode, the current through the external timing resistor R1 charges the timing capacitor C2. Once the voltage at the (CT) terminal of either IC 415 and 915 is above a predetermined threshold, such as above half the IC supply voltage Vcc or Vdd, the internal driver of the controller IC 415, 905 begins discharging the timing capacitor C2. After the voltage at the terminal (CT) is lower than a predetermined threshold, such as one-fifth of the supply voltage Vcc or Vdd, the controller IC405, 915 turns off the above-mentioned internal driver, and stops discharging the timing capacitor C2, so that through the resistor The current in R1 begins to charge capacitor C2 again.

In the sync mode of operation, external capacitor C2 couples the rising edge of the external sync source to the (CT) terminal. The internal driver of the controller 415, 905 starts discharging the voltage at terminal (CT) as long as the voltage at terminal (CT) is above a predetermined threshold, eg half of the IC supply voltage. When the voltage at the terminal (Ct) is less than a predetermined threshold, such as one-fifth of the supply voltage of IC 415, 905, IC 405, 915 turns off the above-mentioned driver and stops discharging the timing capacitor C2. When a negative edge is applied, an internal diode resets the voltage at terminal (CT) and holds the voltage of the external timing capacitor C2 at zero volts. After the voltage of the external timing capacitor C2 reaches zero, the capacitor C2 is ready for the next external positive pulse. In this synchronous mode, the dead time is determined only by the internal impedance at the terminal (CT) and the capacitance of the external timing capacitor C2.

In self-oscillation mode, the timing resistor R1 should not be too small to limit the maximum operating frequency. Usually, the timing resistor R1 should be higher than a predetermined value, such as 2KΩ. The lower the resistance value of resistor R1, the higher the sink current for the internal discharge driver of IC415,905. Since timing resistor R1 is removed in synchronous mode, higher operating frequencies can be obtained. The maximum operating frequency in synchronous mode is determined by the power dissipation driving the external master-side MOSFETS.

Claims (20)

1. A power conversion circuit comprising: an unregulated isolated on-board power module operable to convert the nominal input voltage to an intermediate bus voltage, the isolated on-board power module being controlled in an open-loop manner; and A plurality of closely regulated point-of-load converters operable to convert the intermediate bus voltage to respective point-of-load voltages to provide power to respective loads. 2. The power conversion circuit according to claim 1, wherein the on-board power module comprises: a main open-loop inversion circuit magnetically coupled to each other, a main bias circuit, a secondary synchronous rectification and filter circuit, and a secondary bias circuit, The synchronous rectification and filtering circuit generates the intermediate bus voltage. 3. The power conversion circuit of claim 2, wherein the main open-loop inversion circuit comprises a half-bridge controller IC and a pair of MOSFETs connected in a half-bridge configuration, the controller IC being operable to operate in accordance with 50 % duty cycle alternately controls the MOSFET pair. 4. The power conversion circuit as claimed in claim 3, wherein the main open-loop inversion circuit comprises timing resistors and timing capacitors, and the dead time and switching frequency of the controller IC are based on the timing resistors and timing capacitors. value to adjust. 5. The power conversion circuit as claimed in claim 4, wherein the switching frequency is passed by the formula: $f_{\mathrm{the\; s}}=\frac{1}{2R_1{C}_2}$ To determine, wherein, fs is the switching frequency, R1 is the value of the timing resistor, and C2 is the value of the timing capacitor. 6. The power conversion circuit of claim 3, wherein the pair of MOSFETs comprises DirectFETs. 7. The power conversion circuit of claim 3, wherein the half-bridge controller IC is capable of operating in at least two modes, one of which is a self-oscillating mode and the other of which is is synchronous mode. 8. The power conversion circuit of claim 2, wherein the main open-loop inversion circuit comprises a full-bridge controller IC and two pairs of MOSFETs connected in a full-bridge configuration, the controller IC being operable to follow a 50 % duty cycle alternately controls the two pairs of MOSFETs. 9. The power conversion circuit as claimed in claim 8, wherein said main open-loop inversion circuit comprises a timing resistor and a timing capacitor, and the dead time and switching frequency of said full-bridge controller IC depend on said timing resistor and timing capacitor. Capacitor value to adjust. 10. The power conversion circuit as claimed in claim 9, wherein the switching frequency is obtained by the formula: $f_{\mathrm{the\; s}}=\frac{1}{2R_1{C}_2}$ To determine, wherein, fs is the switching frequency, R1 is the value of the timing resistor, and C2 is the value of the timing capacitor. 11. The power conversion circuit of claim 8, wherein the two pairs of MOSFETs comprise DirectFETs. 12. The half-bridge power conversion circuit as claimed in claim 8, wherein said full-bridge controller IC is capable of operating in at least two modes, one of said modes being a self-oscillating mode, the other of said modes being One is synchronous mode. 13. A half-bridge controller IC for use with a power conversion circuit comprising: an isolated unregulated on-board power module operable to convert a nominal input voltage to an intermediate bus voltage; said on-board power module is controlled in an open-loop manner; and a plurality of tightly regulated point-of-load converters operable to convert said intermediate bus voltage into individual point-of-load voltages to provide power to individual loads, The half-bridge controller IC includes: a bias circuit for generating a bias voltage to operate the half-bridge controller IC; an undervoltage lockout circuit operable to monitor the voltage of a power supply pin of the half-bridge controller IC; an oscillator circuit for providing a timing signal with a 50% duty cycle; a soft-start circuit for ensuring that said duty cycle of said timing signal is gradually increased from 0 to a 50% duty cycle, thereby reducing inrush current during start-up; and High-side and low-side drivers for providing MOSFET drive signals to control a pair of MOSFETs interconnected in a half-bridge configuration, the half-bridge controller IC alternately controlling the MOSFETs with a 50% duty cycle. 14. The half-bridge controller IC of claim 13, wherein said MOSFETs comprise a pair of DirectFETs. 15. A power conversion circuit comprising: An unregulated isolated on-board power module operable to convert a nominal input voltage to an intermediate bus voltage, the isolated on-board power module being controlled in an open-loop manner, the unregulated isolated on-board power module The onboard power module includes a half-bridge controller IC including: a bias circuit for generating a bias voltage to operate the half-bridge controller IC; an undervoltage lockout circuit operable to monitor all the voltage of the power supply pin of the half-bridge controller IC; an oscillator circuit for providing a timing signal with a 50% duty cycle; a soft-start circuit for ensuring that the duty cycle of the timing signal gradually increases A duty cycle that increases from 0 to 50 percent to reduce inrush current during start-up; and high-side and low-side drivers to provide MOSFET drive signals to control a pair of MOSFETs interconnected in a half-bridge configuration, so the half-bridge controller IC alternately controls the MOSFETs with a 50% duty cycle; and A plurality of closely regulated point-of-load converters operable to convert the intermediate bus voltage to respective point-of-load voltages to provide power to respective loads. 16. The power conversion circuit according to claim 15, wherein the on-board power module comprises: a main open-loop inversion circuit, a main bias circuit, a secondary rectification and filter circuit, and a secondary bias circuit, the main open-loop An inversion circuit is magnetically coupled to the secondary rectification and filter circuit, the primary bias circuit is magnetically coupled to the secondary bias circuit, the secondary rectification and filter circuit generates the intermediate bus voltage. 17. The power conversion circuit as claimed in claim 16, wherein the main open-loop inversion circuit comprises timing resistors and timing capacitors, and the dead time and switching frequency of the controller IC are based on the timing resistors and timing capacitors. value to adjust. 18. The power conversion circuit of claim 17, wherein the switching frequency is given by the formula: $f_{\mathrm{the\; s}}=\frac{1}{2R_1{C}_2}$ To determine, wherein, fs is the switching frequency, R1 is the value of the timing resistor, and C2 is the value of the timing capacitor. 19. The power conversion circuit of claim 16, wherein the pair of MOSFETs comprises DirectFETs. 20. The power conversion circuit of claim 16 , wherein the half-bridge controller IC is capable of operating in at least two modes, one of which is a self-oscillating mode and the other of which is is synchronous mode.

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