CN1794075A - Liquid crystal display device and method for forming the same - Google Patents

Abstract

A liquid crystal display device and a method for forming the same are provided, the device includes a gate line, an active layer, a pixel electrode, a source line, and a drain line. The gate line is formed on an insulating substrate, one side of a section protrudes to form a protruding area, and the section is provided with an inward concave area opposite to the protruding area; the active layer is formed on the segment; the pixel electrode is formed on the convex side of the gate line; the source line crosses the overlapping area of the active layer and the gate line to extend beyond the boundary of the active layer along the direction substantially perpendicular to the extending direction of the gate line; the drain line is coupled to the pixel electrode and crosses an overlapping area of the active layer and the gate line in an extending direction substantially parallel to the source line. The invention can avoid the deviation of grid-drain capacitance when the machine platform is not aligned, thereby preventing the phenomenon of uneven brightness of different areas of the liquid crystal display device.

Description

Liquid crystal display device and method for forming the same

technical field

The present invention relates to a liquid crystal display (Liquid Crystal Display; LCD), and particularly relates to a structure of a thin film transistor (Thin Film Transistor; TFT)-LCD device that can avoid gate-drain capacitance deviation.

Background technique

In recent years, flat-panel displays have developed rapidly and have gradually replaced traditional picture tube displays, especially liquid crystal displays. The range of applications ranges from mobile phones to large-size screens. Among liquid crystal displays, active matrix liquid crystal displays using thin film transistors account for the vast majority, because their display effect is better than that of passive matrix liquid crystal displays. Therefore, the active matrix liquid crystal display is the current research and development focus of the liquid crystal display.

FIG. 1 is a plan view showing a pixel unit in a typical thin film transistor-liquid crystal display (TFT-LCD). The pixel unit 10 of the TFT-LCD device includes a gate line 11 disposed on an insulating substrate along the horizontal direction, and the gate line 11 has a protruding area as a gate 12 . An active layer 13 is formed on the gate 12, for example, made of amorphous silicon (amorphous silicon). A source line 14 extends vertically across the gate line 11 and has a protruding region serving as a source 15 . A drain line 16 is coupled to a pixel electrode 18 and crosses the gate 12 along the extending direction of the gate line 11 , and has a drain 17 . The pixel electrode 18 is usually made of a transparent conductive material with good conductivity. For example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).

In the photolithography manufacturing process, the variation of the machine makes the overlapping area between the source 15 /drain 17 and the gate 12 change when the mask is shifted during the TFT formation process. FIG. 2 is a plan view showing that the source 15 /drain 17 in the pixel unit of the TFT-LCD device 10 is shifted to the right due to exposure deviation. Compared with FIG. 1 , in FIG. 2 , the overlapping area between the source 15 and the gate 12 is enlarged, while the overlapping area between the drain 17 and the gate 12 is reduced. Therefore, the gate-source capacitance (hereinafter abbreviated as C _GS ) increases, while the gate-drain capacitance (C _GD ) decreases. Conversely, when the exposure process deviates and the source 15 and drain 17 are shifted to the left (not shown), C _GS decreases and C _GD increases.

FIG. 3 is an equivalent circuit diagram of a pixel unit in a TFT-LCD to illustrate the influence of C _GD on brightness. In the figure, G represents the gate, S represents the source, D represents the drain, C _LC is the liquid crystal capacitor, C _S is the storage capacitor, and these two capacitors are connected in parallel between a pixel electrode P and a shared electrode C . When the TFT-LCD is turned on, the gate voltage is equal to a relatively high voltage V _GH , and the relationship between the total charge Q ₁ in the TFT-LCD and the pixel electrode voltage V _P1 can be expressed as:

Q ₁ ＝C _GD (V _P1 V _GH )+(C _LC +C _S )(V _P1 V _COM ) ...(1)

where V _COM is the voltage of the common electrode.

Conversely, when the TFT-LCD is turned off, the gate voltage is equal to a relatively low voltage V _GL , and the relationship between the total charge Q ₂ in the TFT-LCD and the pixel electrode voltage V _P2 can be expressed as:

Q ₂ ＝C _GD (V _P2 V _GL )+(C _LC +C _S )(V _P2 V _COM ) ...(2)

Since the total charge is conserved, that is, Q1=Q2, it can be known from (1)(2):

V _P ＝V _P1 V _P2 ＝(V _GH V _GL )(C _GD /(C _CL +C _CS +C _GD )) ...(3)

It can be seen from (3) that V _P (the so-called kickback voltage) is affected by C _GD . Since the brightness of the LCD is controlled by the voltage of the pixel electrode, if the _CGD of the TFT in different regions is deviated due to the variation of the machine in the lithography manufacturing process, the phenomenon of uneven brightness will appear in all parts of the liquid crystal display. In severe cases , to produce the so-called "Mura". However, because the exposure accuracy of the exposure machine is limited to a certain range and cannot be 100% accurate, the liquid crystal display generally has uneven brightness everywhere.

Contents of the invention

In view of this, a thin-film transistor-liquid crystal display (TFT-LCD) device that can avoid gate-drain capacitance deviation is desired by those skilled in the art.

The invention provides a liquid crystal display device, which includes a gate line, an active layer, a pixel electrode, a source line, and a drain line. The gate line is formed on an insulating substrate, and one side of a segment protrudes to form a protruding area, and the segment has a sunken area facing the protruding area. The active layer is formed on the segment. The pixel electrode is formed on the protruding side of the gate line. The source line is substantially perpendicular to the extending direction of the gate line, crosses the overlapping area of the active layer and the gate line, and extends beyond the boundary of the active layer. The drain line is coupled to the pixel electrode, and is substantially parallel to the extending direction of the source line, and crosses the overlapping area of the active layer and the gate line.

The present invention provides a structure of a liquid crystal display device, including: a gate line, a first and a second active layer, a first and a second pixel electrode, a source line, and a first and a the second drain line. The gate line is formed on an insulating substrate, wherein two sides of a section of the gate line protrude to form first and second protruding areas respectively, and a hollow area is formed on the first and second protruding areas. out of the middle of the area, and divide the section into a first part and a second part. The first and second active layers are respectively formed on the first part and the second part of the gate line. The first and second pixel electrodes are respectively formed on one side of the gate line. The source line crosses the overlapping area of the active layer and the first portion and the overlapping area of the active layer and the second portion substantially perpendicular to the extending direction of the gate line. The first and second drain lines are respectively coupled to the first and second pixel electrodes, and extend across the first and second active layers in a direction substantially parallel to the extension of the source lines, respectively. an overlapping area with the first and second portions.

The present invention provides a method for forming a liquid crystal display device, comprising: forming a gate line on an insulating substrate, wherein one side of a section of the gate line protrudes to form a protruding area, and has a The recessed area is facing the protruding area; an active layer is formed on the section; a source line and a drain line are defined on the active layer and the insulating substrate, so that the source line is in accordance with Extending across the overlapping region of the active layer and the gate line substantially perpendicular to the extending direction of the gate line beyond the boundary of the active layer, and making the drain line substantially parallel to The extending direction of the source line crosses the overlapping area of the active layer and the gate line from a region where a pixel electrode is expected to be formed on the protruding side of the gate line; and forming the pixel electrode.

The present invention provides a method for forming a liquid crystal display device, comprising: forming a gate line on an insulating substrate, wherein the two sides of a section of the gate line protrude to form first and second protrusions respectively region, and has a hollow region in the middle of the first and second protruding regions to separate the region into a first part and a second part; a gate line is respectively formed on the first part and the second part First and second active layers; define a source line on the first and second active layers and the insulating substrate, and define first and second active layers on the first and second active layers and the insulating substrate respectively a drain line, such that the source line spans the overlapping region of the active layer and the first portion and the active layer and the second portion substantially perpendicular to the extending direction of the gate line overlapping regions, and make the first and second drain lines substantially parallel to the extending direction of the source lines, respectively from the areas on the insulating substrate where a first and second pixel electrodes are predetermined to be formed. across overlapping regions of the first and second active layers and the first and second portions respectively; and forming the first and second pixel electrodes.

Through the thin film transistor liquid crystal display (TFT-LCD) device and its forming method disclosed in the present invention, it is possible to avoid the deviation of the gate-drain capacitance when the alignment of the machine is not accurate, so that the phenomenon of uneven brightness in different areas of the LCD can be prevented .

However, the structure and method of forming the present invention, together with additional objects and advantages thereof, may be best understood through the following description of specific embodiments and when read with reference to the accompanying figures.

Description of drawings

FIG. 1 is a plan view of a pixel unit in a conventional TFT-LCD device;

2 is a plan view of a pixel unit in the conventional TFT-LCD device of FIG. 1 when the source/drain is shifted to the right during exposure;

Fig. 3 is an equivalent circuit diagram of a pixel unit in a TFT-LCD;

4A and FIG. 4B are plan views showing an embodiment of a pixel unit in an LCD device of the present invention, and have different gate line widths and different recessed regions near the TFT;

5A to 5E are cross-sectional views showing the formation process of a pixel unit in the LCD device of FIG. 4A;

6A to 6E are plan views showing a process of forming a pixel unit in the LCD device of FIG. 4A;

7 is a plan view showing an embodiment of a pixel unit in another LCD device of the present invention; and

8A to 8E are plan views showing a process of forming a pixel unit in the LCD device of FIG. 7 .

Symbol Description:

10～Traditional thin film transistor-one pixel unit of liquid crystal display device

11～Gate line

12～Gate 13～Active layer

14～source line 15～source

16～drain line 17～drain

18～Pixel electrodes

40, 40'～a pixel unit of the LCD device of the present invention

41～gate line/conductive film 41a～protruding area

41b～indented area 42～gate

43～semiconductor layer/active layer 44～source line

45～source 46～drain line

47～Drain 48～Pixel electrode

52～Gate insulating film 55～Passivation film

66～contact hole 70～one pixel unit of the LCD device of the present invention

71～gate line 71a ₁ ～the first protruding area

71a ₂ ～second protruding area 71b～indented area

72 ₁ ~ first grid 72 ₂ ~ second grid

73 ₁ ~ first active layer 73 ₂ ~ second active layer

74 ₁ ~ first source 74 ₂ ~ second source

76 ₁ ~First drain line 76 ₂ ~Second drain line

77 ₁ ～first drain 77 ₂ ～second drain

78 ₁ ～first pixel electrode 78 ₂ ～second pixel electrode

86 ₁ ~ first contact hole 86 ₂ ~ second contact hole

Detailed ways

The icons referenced herein are not scaled down to scale. The relative sizes of the different components depicted in the drawings are not intended to represent the proportional characteristics of the actual sizes of these components, but are only used to assist those of ordinary skill in the art to clearly understand how to make and use the present invention, as well as understand the implications Inventive concepts within the present invention.

Referring to FIG. 4A , it is a plan view showing an embodiment of a pixel unit in an LCD device of the present invention. As shown in the figure, in a pixel unit 40, a gate line 41 is formed on an insulating substrate (not shown in the figure), wherein one side of a section of the gate line protrudes to form a protruding region 41a , and the other side is recessed to form a recessed area 41b, which is opposite to the protruding area 41a. This section is used as a gate 42 . An active layer 43 is formed on the gate 42 . A source line 44 has a source electrode 45 on the active layer 43 across the overlapping region of the active layer 43 and the gate line 41 according to the extending direction substantially perpendicular to the gate line 41, and extending beyond the boundaries of the active layer 43 . A drain line 46 is coupled to a pixel electrode 48, and is substantially parallel to the extending direction of the source line 44, from the protruding region 41a of the gate line 41 to the recessed region 41b to cross the The active layer 43 overlaps with the gate line 41 , and has a drain 47 on the active layer 43 . A channel region is defined between the source electrode 45 and the drain electrode 47 in the active layer 43 . Please note that the source line 44 slightly bends toward the drain line 46 on the TFT, however, the source line can also be a straight line, or extend in other directions substantially perpendicular to the gate line 41 .

It is obvious that, under the change of the structural size and the manufacturing process precision, the C _GD will not change due to the change of the manufacturing process precision. As shown in the figure, the extending direction of the parallel gate lines 41 is called the X direction, and the extending direction of the vertical gate lines 41 is called the Y direction. If the exposure machine has a precision variation of ±D _X in the X direction, and the distance between the source line 44 and the overlapping area of the active layer 43 and the gate line 41 in the X direction is L _X1 , the drain line 46 and the active layer The distance between the edge of the overlapping area of 43 and the gate line 41 in the X direction is L _X2 , so L _X1 and L _X2 must be designed to be larger than D _X . Similarly, if the exposure machine has an accuracy variation of ±D _Y in the Y direction, the distance in the Y direction from the edge of the overlapping area between the drain line 46 and the active layer 43 and the gate line 41 is _LY , so _LY must be designed is greater than D _Y . When this design requirement is met, if the exposure accuracy of the exposure machine deviates, the overlapping area of the source 45 /drain 47 and the gate 42 remains constant, so that C _GD does not change much.

In addition, in order to meet the requirement of low resistance of the gate line 41, the pixel unit 40' as shown in FIG. 4B can be used. The gate line is increased in line width, and has a hollow space 41b facing the protruding region 41a.

5A to 5E take the LCD device of FIG. 4A as an example to present cross-sectional views of a formation process of a pixel unit in the LCD device of the present invention. 6A to 6E take the LCD device of FIG. 4A as an example to present a plan view of the formation process of a pixel unit in the LCD device of the present invention, and FIG. 5A to FIG. Sectional view.

First, referring to FIG. 5A, a conductive film 41 is formed on an insulating substrate 50 (such as a glass substrate), wherein the material of the conductive film 41 is, for example, aluminum (Aluminum; Al) or chromium (chromium; Cr) or the like. The low-resistance metal or its alloy is formed in a single-layer or multi-layer structure, and the formation method is a traditional deposition process such as sputtering. Then, a photolithography-etching process is used to pattern the conductive film 41 to form a gate line 41 and a gate 42 on the insulating substrate 50 . As shown in FIG. 6A, one side of a section of the gate line 41 protrudes to form a raised area 41a, and the section has a recessed area 41b facing the raised area 41a, and the section as gate 42 .

Next, as shown in FIG. 5B and FIG. 6B, a gate insulating film (for example, a nitride layer) 52, and a semiconductor layer 43 made of amorphous silicon (for example, including a doped N-type impurity amorphous silicon layer) on the surface of the structure produced in the above steps, and the formation method is, for example, a conventional deposition procedure using plasma enhanced chemical vapor (plasma enhanced chemical vapor deposition; PECVD), and then the semiconductor layer 43 is patterned to form an active layer 43 on the gate 42 (and gate insulating film 52).

Next, as shown in FIG. 5C and FIG. 6C, a conductive film is formed on the entire surface of the structure produced in the above steps, wherein the material of the conductive film is, for example, aluminum (Aluminum; Al) or chromium (chromium; Cr) Low-resistance metals or their alloys are formed in a single-layer or multi-layer structure, and the formation method is, for example, using traditional deposition procedures such as sputtering (sputtering), and then using exposure, development and etching procedures to provide the conductive The thin film is patterned to form a source line 44 and a drain line 46 , wherein the source line 44 and the drain line 46 respectively have a source 45 and a drain 47 on the active layer 43 . As shown in FIG. 5C , the patterning procedure is to make the source line 44 cross the overlapping area of the active layer 43 and the gate line 41 substantially perpendicular to the extending direction of the gate line 41, and The drain line 46 is substantially parallel to the extension direction of the source line 44 from the projected side of the gate line 41 to a predetermined area for forming a pixel electrode, across the active layer 43 and the gate. The overlapping area of polar lines 41.

Next, as shown in FIG. 5D and FIG. 6D, a passivation film (passivation film) 55 is formed on the entire surface of the structure produced in the above steps, wherein the passivation film 55 is, for example, a nitride film, and the forming method utilizes The traditional deposition process of plasma CVD, and then utilize the procedure of exposure development and etching in described passivation film 55 to form a contact hole (contact hole) 61 (not shown in Fig. 5D, but shown in Fig. 6D), so that A part of the drain line 46 is exposed to the outside.

Next, as shown in FIG. 5E and FIG. 6E, a transparent conductive material, such as indium tin oxide or indium zinc oxide, is formed on the entire surface of the structure produced in the above steps, and an etching process is used to make a pattern for the conductive material so that the conductive material is connected to the exposed surface of the drain line 46 to form a pixel electrode 48, wherein the pixel electrode 48 is formed on a part of the drain line 46 and the contact hole 61, and formed on the The active layer 43 is on the passivation film 55 adjacent to the TFT. The pixel electrode 48 is connected to the drain line 46 through the contact hole 61 in the passivation film 55 .

It should be noted that the structure of the present invention can be extended to a double thin film transistor structure to increase the conduction current. 7 is a plan view showing an embodiment of a pixel unit in another LCD device of the present invention, which includes two thin film transistors connected in parallel.

As shown in FIG. 7 , in a pixel unit 70 , a gate line 71 is horizontally disposed on an insulating substrate. Both sides of a section of the gate line 71 protrude to respectively form a first protruding region 71a ₁ and a second protruding region 71a ₂ , and a hollow region 71b is formed between the first protruding region 71a 1 and the second protruding region 71a ₂ . The second protruding region _71a2 is in the middle, and the section is divided into a first part and a second part. The first portion and the second portion serve as a first gate 72 ₁ and a second gate 72 ₂ respectively. A first active layer 73 ₁ and a second active layer 73 ₂ are formed on the first gate 72 ₁ and the second gate 72 ₂ respectively. A source line 74 is substantially perpendicular to the extending direction of the gate line 71, across the overlapping region of the first active layer ₇₃₁ and the first part of the gate line and the second active layer ₇₃₂ and the gate line 71 in the overlapping area of the second part, and respectively have a first source 75 ₁ and a second source 75 ₂ on the overlapping area. A first drain line ₇₆₁ is substantially parallel to the extending direction of the source line 74, and a first pixel electrode ₇₈₁ spans the first active layer ₇₃₁ and the first part of the gate line 71 An overlapping region, and a first drain 77 ₁ is located on the overlapping region. Similarly, a second drain line ₇₆₂ is substantially parallel to the extending direction of the source line 74, and a second pixel electrode ₇₈₂ spans the second active layer ₇₃₂ and the gate line 71 is the overlapping area of the second part, and there is a second drain 77 ₂ on the overlapping area. Between the first source 75 ₁ and the first drain 77 ₁ , and between the second source 75 ₂ and the second drain 77 ₂ , are respectively the first active layer 73 ₁ and the second active layer 73 ₂ defines a channel area.

The structure is a double thin film transistor structure, which includes two parallel first thin film transistors and second thin film transistors. The first thin film transistor includes a first gate 72 ₁ , a first active layer 73 ₁ , a first source 75 ₁ , and a first drain 77 ₁ ; while the second thin film transistor includes a second gate 72 ₂ , a second active layer 73 ₂ , second source 75 ₂ , and second drain 77 ₂ . In addition, it should be noted that in the figure, the source line 74 slightly bends toward the first and second drain lines 76 ₁ and 76 ₂ when passing through the first and second thin film transistors, but the source line 74 can also be a straight line, that is, It only needs to extend along a direction substantially perpendicular to the extending direction of the gate lines 71 .

In the LCD device of this embodiment, when the structural size and the manufacturing process precision change, the C _GD will not change accordingly due to the manufacturing process precision change. As shown in the figure, the distances between the edge of the source line 74 and the edge of the overlapping area of the two active layers 73 ₁ /73 ₂ and the gate line 71 in the X direction are L _X11 and L _X12 respectively, and the two drain lines 76 ₁ The distances between the edges of the two active layers 73 ₁ , 73 ₂ and the overlapping _areas of the gate line 71 in the X direction are L _X21 and L _X22 , and the distances in the Y direction are _LY1 and _LY2 . If the exposure machine has the accuracy variation of ±D _X and ±D _Y in the X and Y directions respectively, then when L _X11 , L _X12 , L _X21 , and L _X22 are designed to be greater than D _X , and _LY1 and _LY2 are designed to be greater than When D _Y , even if the exposure accuracy of the exposure machine deviates, the overlapping area of the source line 74, the first drain line ₇₆₁ and the gate line 71, and the overlapping area between the source line 74, the second drain line ₇₆₂ and the gate line The overlapping area of the line 71 can be kept constant, so that the C _GD of the first and second thin film transistors have little variation.

The formation process of this dual TFT LCD device is similar to the formation process of the LCD device with a single TFT structure in FIG. 4A . For the sake of brevity, FIGS. 8A to 8E present plan views of the formation process of a pixel unit in the LCD device of FIG. 7 , and the drawing and related description of the cross-sectional views are omitted. The forming process includes the following steps.

First, a conductive film is formed on an insulating substrate (such as a glass substrate), wherein the material of the conductive film is, for example, a low-resistance metal such as aluminum or chromium or an alloy thereof, formed in a single-layer or multi-layer structure, and Formation methods are, for example, conventional deposition procedures of sputtering. Then, a process of exposure, development and etching is used to pattern the conductive film, so as to form a gate line 71 on the insulating substrate. As shown in FIG. 8A , the two sides of a section of the gate line 71 protrude to form a first protruding area 71a ₁ and a second protruding area 71a ₂ , and have a hollow area 71b to separate the area. The segments are separated into a first gate 72 ₁ and a second gate 72 ₂ .

Next, on the surface of the structure produced in the above steps, a gate insulating film (such as a nitride layer) and a semiconductor layer made of amorphous silicon (such as an amorphous silicon layer doped with N-type impurities) are formed. silicon layer). Formation methods are, for example, conventional deposition procedures using plasma chemical vapor phase. Afterwards, the amorphous silicon is patterned so that on the first gate 72 ₁ (the gate insulating film adjacent thereto), and the second gate 72 ₂ (the gate insulating film adjacent thereto), A first active layer 73 ₁ and a second active layer 73 ₂ are respectively formed, as shown in FIG. 8B .

Next, a conductive film is formed on the entire surface of the structure produced in the above steps. The material of the conductive film is, for example, a low-resistance metal such as aluminum or chromium or an alloy thereof, and is formed in a single-layer or multi-layer structure, and the forming method is, for example, a traditional deposition process using sputtering. Then, a process of exposure, development and etching is used to pattern the conductive film to form a source line 74 , a first drain line 76 ₁ , and a second drain line 76 ₂ . Referring to FIG. 8C, the patterning procedure is to make the source line 74 cross the first active layer 731, the second active layer ₇₃₂ and the gate line ₇₁ according to the extending direction substantially perpendicular to the gate line 71. The overlapping region, and making the first drain line ₇₆₁ and the second drain line ₇₆₂ substantially parallel to the extending direction of the source line 74, are respectively predetermined to form a first drain line from one side of the gate line. The area of the first and second electrodes spans the overlapping area of the first active layer 73 ₁ and the second active layer 73 ₂ with the gate line 71 .

Next, a passivation film is formed on the entire surface of the structure produced in the above steps. The passivation film is, for example, a nitride film. The forming method is, for example, a conventional deposition process of plasma CVD. Subsequently, a process of exposure, development and etching is carried out in the passivation film to form a first contact hole 86 ₁ and a second contact hole 86 ₂ , so that the first drain line 76 ₁ and the second drain line A portion of the area ₇₆₂ is exposed, as shown in Figure 8D.

Next, form a transparent conductive material, such as indium tin oxide or indium zinc oxide, on the entire surface of the structure produced in the above steps, and use an etching process to pattern the conductive material so that the conductive material is connected To the exposed surfaces of the first drain line 76 ₁ and the second drain line 76 ₂ , a first pixel electrode 78 ₁ and a second pixel electrode 78 ₂ are formed. Referring to FIG. 8E , the patterning process is to form the first pixel electrode ₇₈₁ on a part of the first drain line ₇₆₁ , the first contact hole ₈₆₁ and the adjacent passivation film of the first thin film transistor; The second pixel electrode 78 ₂ is formed on a part of the second drain line 76 ₂ , on the second contact hole 86 ₂ and on the adjacent passivation film of the second thin film transistor. In this way, the first pixel electrode ₇₈₁ can be connected to the first drain line ₇₆₁ through the first contact hole ₈₆₁ , and the second pixel electrode ₇₈₂ can be connected to the second drain line through the second contact hole _862. polar line 76 ₂ .

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention should be as defined by the scope of the patent application.

Claims (8)

1. liquid crystal indicator is characterized in that comprising:

One gate line is formed on the insulated substrate;

Wherein one side of a section is protruded and is formed a raised zones in the middle of this gate line, and this section has the zone of caving in and is right against described raised zones;

One pixel electrode is formed on the described insulated substrate;

One active layers is formed on the described section;

The one source pole line according to substantially perpendicular to the bearing of trend of described gate line, extends beyond the border of described active layers across the overlapping region of described active layers and described gate line; And

One drain line couples described pixel electrode, electrically connects with described pixel electrode, and according to the bearing of trend that is parallel to described source electrode line substantially, across the overlapping region of described active layers and described section.

2. liquid crystal indicator as claimed in claim 1 is characterized in that, the another side that described section is right against described protrusion limit is to cave in and form the described zone of caving in.

3. liquid crystal indicator as claimed in claim 1 is characterized in that, described section has a hole region and is right against described raised zones, and forms the described zone of caving in.

4. the structure of a liquid crystal indicator is characterized in that comprising:

One gate line is formed on the insulated substrate,

Wherein the both sides of a section are protruded and are formed first and second raised zones respectively in the middle of this gate line, and have a hole region in the middle of described first and second raised zones and described section is separated into first and second portion;

One first and one second active layers is formed at respectively in the first and second portion of described gate line;

One first and one second pixel electrode is formed at respectively on the described insulated substrate;

The one source pole line is according to substantially perpendicular to the bearing of trend of described gate line, across the overlapping region of described first active layers and described first and the overlapping region of described second active layers and described second portion; And

One first and one second drain line couples described first and second pixel electrode respectively, and according to the bearing of trend that is parallel to described source electrode line substantially, respectively across described first and second active layers respectively with the overlapping region of described first and second part.

5. the formation method of a liquid crystal indicator is characterized in that comprising:

On an insulated substrate, form a gate line,

One side of a section is protruded and is formed a raised zones in the middle of the wherein said gate line, and has the zone of caving in and be right against described raised zones;

On described section, form an active layers;

A definition one source pole line and a drain line on described active layers and insulated substrate, to make described source electrode line according to the border of coming to extend beyond described active layers substantially perpendicular to the bearing of trend of described gate line across the overlapping region of described active layers and described gate line, and make described drain line according to the bearing of trend that is parallel to described source electrode line substantially, protrude the side one predetermined zone that forms a pixel electrode by described gate line, across the overlapping region of described active layers and described gate line; And

Form a pixel electrode in described picture element electrode zone, electrically connect with described drain line.

6. the formation method of liquid crystal indicator as claimed in claim 5 is characterized in that, the another side that described section is right against described protrusion limit is to cave in and form the described zone of caving in.

7. the formation method of liquid crystal indicator as claimed in claim 5 is characterized in that, described section has a hole region, is right against described raised zones and forms the described zone of caving in.

8. the formation method of a liquid crystal indicator is characterized in that comprising:

On an insulated substrate, form a gate line,

The both sides of a section are protruded and are formed first and second two raised zones respectively in the middle of the wherein said gate line, and have a hole region in the middle of described first and second raised zones and this section is separated into first and second portion;

On the first of described gate line and second portion, form first and second active layers respectively;

Described first, definition one source pole line on second active layers and the insulated substrate, and respectively on described first and second active layers and insulated substrate the definition first and second drain line, with make described source electrode line according to substantially perpendicular to the bearing of trend of described gate line across the overlapping region of described first active layers and described first and the overlapping region of described second active layers and described second portion, and make described first and second drain line according to the bearing of trend that is parallel to described source electrode line substantially, respectively by described gate line wherein the predetermined zone that forms first and second electrode of a side one across described first and second active layers respectively with the overlapping region of described first and second part; And

Form described first and second pixel electrode, electrically connect with described first and second drain line respectively.

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