CN1620718A - 在衬底表面上形成不同厚度氧化层的方法 - Google Patents
在衬底表面上形成不同厚度氧化层的方法 Download PDFInfo
- Publication number
- CN1620718A CN1620718A CNA028281977A CN02828197A CN1620718A CN 1620718 A CN1620718 A CN 1620718A CN A028281977 A CNA028281977 A CN A028281977A CN 02828197 A CN02828197 A CN 02828197A CN 1620718 A CN1620718 A CN 1620718A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- initial
- thickness
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H10D64/0134—
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- H10D64/01342—
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- H10D64/01344—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
- H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0144—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0181—Manufacturing their gate insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10207122.5 | 2002-02-20 | ||
| DE10207122A DE10207122B4 (de) | 2002-02-20 | 2002-02-20 | Ein Verfahren zur Herstellung von Schichten aus Oxid auf einer Oberfläche eines Substrats |
| US10/208,308 | 2002-07-30 | ||
| US10/208,308 US6703278B2 (en) | 2002-02-20 | 2002-07-30 | Method of forming layers of oxide on a surface of a substrate |
| PCT/US2002/040807 WO2003073491A1 (en) | 2002-02-20 | 2002-12-20 | Method of forming layers of oxide of different thicknesses on a surface of a substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1620718A true CN1620718A (zh) | 2005-05-25 |
| CN1315162C CN1315162C (zh) | 2007-05-09 |
Family
ID=27766671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB028281977A Expired - Fee Related CN1315162C (zh) | 2002-02-20 | 2002-12-20 | 在衬底表面上形成氮氧化层和氧化层的方法 |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1476899B1 (zh) |
| JP (1) | JP4145802B2 (zh) |
| CN (1) | CN1315162C (zh) |
| AU (1) | AU2002351408A1 (zh) |
| TW (1) | TWI278038B (zh) |
| WO (1) | WO2003073491A1 (zh) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7550349B2 (en) | 2005-12-14 | 2009-06-23 | Dongbu Electronics Co., Ltd. | Method for forming gate dielectric layers |
| CN108257860A (zh) * | 2018-01-19 | 2018-07-06 | 武汉新芯集成电路制造有限公司 | 一种栅极氧化层的制作方法 |
| CN110730760A (zh) * | 2017-03-08 | 2020-01-24 | 耐诺维尔德有限公司 | 提供多个纳米线的装置和方法 |
| CN113921469A (zh) * | 2020-09-25 | 2022-01-11 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
| WO2022151650A1 (zh) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
| US12119222B2 (en) | 2021-01-14 | 2024-10-15 | Changxin Memory Technologies, Inc. | Method for preparing semiconductor structure and semiconductor structure |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6033943A (en) * | 1996-08-23 | 2000-03-07 | Advanced Micro Devices, Inc. | Dual gate oxide thickness integrated circuit and process for making same |
| US6087236A (en) * | 1998-11-24 | 2000-07-11 | Intel Corporation | Integrated circuit with multiple gate dielectric structures |
| US6235590B1 (en) * | 1998-12-18 | 2001-05-22 | Lsi Logic Corporation | Fabrication of differential gate oxide thicknesses on a single integrated circuit chip |
| KR20010004417A (ko) * | 1999-06-28 | 2001-01-15 | 김영환 | 반도체장치의 듀얼 게이트산화막 형성 방법 |
-
2002
- 2002-12-20 JP JP2003572081A patent/JP4145802B2/ja not_active Expired - Fee Related
- 2002-12-20 WO PCT/US2002/040807 patent/WO2003073491A1/en not_active Ceased
- 2002-12-20 AU AU2002351408A patent/AU2002351408A1/en not_active Abandoned
- 2002-12-20 EP EP02787067A patent/EP1476899B1/en not_active Expired - Lifetime
- 2002-12-20 CN CNB028281977A patent/CN1315162C/zh not_active Expired - Fee Related
-
2003
- 2003-02-19 TW TW092103374A patent/TWI278038B/zh not_active IP Right Cessation
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7550349B2 (en) | 2005-12-14 | 2009-06-23 | Dongbu Electronics Co., Ltd. | Method for forming gate dielectric layers |
| CN110730760A (zh) * | 2017-03-08 | 2020-01-24 | 耐诺维尔德有限公司 | 提供多个纳米线的装置和方法 |
| CN110730760B (zh) * | 2017-03-08 | 2023-11-21 | 耐诺维尔德有限公司 | 提供多个纳米线的装置和方法 |
| CN108257860A (zh) * | 2018-01-19 | 2018-07-06 | 武汉新芯集成电路制造有限公司 | 一种栅极氧化层的制作方法 |
| CN113921469A (zh) * | 2020-09-25 | 2022-01-11 | 台湾积体电路制造股份有限公司 | 半导体器件及其制造方法 |
| US12369385B2 (en) | 2020-09-25 | 2025-07-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plural gate oxide structures with different thicknesses in semiconductor devices |
| WO2022151650A1 (zh) * | 2021-01-14 | 2022-07-21 | 长鑫存储技术有限公司 | 半导体结构的制备方法及半导体结构 |
| US12119222B2 (en) | 2021-01-14 | 2024-10-15 | Changxin Memory Technologies, Inc. | Method for preparing semiconductor structure and semiconductor structure |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1315162C (zh) | 2007-05-09 |
| TW200304187A (en) | 2003-09-16 |
| EP1476899B1 (en) | 2007-03-07 |
| AU2002351408A1 (en) | 2003-09-09 |
| TWI278038B (en) | 2007-04-01 |
| JP4145802B2 (ja) | 2008-09-03 |
| JP2005518675A (ja) | 2005-06-23 |
| EP1476899A1 (en) | 2004-11-17 |
| WO2003073491A1 (en) | 2003-09-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ADVANCED MICRO DEVICES INC Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20100708 |
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| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, USA TO: GRAND CAYMAN ISLAND RITISH CAYMAN ISLANDS |
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| TR01 | Transfer of patent right |
Effective date of registration: 20100708 Address after: Grand Cayman, Cayman Islands Patentee after: Globalfoundries Semiconductor Inc. Address before: American California Patentee before: Advanced Micro Devices Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070509 Termination date: 20161220 |