CN1610485A - Inspection method of test points before printed circuit board layout drawing - Google Patents

Abstract

A method for inspecting test points before a printed circuit board layout chart is plotted. Firstly, providing a layout text data, and drawing the layout text data into a printed circuit board layout. Next, name data of a plurality of nodes in the layout character data is collected. Then, the layout data of a plurality of available test points in the layout character data is collected. Then, the validity of the available test points is analyzed to select a plurality of valid test points. Then, an actual test point of each node is selected from the valid test points. Then, the distribution data of the nodes and the actual test points are analyzed.

Description

Inspection method of test points before printed circuit board layout drawing

technical field

The invention relates to a method for checking test points of a printed circuit board (PCB), in particular to a method for checking test points before a printed circuit board layout drawing is drawn.

Background technique

The printed circuit board is a key component of an electronic device. Its main function is to fix the parts and connect the circuits between the parts to provide a stable circuit environment. According to the way of circuit configuration, printed circuit boards can be divided into single-sided boards, double-sided boards and multi-layer boards. Among them, the single-sided board uses the insulating substrate as the support body when the parts are installed, and the metal lines connecting the parts are laid out on the insulating substrate. As the functions of electronic devices become increasingly diversified, the number of parts will also increase, and the circuit design will become more complicated. Single-sided boards will not be enough for use, and double-sided boards will come in handy at this time. The double-sided board is to arrange the circuit on the front and back of the insulating substrate, and arrange the circuit vias on the insulating substrate to connect the circuits on the front and the back. In addition, the multi-layer board is used in a more complex circuit environment, which arranges the circuit into a multi-layer structure and presses it together, and lays out circuit through holes between each layer to connect the circuits of each layer.

Please refer to FIG. 1 , which shows a flowchart of a conventional method for forming a printed circuit board. First, in step 10, the circuit designer designs a component circuit diagram. Then, enter step 11, the layout personnel use the printed circuit board layout software tool to carry out the layout operation of the component circuit diagram. At first, the layout image displayed on the computer screen will be a bit messy, and the layout personnel can arrange the parts and circuits neatly. Then, enter step 12, the layout personnel visually view the layout image displayed on the computer screen, and use the printed circuit board layout software tool to configure the test points of the nodes in the layout diagram. A node is defined as a connection between any two parts, and a node must be matched with a test point. Then, enter step 13, the layout personnel directly visually inspect the distribution of test points in the layout image on the computer screen, and check whether each node is matched with a test point. Then, enter step 14, the layout personnel convert the final result of the layout image into a layout text data and output it. Wherein, the layout text data at least includes the name data of all nodes on the printed circuit board, the layout data of all test points, the layout data of all parts and so on.

Then, enter step 15, use specific drawing software to output the layout text data into a printed circuit board layout, such as a Gerber file (Gerber file), and send it to the printed circuit board manufacturer. Then, enter step 16, the printed circuit board manufacturer will manufacture printed circuit boards according to the printed circuit board layout drawing. Next, enter step 17, and use equipment to detect the electrical quality of the printed circuit board. Wherein, the equipment will be made according to the layout text data, and there are many probes on the equipment, and these probes are used for contacting the test points on the front and back of the printed circuit board, so as to conduct the electrical test of the printed circuit board.

It should be noted that before the layout of the printed circuit board is drawn, the distribution of the pilot points is inspected manually, which results in the layout personnel having to spend a lot of work time. Once the layout personnel are distracted, inattentive or distracted, it is easy for the layout personnel to ignore the inspection operation of some test points, which virtually increases the production risk of the printed circuit board. When the distance of some test points is smaller than the diameter of the probe or some test points are covered by parts and not checked by the layout personnel, it will affect the electrical quality and measurability of the printed circuit board, and increase the number of unqualified printed circuit boards. The scrap rate, the production time of the equipment and the production cost of the equipment are quite uneconomical.

Contents of the invention

In view of this, the object of the present invention is to provide a method for checking the test points before the layout of the printed circuit board, which can be used to check the test points before the layout of the printed circuit board is given to the manufacturer of the printed circuit board. Know the distribution of all test points. On the one hand, the problem of the test point can be found and solved earlier, on the other hand, the electrical quality and measurability rate of the printed circuit board can be improved, and the scrap rate of the unqualified printed circuit board, the production time of the equipment and the production cost of the equipment can be reduced. , which is quite economical.

According to the purpose of the present invention, a method for checking test points before the printed circuit board layout is drawn is proposed. Firstly, a layout text data is provided, and the layout text data can be output as a printed circuit board layout diagram. Next, collect name data of several nodes in the layout text data. Then, the layout data of several available test points in the layout text data are collected. Then, the validity of these available test points is analyzed to select several valid test points. Then, an actual test point of each node is selected from these valid test points. Then, analyze the distribution data of these nodes and these actual test points.

In order to make the above-mentioned purpose, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 shows a flowchart of a conventional method of forming a printed circuit board.

FIG. 2 shows a flow chart of a method for inspecting test points before a printed circuit board layout drawing according to Embodiment 1 of the present invention.

FIG. 3 shows a flow chart of a method for inspecting test points before the printed circuit board layout is drawn according to Embodiment 2 of the present invention.

Detailed ways

Embodiment one

Please refer to FIG. 2 , which shows a flow chart of a method for inspecting test points before a printed circuit board layout drawing according to Embodiment 1 of the present invention. Firstly, in step 20, a layout text data is provided, and the layout text data can be output as a printed circuit board layout diagram. Next, enter step 21, collect the name data of several nodes in the layout text data. Then, enter step 22, collect the layout data of several available test points in the layout text data. Wherein, the layout data of these available test points includes the position coordinates of each available test point on a printed circuit board, the name of the node connected to each available test point and the test point type of each available test point, the test point of each available test point Types are, for example, flat test points, through-holes, and component feet.

Next, enter step 23, analyze the effectiveness of these available test points, to select several valid test points. For example, according to the layout data of the available test points, it is determined whether the distance between any two available test points is smaller than a default value to determine the validity of the available test points. When the distance between the two available test points is less than the default value, select one of the two available test points as an effective test point; when the distance between the two available test points is greater than or equal to the default value, define two Available test points are two valid test points. Wherein, the default value may be the diameter value of the probe used by those skilled in the art, such as 50, 75 or 100 mils (mil).

Then, enter step 24, select an actual test point of each node from these valid test points. For example, an actual test point of each node is selected from the effective test points in the order of the test point types of the plane test point, the through hole and the component foot. Then, enter step 25, analyze the distribution data of these nodes and these actual test points, as shown in Table 1. Item (A) of Table 1 shows the measurability rate, which is obtained by dividing the number of nodes with actual test points by the number of these nodes. Among them, the measurable rate is, for example, 96%. As shown in item (B) of Table 1, the distribution data of these nodes and these actual test points also includes the distribution number and distribution ratio of these actual test points on the front and back of a printed circuit board. Wherein, the number of actual test points on the front side is 74, and the number of actual test points on the back side is 278, so the ratio of the front side test points is 20%, and the ratio of the back side test points is 80%. Of course, there are also data on the number of measuring points on the front and back planes and the number of through holes. As shown in item (C) of Table 1, the distribution data of these nodes and these actual test points also includes the number of nodes whose number of connected parts is less than 2, that is, the number of NC (not connect) points. Wherein, the number of NC points is 18, for example.

As shown in item (D) of Table 1, the distribution data of these nodes and these actual test points also includes the distribution data of the distance between these actual test points and the applicable probe specifications. Among them, the two actual test points with a distance between 50 (mil) and 75 (mil) can be individually applied to probes with a diameter of 50 (mil), and suitable for probes with a diameter of 50 (mil). The number of positive actual test points is 14 for example. Two actual test points with a distance between 75 (mil) and 100 (mil) can be individually applied to probes with a diameter of 75 (mil), and are suitable for the front of a probe with a diameter of 75 (mil) The number of actual test points is 9, for example. Two actual test points with a distance of more than 100 (mil) can be individually applied to a probe with a diameter of 100 (mil), and the number of actual test points on the front of a probe with a diameter of 100 (mil) is, for example, for 51. Since the smaller the diameter of the probe, the more expensive it is, the present invention can use the distribution data of the distance between the actual test points and the applicable probe specification to reduce the cost of the probe used.

In addition, the distribution data of these nodes and these actual test points also includes the name data of nodes lacking an actual test point, that is, the name data of nodes without actual test points, which are omitted here and not shown in Table 1.

Table I (A) Measurable rate: 352/366=96% (B) Number of positive actual test points: 74 Positive ratio: 20% Number of front plane test points: 74 Number of front through holes: 0 Number of actual test points on the back: 278 Back ratio: 80% Number of backplane test points: 263 Number of rear through holes: 15 (C) Number of nodes (NC points) whose number of connected parts is less than 2: 18 (D) Applicable Probe Specifications 50(mil) 75(mil) 100(mil)

Number of positive actual test points 14 9 51 Number of actual test points on the back 96 50 132 number of probes required 110 59 183 Ratio of required probes (%) 30 16 50

When the layout personnel get the above-mentioned distribution data of these nodes and these actual test points, the layout personnel can modify the layout text data. After modification, this inspection method can be executed again. In this way, under repeated inspection operations, the present invention can reduce the degree of missed inspection of test points and improve the testability rate of the printed circuit board.

Embodiment two

Please refer to FIG. 3 , which shows a flow chart of a method for inspecting test points before the printed circuit board layout is drawn according to Embodiment 2 of the present invention. Firstly, in step 30, a layout text data is provided, and the layout text data can be output as a printed circuit board layout diagram. Then, enter step 31, collect the name data of several nodes in the layout text data. Then, enter step 32, collect the layout data of several available test points in the layout text data. Wherein, the layout data of these available test points includes the position coordinates of each available test point on a printed circuit board, the name of the node connected to each available test point and the test point type of each available test point, the test point of each available test point Types are, for example, flat test points, through-holes, and component feet. Then, enter step 33, collect the layout data of several parts in the layout text data. Among them, the layout data of these parts includes the position coordinates of each part on the printed circuit board, the size of each part, the name of the node connected to each part, and the type of each part, such as surface mount technology (SMT) components Or pin insertion type (pin through hole, PTH) components.

Then, enter step 34, analyze the effectiveness of these available test points, to select several effective test points. For example, according to the layout data of the available test points and the layout data of the parts, it is judged whether the available test points are pressed by the parts to determine the validity of the available test points. When an available test point is pressed by these parts, define this available test point as an invalid test point; when an available test point is not pressed by these parts, define this available test point as a valid test point.

Alternatively, the validity of the available test points is determined by judging whether the distance between any two available test points is smaller than a default value. When the distance between the two available test points is less than the default value, select one of the two available test points as an effective test point; when the distance between the two available test points is greater than or equal to the default value, define two Available test points are two valid test points. Wherein, the default value may be the diameter value of the probe used by those skilled in the art, such as 50, 75 or 100 mils (mil).

In addition, the present invention can also first determine whether these available test points are pressed by these parts, and then determine whether the distance between any two available test points that are not pressed by these parts is less than a default value to determine the validity of the available test points . For example, first, judge whether these available test points are pressed by these parts; when an available test point is pressed by these parts, define the available test point as an invalid test point; when an available test point is not pressed by these parts , define the available test point as a test point outside the part. Then, judge whether the distance between the test points outside any two parts is less than a default value; when the distance between the test points outside the two parts is less than the default value, select one of the test points outside the two parts The test point is a valid test point; when the distance between the test points outside the two parts is greater than or equal to the default value, the test points outside the two parts are defined as two valid test points.

In addition, the present invention can also first determine whether the distance between two available test points is less than a default value, and then determine whether the two available test points are pressed by these parts to determine the validity of the available test points. First, judge whether the distance between any two available test points is less than a default value; when the distance between the two available test points is less than the default value, select one of the two available test points as a preset test point ; When the distance between two available test points is greater than or equal to the default value, define the two available test points as two preset test points. Then, judge whether these preset test points are pressed by these parts; When a preset test point is pressed by these parts, define this preset test point as an invalid test point; When a preset test point is not pressed by these parts When pressed, define the preset test point as an effective test point.

After the validity of these available test points is analyzed, it enters step 35 to select an actual test point for each node from these effective test points. For example, an actual test point of each node is selected from the effective test points in the order of the test point types of the plane test point, the through hole and the component foot. Then, enter step 36, analyze the distribution data of these nodes and these actual test points.

Wherein, the distribution data of these nodes and these actual test points includes a measurable rate obtained after the number of nodes with actual test points/the number of these nodes, the number of these actual test points on the front and back of a printed circuit board The distribution number and distribution ratio, the number of nodes connected with the number of parts less than 2, the distribution data of the distance between these actual test points and the applicable probe specifications and the name data of nodes lacking an actual test point, the results As described in Table 1, it will not be repeated here.

The inspection method of the test points before the layout of the printed circuit board disclosed in the above-mentioned embodiments of the present invention can check the test points before the layout of the printed circuit board is given to the manufacturer of the printed circuit board, so as to know all the test points distribution status. On the one hand, the problem of the test point can be found and solved earlier, on the other hand, the electrical quality and measurability rate of the printed circuit board can be improved, and the scrap rate of the unqualified printed circuit board, the production time of the equipment and the production cost of the equipment can be reduced. , quite economical

In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Those skilled in the art can make various changes without departing from the spirit and scope of the present invention. Changes and modifications, so the scope of protection of the present invention should be based on the appended claims.

Claims (10)

1. A method for checking test points before a printed circuit board layout drawing, comprising: Provide a layout text data, the layout text data can be drawn as a printed circuit board layout diagram; Collect the name data of multiple nodes in the layout text data; Collect layout data of multiple available test points in the layout text data; Analyzing the validity of the available test points to select a plurality of effective test points; selecting an actual test point for each of the nodes from the valid test points; and Analyzing the distribution data of the nodes and the actual test points. 2. The method as claimed in claim 1, wherein the layout data of the available test points includes position coordinates of each of the available test points on a printed circuit board, the name of the node connected to each of the available test points, and each of the available test points. test point types of available test points, and the method further includes in the step of analyzing the validity of said available test points: Judging whether the distance between any two available test points is less than a default value; When the distance between the two available test points is less than the default value, select one of the two available test points as an effective test point; and When the distance between the two available test points is greater than or equal to the default value, define the two available test points as two valid test points. 3. The method according to claim 1, the method further comprises between the step of collecting the layout data of a plurality of available test points in the layout text data and the step of analyzing the validity of the available test points: Layout data of a plurality of parts in the layout text data is collected. 4. The method as claimed in claim 3 , wherein the layout data of the available test points includes the position coordinates of each of the available test points on a printed circuit board, the name of the node connected to each of the available test points, and each of the available test points. The test point type of available test points, and the layout data of the parts include the position coordinates of each part on the printed circuit board, the size of each part, the type of each part and the name of the node connected to each part , and the method further includes in the step of analyzing the validity of the available test points: judging whether the available test point is pressed by the part; defining an available test point as an invalid test point when the available test point is pressed by the part; and When an available test point is not pressed by the part, the available test point is defined as an effective test point. 5. The method according to claim 4, wherein the distribution data of the nodes and the actual test points includes the number of the nodes whose number of connected parts is less than two. 6. The method as claimed in claim 1, wherein the method further comprises in the step of selecting an actual test point of each node from the effective test points: According to the order of the test point types of the plane test point, the through hole and the part foot, an actual test point of each node is selected from the effective test points. 7. The method as claimed in claim 1, wherein the distribution data of the nodes and the actual test points comprises a measurable rate obtained after the number of the nodes with the actual test points/the number of the nodes . 8. The method as claimed in claim 1, wherein the distribution data of the nodes and the actual test points comprises distribution numbers and distribution ratios of the actual test points on the front and back of a printed circuit board. 9. The method according to claim 1, wherein the distribution data of the nodes and the actual test points comprises the distribution data of the distance between the actual test points. 10. The method of claim 1, wherein the distribution data of the nodes and the actual test points include name data and applicable probe specifications of the nodes lacking an actual test point.

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