CN1681048A - Testing method of memory address line - Google Patents

Abstract

The invention relates to a method for testing memory address lines. It mainly uses the method of "walking 1" or "walking 0" to select the address unit of the memory, and writes test data in the address unit, and the data bit corresponding to the address line to be tested is "0". , and the rest of the data bits are "1"; perform a walk test on all address lines, read the data in the first address unit and the last address unit of the memory, and determine the corresponding address line fault according to the "0" bit in the data .

Description

Memory Address Line Test Method

technical field

The invention relates to a method for testing memory address lines, in particular to a method for accurately locating address line faults by adopting the "step 0" and "step 1" methods.

Background technique

At present, the minimum CPU system on a single board generally includes CPU, FLASH and SDRAM and other devices. The CPU is the core of the single board and is used to execute various operations specified by the single board software. FLASH is an electrically erasable memory, even if the board is powered off, the program or data stored in it will not be lost. The CPU can easily read out the content in the FLASH, but only in certain circumstances can it be erased and written. SDRAM is a dynamic memory. After the board is powered off, the programs or data stored in it will be lost, and the CPU can easily read and write SDRAM. The characteristics of these two memories determine that the CPU reads and writes data in FLASH slowly, but reads and writes data in SDRAM faster. Therefore, the board software is generally stored in FLASH, and after the board is powered on for necessary initialization, the programs and data in the FLASH are moved to SDRAM to run, which can ensure a faster running speed of the board. The functions of SDRAM and FLASH on the single board are very important, so it is necessary to conduct a comprehensive test on its data lines, address lines and units.

At present, the "three-step test method" is generally adopted for the FLASH peripheral interconnection test, and its specific description is excerpted as follows:

Table 1 Summary table of the three-step test method test steps operate address data note first step Write A ₀ 0...000 A ₀ and A ₁ are two arbitrary different addresses, which are compared and judged while reading. Write A ₁ 1...111 read A ₀ 0...000 read A ₁ 1...111 second step a Write A ₀ 0...001 A ₀ , A ₁ ,..., _An are any set of addresses, and the addresses are required to be different. It is recommended to use a set of addresses incrementing from 0, and use the "walking 1" algorithm for the data lines. Write A ₁ 0...010  …  …  … Write _An 1...000 read A ₀ 0...001 read A ₁ 0...010  …  …  … read _An 1...000 second stepb Apply the "step 0" algorithm to the data line, and repeat the process of the second step a third stepa Write 0...000 D ₀ D ₀ , D ₁ , ... D _n are any set of distinguishable data. Apply the "walk 1" algorithm to the address lines. Write 0...001 D ₁ Write  …  … Write 1...000 D _n read 0...000 D ₀ read 0...001 D ₁ read  …  … read 1...000 D _n Step 3b Apply the "step 0" algorithm to the address line, and repeat the process of the third step a.

The first test is used to test whether there is an open circuit fault on the data line, the second test is used to test whether there is a short circuit fault on the data line, and the third test is used to test whether there is an open circuit or short circuit fault on the address line. Carry out fault diagnosis after all tests of data lines and address lines are completed.

The fault diagnosis of the first step test is relatively simple. If all 0s are written and all 0s are not read, it means that the data line has an S-A-1 (fixed to 1) fault, and the data line with a value of 1 is the fault line of S-A-1. Location. On the contrary, if writing 1 does not read all 1s, it means that the data line has an S-A-0 (fixed to 0) fault, and the data line with a value of 0 is the position of the data line where the S-A-0 fault occurs.

The second step of the test needs to judge the position of the data line of the short-circuit fault and what type of short-circuit fault is. Table 2 is a result of the second step of the test. An example is used to illustrate the fault diagnosis (data line b ₃ b ₂ b ₁ b ₀ , Test vector r ₀ r ₁ ... r ₇ ):

Table 2 The second step of the three-step test method (data line test) 1 2 3 4 5 6 7 8 expected value b ₂ open circuit SA-0 b ₂ and b ₁ open SA-0 b ₂ and b ₁ short circuit 0-dominant type b ₂ and b ₁ open circuit SA-1 b ₂ and b ₁ short circuit 1-dominant type b ₃ and b ₁ open circuit SA-0 b2 and b1 short circuit 0-dominant type b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ b ₃ b ₂ b ₁ b ₀ r ₀ 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 r ₁ 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 r ₂ 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 r ₃ 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 r ₄ 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 r ₅ 1 0 1 1 1 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 r ₆ 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 r ₇ 1 1 1 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0 0 1 1 0

When running the second-step test, the algorithm of "walking 1" and "walking 0" is carried out at the same time, in order to distinguish between 1-dominated short circuit and 0-dominated short circuit.

The diagnosis process for open circuit fault and short circuit fault of data line is as follows:

BEGIN

FOR actually tests each column V _i of the response matrix V

IF V _i does not agree with the corresponding column T _i of the expected response matrix T

report a fault;

Each component of IF V _i is fixed at 1

Report that an open circuit fault fixed to 1 has occurred on the i-th data line;

Each component of ELSE IF V _i is fixed to 0

Report that the i-th data line has an open circuit fault fixed at 0;

ELSE IF Find the result of the logical OR operation of the j-th column vector T _i and the i-th column vector T _i in the expected response matrix equal to V _i

Report the i-th data line and the j-th data line as short-circuit, and the fault type is 1-dominant short-circuit fault;

ELSE IF Find the result of the logical AND operation of the j-th column vector T _i and the i-th column vector T _i in the expected response matrix equal to V _i

Report the i-th data line and the j-th data line as short-circuit, and the fault type is 1-dominant short-circuit fault;

ELSE

The report failure type cannot be judged;

END IF

END IF

END FOR

IF there is no fault

Report that the data line test did not find any faults;

END.

Note that the above only judges the short circuit between two data lines. In fact, the short circuit of two or more data lines is also included in the two short circuit. The diagnosis results can be further analyzed to obtain the short circuit of two or more data lines. situation.

After ensuring that there is no fault in the data line, the third step of testing can be carried out to test the address line. The following is a result of the third step test, and an example is given to illustrate the fault diagnosis (address line a ₃ a ₂ a ₁ a ₀ , test Data D ₀ D ₁ ... D ₄ are different from each other):

Table 3 The third step of the three-step test method (address line test) 1 2 3 4 5 6 7 8 address expected value a ₂ open circuit SA-0 a ₂ and a ₁ open circuit SA-0 a ₂ and a ₁ short circuit 0-dominant type a ₂ and a ₁ open circuit SA-1 a ₂ and a ₁ short circuit 1-dominant type a ₃ and a ₀ open circuit SA-0 a ₂ and a ₁ short circuit 0-dominant type a ₃ a ₂ a ₁ a ₀ 0 0 0 0 D _{0 D3 D3 D3 D3} D ₀ D ₄ 0 0 0 1 D ₁ D ₁ D ₁ D ₁ D ₁ D ₁ D ₄ 0 0 1 0 _{D2 D2 D3 D3 D3 D3} D ₄ 0 1 0 0 _{D3 D3 D3 D3 D3 D3} D ₄ 1 0 0 0 D ₄ D ₄ D ₄ D ₄ D ₄ D ₄ D ₄ 1 1 1 1 D _{0 D3 D3} D _{0 D3 D3} D ₄ 1 1 1 0 D ₁ D ₁ D ₁ D ₁ D ₁ D ₁ D ₄ 1 1 0 1 _{D2 D2 D3 D3 D3 D3 D3} 1 0 1 1 _{D3 D3 D3 D3 D3 D3 D3} 0 1 1 1 D ₄ D ₄ D ₄ D ₄ D ₄ D ₄ D ₄

The diagnosis principle for address line open circuit fault and short circuit fault is the same. The general process is as follows:

BEGIN

The IF read data is consistent with the expected data

Report that the address line test found no faults;

ELSE

Translate all data into corresponding addresses in the order of writing, and obtain the expected response matrix T and the actual response matrix V;

FOR actually tests each column V _i of the response matrix V

Each component of IF V _i is fixed at 1

Report that an open circuit fault fixed to 1 has occurred on the i-th address line;

Each component of ELSE IF V _i is fixed to 0

Report that the i-th address line has an open circuit fault fixed at 0;

ELSE IF Find the result of the logical OR operation of the j-th column vector T _i and the i-th column vector T _i in the expected response matrix equal to V _i

Report that the i-th address line and the j-th address line are short-circuited, and the fault type is 1-dominant short-circuit fault;

ELSE IF Find the jth column vector T _i and the column vector T _i logical AND operation result equal to V _i in the expected response matrix

Report a short circuit between the i-th address line and the j-th address line, and the fault type is 0-dominant short-circuit fault;

ELSE

The report failure type cannot be judged;

END IF

END IF

END FOR

END.

Note that the above only judges the short circuit between two address lines, and the short circuit of two or more address lines can also be obtained by further analysis of the diagnosis results.

The shortcoming of prior art one:

After using the "three-step test method" to realize the FLASH test, in the process of testing and verifying the implementation by using the simulated fault method, it was found that the test program could not accurately locate the fault of the FLASH address line. After careful analysis, it was found that The third step of the "three-step test method" cannot accurately locate the fault of the FLASH address line. The following is a specific analysis of the third step of the "three-step test method".

In fact, the idea of the third step of the existing "three-step testing method" is not wrong, but there are problems with the specific method. The reason for the problem is that the characteristics of FLASH are ignored. In the test method, it is regarded as RAM. It is thought that a certain address can be written arbitrarily without erasing. In fact, FLASH must be erased before it can be written normally. That is, the write operation of FLASH can write 1 bits into 0, but cannot write 0 bits into 1.

Through analysis, it is found that the above table (Table 3) is not accurate, assuming that a ₂ and a ₁ are short-circuit 0-dominant faults, when data D ₂ is written to address 0010, the data is actually written to address 0000, Instead of address 0010, if you read the content of address 0010 at this time, you actually read the content of address 0000. Similarly, when data D ₃ is written to address 0100, address 0000 is also written, and the contents of address 0000 are actually read. Because the characteristic of FLASH is that it can be written as 0 for the bit of 1, but it cannot be written as 1 for the bit of 0. The final result is that the content stored in the 0000 address is the result of the "AND" of D ₂ and D ₃ , and it is also written in 1111 The input content is not as analyzed in the table. Therefore, step 3 can only determine that the address line is faulty, but cannot determine which address line (or several) the address line is faulty.

Contents of the invention

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for accurately locating address line faults of memory (including FLASH memory and RAM memory).

The method provided by the invention is as follows:

A kind of FLASH memory address line test method, comprises the following steps:

A) Erase all storage space of FLASH;

B) Select the address unit of FLASH with the "walking 1" method, write test data in the address unit, the data bit corresponding to the address line to be tested is "0", and the remaining data bits are "1" ";

C) Repeat step B until all address lines have completed the "walk 1" test;

D) Read the data in the first address unit of the FLASH, and determine that the address line at the corresponding position is faulty according to the arrangement position of "0" in the data.

The present invention provides a kind of FLASH memory address line testing method in addition, comprises the following steps:

A) Erase all storage space of FLASH;

B) Select the address unit of FLASH with the "walking 0" method, write test data in the address unit, the data bit corresponding to the address line to be tested is "0", and the remaining data bits are "1" ";

C) Repeat step B until all address lines have completed the "walk 0" test;

D) Read the data in the last address unit of the FLASH, and determine that the address line at the corresponding position is faulty according to the arrangement position of "0" in the data.

The invention provides a method for testing RAM memory address lines, comprising the following steps:

A) write all "1" on the first address unit of the RAM memory;

B) Select the address unit of the RAM with the "walking 1" method, write test data in the address unit, the data bit corresponding to the address line to be tested is "0", and the remaining data bits are "1" ";

C) Read the data in the first address unit of the RAM memory, and perform a "logic AND" operation with the last recorded data, and save the operation result (when reading for the first time, there is no "last recorded data", directly save the The read data can be saved);

D) Repeat step B and step C until all address lines have completed the test of "step 1";

E) According to the arrangement position of "0" in the final result, it is determined that the address line at the corresponding position is faulty.

The present invention provides a kind of RAM memory address line testing method in addition, comprises the following steps:

A) write all "1" on the last address unit of the RAM memory;

B) Select the address unit of RAM with the "walking 0" method, write test data in the address unit, the data bit corresponding to the address line to be tested is "0", and the remaining data bits are "1" ";

C) Read the data in the last address unit of the RAM memory, and perform a "logic AND" operation with the last recorded data, and save the operation result (when reading for the first time, there is no "last recorded data", directly save the The read data can be saved);

D) Repeat step B and step C until all address lines have completed the test of "walking 0";

E) According to the arrangement position of "0" in the final result, it is determined that the address line at the corresponding position is faulty.

According to the above methods of the present invention, if the number of data lines is less than that of address lines, the address lines are tested in batches, so that the number of address lines for each test is less than or equal to the data lines.

According to the above methods of the present invention, the size of the address unit is determined according to the number of bits of data lines of the memory.

The advantages of the present invention are as follows:

1. The FLASH and RAM memory can accurately locate which address line (or which) the fault occurs on, which makes up for the difficult problem of fault location of the address line in the existing test method.

2. The method of the present invention is simple and intuitive to operate. According to the read data, it is very intuitive to know which address line has a problem; the programming is very simple, and it is not necessary to carry out the test data and the expected data like the method in the prior art. Operation and comparison greatly reduce the complexity of programming.

Detailed ways

The present invention locates which address lines have fixed low level and sticky 0-dominant faults with the method of "walking 1" of address lines; uses the method of "walking 0" of address lines to locate which address lines have fixed high level and Sticky 1-dominant type of fault; when performing "walk 1" or "walk 0" test on the address, the data bit corresponding to the test data and the address line to be tested is required to be 0, and the other data bits are 1.

For the address line "walking 1" test, as shown in Table 4, taking the 8-bit address as an example, first assume that only the same type of wiring fault exists, and the fault mode is: a ₇ is always 0, a ₅ and a ₄ are short-circuited 0 -Dominant type, when this type of failure occurs, the program will write the test data to the unit with the address 00000000 when writing the test data (when there are multiple address line failures, it will write multiple times, if the address line is normal then The address unit will not be written), and finally only need to read the value in the 00000000 address, and which address lines are faulty can be known according to which bits (bits) are 0. After writing all the test data sequentially in Table 4, the read content of address 00000000 is 01001111. As shown in Table 4, when the address line is normal, the content in the address unit 00000000 should be 11111111, but the read result is 01001111, indicating that bit7, bit5, and bit4 have changed to 0, indicating that a ₇ , a ₅ and a ₄ has a problem. In this way, we can intuitively know which address line has a problem according to the read data.

Table 4 Three-step test method of the present invention tests FLASH memory address line 0-dominant fault example table

(address line "walk 1") address to write written data actual write address Read the content obtained from address 00000000 a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1

(The data in bold in the above table indicates that there is an error)

Because the read and write operations of FLASH and RAM are somewhat different, when testing RAM, first write all 1s into address 00000000, after writing the first test data, you can read and record the data in address 00000000, Then every time a number is written, read out the content of address 00000000 and perform a "logic AND" operation with the last recorded data, save the operation result, and finally know which address line has a problem according to the position of "0" in the result . As shown in Table 5 below, taking the 8-bit address as an example, assuming that the failure mode is: a ₇ is always 0, a ₅ is always 1, and the final result of the "logical AND" of the data read each time is 01011111. It can be known that there is a problem with a ₇ and a ₅ .

Table 5 Three-step test method of the present invention tests RAM memory address line 1 and 0-example table of dominant fault

(address line "walk 1") address to write written data actual write address The content obtained by reading the address 00000000 is actually the content in the address 00100000, assuming that the address 00100000 is an arbitrary number, such as: 01001100, but when writing 11111111 to the address 00000000, the content in the address 0010000 Rewritten to 11111111 a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1

(The data in bold in the above table indicates that there is an error)

If some address lines have 0-dominant faults and some have 1-dominant faults, assume that a ₇ is always 1, and a ₅ and a ₄ are short-circuited 0-dominant type. When reading address 00000000 here, the data read is not necessarily the data in address 00000000, but if the address line fails during the walking test (including "walking 1" and "walking 0" tests), the write and The readout will be the same address, so it will not affect the test results. For details, please refer to Table 6 below.

Table 6 Three-step test method of the present invention tests address line 1 and 0-example table of dominant fault

(address line "walk 1") address to write written data actual write address Read the content obtained from address 00000000 (since a ₇ is always 1, what is actually read is the content of address 10000000) a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 1 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 For the address line "walking 0" test, as shown in Table 7 below, taking the 8-bit address as an example, first assume that only the same type of wiring fault exists, and the fault mode is: a7 is always 1, and a ₅ and a ₄ are short-circuited 1- Dominant type, when this kind of failure occurs, the program will write the test data into the space with the address 11111111 when writing the test data, and finally only need to read the value in the address of 11111111, and judge which bits are 0 to know those addresses There is such a fault in the line. After writing all the test data in Table 7, the content of address 11111111 is 01001111, indicating that a ₇ , a ₅ and a ₄ have problems.

Table seven Three-step test method of the present invention tests address line 1-example table of dominant fault

(address line "walk 0") address to write written data actual write address The content obtained by reading the address of 11111111 a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1

If some address lines have 0-dominant faults and some have 1-dominant faults, assume that a ₇ is always 1, and a ₅ and a ₄ are short-circuited 0-dominant type. When reading address 11111111 here, the read data does not necessarily exist in address 11111111, but since the write and read are the same address during the test, it will not affect the test result. For details, please refer to Table 8.

Table 8 Three-step test method of the present invention tests address line 1 and 0-example table of dominant fault

(address line "walk 0") address to write written data actual write address Read the content obtained from address 11111111 (since a ₇ is always 1, a ₅ and a ₄ are always 0, what is actually read is the content of address 11001111) a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a ₁ a ₀ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 1 1

In fact, for the problem of various faults on the address line at the same time, the above two methods can be used to locate the exact position of the faulty connection, but the actual write address may not be 00000000 or 11111111, but it is still only necessary to read these two addresses. The content can be judged, because when reading these two addresses, what is read is actually the value in the written address.

According to above analysis, the flow process of step 3 (for FLASH memory) of the present invention is:

BEGIN

Erase FLASH space;

Write test data to each address in the way of "walking 1" (the data bit corresponding to the test data and the address line to be tested is 0, and the other bits are 1);

The 0 address space in IF FLASH is not all 1;

Report the address line test and find a fixed level (it may be fixed at low or high, but if you know which address line has a problem, the fault can be easily located), and print the content of the address space in binary mode;

ELSE

Report that the address line "walk 1" test did not find a fixed level fault;

END IF

Write test data to each address in the way of "walking 0" (the data bit corresponding to the test data and the address line to be tested is 0, and the other bits are 1);

The last address space in IF FLASH is not all 1;

Report the address line test and find a fixed level (it may be fixed to be high or it may be fixed to be low, but if you know which address line has a problem, the fault can be easily located), and print the content of the address space in binary mode;

ELSE

Report that the address line "walk 0" test did not find a fixed level fault;

END IF

END.

Note: The above process is to write a number, and then read the 0 address space or 1 address space of the memory until all the address lines have completed the walking test. After modifying the equipment test program according to the above process, and simulating various address line faults on the single board, the fault of which address line can be accurately located according to the reported data.

In actual operation, the FLASH peripheral interconnection test needs to be treated according to the specific application of FLASH in the system, and the data bus width and address space of FLASH need to be considered. For example, in a system, two pieces of FLASH with a data width of 16 bits are used in parallel, the data bus width is 32 bits, and the address range is 0xFD000000-0xFD7FFFFF. CPU address bus A29 is connected to A0 of 2 pieces of FLASH. The actual address line used is A[29:9] of CPU, which corresponds to A[0:20] of FLASH. There are 21 address lines in total, and the accessible space is 2M× 32bit, exactly 8M Bytes. When performing the address line "walking 1" test, the starting address of writing data is 0xFD000004, and the address of reading data is 0xFD000000. When performing the address line "walking 0" test, the starting address of writing data is 0xFD7FFFF8, and the address of reading data is 0xFD7FFFFC. The starting address line of the test is A29 of the CPU (A0 of the FLASH), the cycle is 21 times, and the 21 address lines are exactly covered. The basis for judging which addresses are wrong is to see which bits of the 32-bit data read from 0XFD000000 and 0XFD7FFFFC are data "0".

When the method of the present invention is actually used, if the number of memory data lines is less than that of address lines, the address lines need to be tested in batches so that the number of address lines tested each time is less than or equal to the data lines. If there is a single board with 8M Bytes FLASH, the data line is 16 bits, and the address line has 22 in total, the accessible space is 4M×16bit, and the number of data lines is less than the address line, so it is necessary to divide the address line twice After testing, first use the method described above to test the low 16-bit address line, and then use the same method to test the high-bit address line, so that you can easily locate the fault to which address line according to the read data.

For example: for the address line "walking 1" test, as shown in Table 9 below, taking the 22bit address as an example, for the sake of simplicity, first assume that there is only the same type of connection fault, and the fault mode is: a ₂₀ , a ₁₈ , a ₁₅ a ₇ is always 0, a ₅ and a ₄ short-circuit 0-dominant type,

Table nine three-step test method of the present invention test address line 0-example table of dominant fault

(address line "walk 1") address to write written data actual write address The content obtained by reading the address 0000000000000000000000 _{a 21} a ₂₀ a ₁₉ a ₁₈ a ₁₇ a ₁₆ a ₁₅ a ₁₄ a ₁₃ a ₁₂ a 11 a ₁₀ a 9 a ₈ a ₇ a ₆ a ₅ a ₄ a ₃ a ₂ a _{1 a 0} 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 1 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 0 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 1 0 0 1 1 1 1 1 1 1 11 1 1 1 1 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 1 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 1 0 0 0 1 1 1 1 1 1 1 11 1 1 1 0 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 1 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 1 0 0 0 0 1 1 1 1 1 1 1 11 1 1 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 1 0 0 0 0 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 1 0 0 0 0 0 0 1 1 1 1 1 1 1 11 0 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 1 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 10 0 0 0 0 0 0 0 1 1 1 1 1 1 1 01 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 10 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 0 1 1 1 1 1 1 0 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 0 0 1 1 1 1 1 0 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 0 0 0 1 1 1 1 0 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 1 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 0 0 0 0 1 1 1 0 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 1 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 0 0 0 0 0 1 1 0 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 1 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 00 1 0 0 0 0 0 00 0 0 0 0 0 0 0 1 0 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 1 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 1 1 1 1 0 0 0 0 0 01 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 1 1 1 1 1 1 10 1 0 0 1 1 1 1 The above is the first test, which tested the lower 16-bit address line, and the following is the second test, which tested the upper 6-bit address line 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 is all 1 after erasing 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 0 10 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 10 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 0 1 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 0 1 0 0 0 0 1 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 1 0 0 0 1 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 0 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 0 1 1 0 0 1 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 0 1 1 1 0 0 1 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 1 1 0 1 1 0 1 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 0 1 1 1 1 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 0 1 0 1 1 1 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 0 1 1 1 1 1 1 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 1 1 1 1 1 1 1 11 1 1 0 1 0 1 1 Note, as shown in the above table, a total of 2 tests are required. After the first test, the content read at the address unit 0000000000000000000000 is: 0111111101001111, where d ₄ , d ₅ , d ₇ , and d ₁₅ are 0, so it can be judged The corresponding a ₄ , a ₅ , a ₇ and a ₁₅ are faulty. After the second test, the content read at the address unit 0000000000000000000000 is: 1111111111101011, where d ₂ and d ₄ are 0, so it can be judged that the corresponding a ₁₈ (16+2) and a ₂₀ (16+4) have Fault. In this way, after two tests, the fault of the address line can be accurately located. The method of "walking 0" of the address line is the same as this processing method, and will not be repeated here.

Claims (12)

1, a kind of FLASH testing method of memory address line comprises the following steps:

A) wipe the whole memory spaces of FLASH;

B) choose the address location of FLASH with " walking 1 " method, write test data in address location, the described test data data bit corresponding with the address wire that needs test is " 0 ", and the remainder data position is " 1 ";

C) repeating step B is until all address wires are all finished " walking 1 " test;

D) read data in first address location of this FLASH, according to the arrangement position of " 0 " in the data, determine that the address wire of opposite position breaks down.

2, FLASH testing method of memory address line as claimed in claim 1 is characterized in that: if the quantity of data wire is lacked than address wire, then address wire is tested in batches, make the number of address lines of each test less than or equal to data wire.

3, FLASH testing method of memory address line as claimed in claim 1 or 2 is characterized in that: the size of described address location is determined according to the data wire figure place of memory.

4, a kind of FLASH testing method of memory address line comprises the following steps:

A) wipe the whole memory spaces of FLASH;

B) choose the address location of FLASH with " walking 0 " method, write test data in address location, the described test data data bit corresponding with the address wire that needs test is " 0 ", and the remainder data position is " 1 ";

C) repeating step B is until all address wires are all finished " walking 0 " test;

D) read data in last address location of this FLASH, according to the arrangement position of " 0 " in the data, determine that the address wire of opposite position breaks down.

5, FLASH testing method of memory address line as claimed in claim 4 is characterized in that: if the quantity of data wire is lacked than address wire, then address wire is tested in batches, make the number of address lines of each test less than or equal to data wire.

6, such as claim 4 or 5 described FLASH testing method of memory address lines, it is characterized in that: the size of described address location is determined according to the data wire figure place of memory.

7, a kind of RAM testing method of memory address line comprises the following steps:

A) the first address location of RAM memory is write entirely " 1 ";

B) choose the address location of RAM with " walking 1 " method, write test data in address location, the described test data data bit corresponding with the address wire that needs test is " 0 ", and the remainder data position is " 1 ";

C) read data in RAM memory the first address location, and carry out " logical AND " operation with last record data, operating result is preserved;

D) repeating step B and step C are until all address wires are all finished the test of " walking 1 ";

E) according to the arrangement position of " 0 " in the end product, determine that the address wire of opposite position breaks down.

8, RAM testing method of memory address line as claimed in claim 7 is characterized in that: if the quantity of data wire is lacked than address wire, then address wire is tested in batches, make the number of address lines of each test less than or equal to data wire.

9, such as claim 7 or 8 described RAM testing method of memory address lines, it is characterized in that: the size of described address location is determined according to the data wire figure place of memory.

10, a kind of RAM testing method of memory address line comprises the following steps:

A) last address location of RAM memory is write entirely " 1 ";

B) choose the address location of RAM with " walking 0 " method, write test data in address location, the described test data data bit corresponding with the address wire that needs test is " 0 ", and the remainder data position is " 1 ";

C) read data in last address location of RAM memory, and carry out " logical AND " operation with last record data, operating result is preserved;

D) repeating step B and step C are until all address wires are all finished the test of " walking 0 ";

E) according to the arrangement position of " 0 " in the end product, determine that the address wire of opposite position breaks down.

11, RAM testing method of memory address line as claimed in claim 10 is characterized in that: if the quantity of data wire is lacked than address wire, then address wire is tested in batches, make the number of address lines of each test less than or equal to data wire.

12, such as claim 10 or 11 described RAM testing method of memory address lines, it is characterized in that: the size of described address location is determined according to the data wire figure place of memory.