CN109801667A

CN109801667A - A kind of parallel static memory address wire out of circuit test method

Info

Publication number: CN109801667A
Application number: CN201811602061.XA
Authority: CN
Inventors: 张锐
Original assignee: CETC 20 Research Institute
Current assignee: CETC 20 Research Institute
Priority date: 2018-12-26
Filing date: 2018-12-26
Publication date: 2019-05-24
Anticipated expiration: 2038-12-26
Also published as: CN109801667B

Abstract

The present invention provides a kind of parallel static memory address wire out of circuit test methods, if parallel static memory has m root address wire, n root data line, then address wire is expressed as A from a high position to low level_m‑1~A₀, data line is expressed as D from a high position to low level_n‑1~D₀；When testing m root address wire, decimal number is first written in order respectively to decimal address；Then corresponding data is read again；The write-in data of identical address are subtracted each other with data are read respectively, if result is all 0, then address wire is without breaking phenomena；Otherwise, all write-in data are found out and read the address that data subtraction value is not 0, if any k address, just there is the open circuit of k root address wire, subtraction value is not the former write-in data decimal value i of 0 address is how many, means that A_iNumber address wire open circuit.The present invention saves the time of nearly one third than being currently known method, effectively shortens the testing time, improves work efficiency.

Description

A kind of parallel static memory address wire out of circuit test method

Technical field

The present invention relates to the test methods of SRAM a kind of.

Background technique

In recent years, with the rapid development of computer technology, integrated circuit technique, in board largely using based on BGA, The high-density memory device of QFP encapsulation.Parallel static memory (SRAM) is high with its integrated level, manufacturing cost is low, easy to use Many advantages, such as be widely used in electronics, these chips will do it stringent performance test when leaving the factory, but in electricity It is easy to be caused device pin rosin joint by reasons such as pin oxidation, electrical fitting technologies during dress, and work going out in bad environments The problems such as existing pin cracking.

Parallel static memory (SRAM) interface is mainly made of control line, data line and address wire, wherein data line and Number of address lines is more, and probability of malfunction is big.The measuring means such as the visual of routine, X-ray, intelligent image identification easily determine that memory draws Foot overlap joint, short circuit phenomenon, but the above-mentioned means of the breaking phenomenas such as rosin joint, cracking are difficult to judge, position, it generally must be by memory Test is written and read to judge.Data line open circuit is easy to position, and general use " full 0 ", " complete 1 " method, i.e., same address are first write " full 0 " after reading, then is written that " complete 1 " is read, and the binary number of judgement data twice, who is identical, then this bit of data line Open circuit.But the above method is not suitable for address wire judgement, and required time overhead is too big.

It is investigated that disclosed documents and materials are read, currently, Li Gang et al. is in " 51 series monolithic system design and application skill " In give the method for test macro RAM a kind of, this method is to check in two steps, and first backward entire data field send " complete respectively 0 ", " complete 1 ", then successively read and compare, if different, illustrate to malfunction.It adds up since this method is used to packet data block And verification, it is therefore desirable to a large amount of data transmitting is carried out between CPU and RAM, time overhead needed for RAM self-test is very big.It is old Soldier et al. proposes that a kind of " by-line scanning method " judges memory address line in " improved method of RAM Self-checking for Single Chip Processor " The breaking used time is shorter, and piece address wire of every detection only write for 2 times to RAM and 1 reading, that is, judges n bit address line, need to write 2n times, read n times.Although the method greatly reduces detection time, but still needs to be further increased detection efficiency.

Summary of the invention

For overcome the deficiencies in the prior art, the present invention provides a kind of parallel static memory (SRAM) address wire open circuit inspection Survey method can be improved efficiency, more quickly judge memory address line open circuit.

The technical solution adopted by the present invention to solve the technical problems is: setting parallel static memory has m root address wire, n Root data line, then address wire is expressed as A from a high position to low level_m-1~A₀, data line is expressed as D from a high position to low level_n-1~D₀；It surveys When trying m root address wire, first to decimal address 2⁰、2¹、2²、2³……2^m-2、2^m-1, 0 respectively in order write-in decimal number 0,1, 2,3……,m-2,m-1,m；Then again from address 2⁰、2¹、2²、2³……2^m-2、2^m-1, read corresponding data in 0；Respectively by phase Write-in data with address are subtracted each other with data are read, and if result is all 0, then address wire is without breaking phenomena；Otherwise, all write is found out Enter data and read the address that data subtraction value is not 0, if any k address, just has k root address wire breaking, these subtraction values are not Former write-in data decimal value i for 0 address is how many, means that A_iNumber address wire open circuit.

The beneficial effects of the present invention are: judging the open circuit conditions of m root memory address line, it can only pass through m+1 write-in Operation and m+1 read operation, so that it may quickly and position which root or which root address wire open circuit, be saved than being currently known method The time of nearly one third, the testing time is effectively shortened, is improved work efficiency.Simultaneously this method can be generalized to it is a variety of simultaneously In the address wire open circuit detection of line storage.

Specific embodiment

Below with reference to embodiment, the present invention is further described, and the invention includes, but is not limited to, the following examples.

The present invention provides a kind of test method of parallel static memory (SRAM) address wire open circuit positioning, is particularly suitable for using In printed board Denso, equipment adverse circumstances using caused chip pin rosin joint, cracking, to cause SRAM in circuit-board card logical Believe the positioning of failure.

If parallel static memory has m root address wire, n root data line, then address wire is expressed as A from a high position to low level_m-1~ A₀, data line is expressed as D from a high position to low level_n-1~D₀, this method can test address line number amount be 1~2ⁿRoot, i.e., up to 2 N times root, therefore 1≤m≤2ⁿ, behind m in document, n indicates this definition, no longer describes.

M root address wire is tested, first to decimal address 2⁰、2¹、2²、2³……2^m-2、2^m-1, 0 respectively in order write-in ten into Number 0 processed, 1,2,3 ..., m-2, m-1, m；Then again from address 20,2¹、2²、2³……2^m-2、2^m-1, read corresponding data in 0. The write-in data of identical address are subtracted each other with data are read respectively, if result is all 0, then address wire is without breaking phenomena；Otherwise, ground Location line has breaking phenomena.Finding out all write-in data and reading the address that data subtraction value is not 0 just has k if any k address Root address wire open circuit, these subtraction values are not former write-in data decimal value i (0≤i≤m) of 0 address is how many, mean that A_iNumber address wire open circuit.

In the embodiment of the present invention, by processor (model TMS320C28335) to SRAM (model CY7C1061AV33 address wire) is tested to illustrate specific implementation process of the invention.Data between the processor and SRAM Totally 16, line, it is expressed as D₇~D₀, n=8；Address wire totally 10, it is expressed as A₉~A₀, m=10.A is set₉、A₅、A₁、A₀For open circuit State.

First to decimal address 2⁰、2¹、2²、2³……2⁸、2⁹, 0 respectively in order write-in decimal number 0,1,2,3 ..., 8,9,10, then from decimal address 2⁰、2¹、2²、2³……2⁸、2⁹, 0 read data, then respectively by the write-in number of identical address Subtract each other according to reading data.Write-in data, reading data, write-in data in writing address and the difference such as following table for reading data It is shown:

Write-in data have 4 with the address that data subtraction value is not 0 is read as can be seen from the table, therefore judgement has 4 Address wire open circuit, these subtraction values are not that the former write-in data decimal value of 0 address is 0,1,5,9 respectively, therefore indicates A₀、A₁、 A₅、A₉Number address wire open circuit.

Judging result is consistent with actual result, it was demonstrated that this method can quickly and effectively orient the address wire open circuit shape of memory State.

Claims

1. a parallel static memory address line disconnection test method is characterized in that comprising the following steps:

Suppose the parallel static memory has m address lines and n data lines, then the address lines from high to low are expressed as A _m-1 ~ A ₀ , and the data lines are expressed as D _n-1 ~ D ₀ from high to low; test m When the root address line is used, first write the ^decimal ^{numbers 0, 1} ^, ² ^, ³ ..., m-2, m-1, m; then read the corresponding data from addresses 2 ⁰ , 2 ¹ , 2 ² , 2 ³ ...... 2 ^m ^-2 , 2 ^m-1 , 0; write the same address respectively Subtract the input data and the read data. If the result is all 0, the address line has no open circuit phenomenon; otherwise, find all the addresses whose subtraction value is not 0 between the write data and the read data. If there are k addresses, then There are k address lines disconnected, and the decimal value i of the original written data of these addresses whose subtraction value is not 0 indicates that the address line A _i is disconnected.