CN1674261A - Manufacturing method of flash memory - Google Patents

Abstract

A method for manufacturing flash memory includes providing substrate including multiple element isolation structures to define active region, forming tunnel dielectric layer and mask layer on substrate of active region in sequence. Then, a portion of each of the device isolation structures is removed to form a plurality of trenches. Then, a dielectric layer is formed on the substrate to cover the mask layer and the surfaces of the trenches. Then, after filling the sacrificial layer into the trenches, the sacrificial layer is used as a self-aligned mask to remove a portion of the dielectric layer. Then, the mask layer is removed to expose the tunneling dielectric layer. Then, a conductor layer is formed on the substrate. Then, part of the conductor layer is removed until the top of the sacrificial layer is exposed. Then, after removing the sacrificial layer, an inter-gate dielectric layer is formed on the substrate. Then, after forming a control gate on the inter-gate dielectric layer, a source region and a drain region are formed in the substrate at two sides of the control gate.

Description

Manufacturing method of flash memory

technical field

The present invention relates to a manufacturing method of a memory element, and in particular to a manufacturing method of a flash memory and a floating gate.

Background technique

Flash memory is a kind of electrically erasable and programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), which has the advantages of being writable, erasable, and can still save data after power failure, so it is A memory element widely used in personal computers and electronic equipment. In addition, flash memory is a non-volatile memory (Non-Volatile Memory, NVM) component, which has the advantages of small non-volatile memory, fast access speed and low power consumption, and because of its data erasure ( Erasing) adopts the "block by block" (Block by Block) erasing method, so it has the advantage of fast operation speed.

A typical flash memory device uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). Moreover, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunneling oxide (Tunneling Oxide) ( Also known as stacked gate flash memory). The flash memory device utilizes the positive or negative voltage applied on the control gate to control the injection and discharge of charges in the floating gate to achieve the storage function.

FIG. 1A to FIG. 1C are schematic cross-sectional views showing part of the manufacturing process of a conventional flash memory device.

Referring to FIG. 1A, a substrate 100 is provided, and a plurality of element isolation structures 102 have been formed in the substrate 100 to define an active region 104 of the element, and a penetrating structure has been formed on the substrate 100 of the active region 104. tunnel dielectric layer 106 .

Then, a conductive layer 108 is formed on the substrate 100 to cover the device isolation structure 102 and the tunneling dielectric layer 106 . Next, a planarization process is performed to remove part of the conductive layer 108 and make the top surface of the conductive layer 108 flat.

Next, please refer to FIG. 1B , a patterned mask layer 109 is formed on the conductive layer 108 , and the patterned mask layer 109 exposes part of the conductive layer 108 on the device isolation structure 102 . Then, using the patterned mask layer 109 as a mask, part of the conductor layer 108 is removed, and a plurality of trenches 107 are formed in the conductor layer 108 on the device isolation structure 102, and the remaining conductor layer 108 is a floating Set gate 110.

Then, referring to FIG. 1C , after removing the patterned mask layer 109 , an inter-gate dielectric layer 112 is formed on the substrate 100 to cover the floating gate 110 . Next, a control gate 114 is formed on the inter-gate dielectric layer 112 .

In the above process, the floating gate 110 is formed by a lithographic etching process. However, the lithographic etching process needs to perform dehydration baking, priming, masking, pre-baking, exposure, post-exposure baking, development, hardening, and etching in sequence. Therefore, it is not only time-consuming, but also increases a lot of process costs.

In addition, in the above process, since the conductive layer 108 is planarized by chemical mechanical polishing (CMP), there is no termination layer as a reference for polishing termination during the chemical mechanical polishing process. Therefore, the thickness of the conductor layer 108 remaining in each process is different, that is, the thickness of the floating gate 110 cannot be effectively controlled.

On the other hand, if the gate coupling ratio (Gate Couple Ratio, GCR) between the floating gate and the control gate is larger, the operating voltage required for its operation will be lower. The method for improving the gate coupling ratio includes increasing the capacitance of the inter-gate dielectric layer or reducing the capacitance of the tunnel oxide layer. Wherein, the method for increasing the capacitance of the inter-gate dielectric layer is to increase the area between the control gate layer and the floating gate. Therefore, if the size of the formed trench 107 is smaller, the area between the floating gate and the control gate will be larger, and the gate coupling ratio will be larger. However, in the process of patterning the conductive layer 108 , the size of the trench 107 is limited by the lithographic etching process for a tiny size, that is, it is impossible to form a finer trench 107 . Therefore, the area between the control gate and the floating gate cannot be further increased, thereby affecting the performance of the device.

Contents of the invention

In view of this, the object of the present invention is to provide a method for manufacturing a flash memory, which can solve the problem that the thickness of the existing floating gate is not easy to control, and can also increase the gate thickness between the floating gate and the control gate. Polar coupling rate, thereby improving device performance.

Another object of the present invention is to provide a method for manufacturing a floating gate, so as to omit the mask used for manufacturing the floating gate, that is, reduce one lithographic etching process, and thus simplify the process.

The invention proposes a method for manufacturing a flash memory. The method firstly provides a substrate on which a tunnel dielectric layer, a first conductor layer, a pad oxide layer and a patterned mask layer have been sequentially formed. Afterwards, using the patterned mask layer as a mask, part of the pad oxide layer, the first conductor layer, the tunnel dielectric layer and the substrate are removed to form a plurality of first trenches in the substrate. Then, insulating material is filled into the first trenches to form a plurality of device isolation structures. Next, a part of each element isolation structure is removed to form a plurality of second trenches, and the remaining top of each element isolation structure is interposed between the tunneling dielectric layer and the mask layer. Then, a dielectric layer is formed on the substrate to cover the mask layer and the surfaces of the second grooves. Afterwards, a sacrificial layer is filled in the second trenches, wherein the materials of the sacrificial layer and the dielectric layer have different etching selectivities. Then, using the sacrificial layer as a self-alignment mask, part of the dielectric layer is removed. Next, the mask layer is removed to expose the pad oxide layer. Then, the pad oxide layer is removed to expose the first conductive layer. Afterwards, a second conductor layer is formed on the substrate. Next, part of the second conductor layer is removed until the top of the sacrificial layer is exposed, and the second conductor layer and the first conductor layer form a floating gate, wherein part of the second conductor layer is removed until the top of the sacrificial layer is exposed. The top method can be a chemical mechanical polishing method, and the materials of the second conductive layer and the sacrificial layer have different etching selectivities. Then, the sacrificial layer is removed. Next, an inter-gate dielectric layer is formed on the substrate to cover the floating gate. Then, a control gate is formed on the inter-gate dielectric layer. Afterwards, a source region and a drain region are respectively formed in the substrate on both sides of the control gate.

Because in the process of forming the floating gate in the present invention, the second trench is formed on the element isolation structure first, and then the dielectric layer and the sacrificial layer are filled in the second trench in sequence, and by this dielectric layer and the sacrificial layer to form a floating gate. Therefore, by using the method of the present invention, the mask for making the floating gate can be omitted, that is, one lithographic etching process can be reduced, thereby saving the process cost.

In addition, since the thickness of the floating gate formed in the present invention is related to the total height of the formed dielectric layer and the sacrificial layer, the thickness of the floating gate can be determined by the total height of the formed dielectric layer and the sacrificial layer. To decide, so the thickness of the floating gate can be better controlled.

In addition, because the present invention can reduce the size of the second trench by forming a thicker dielectric layer, thereby forming a larger floating gate. Therefore, the area between the control gate and the floating gate can be increased, thereby increasing the gate coupling rate.

The present invention proposes a method for manufacturing a floating gate. In this method, a substrate is firstly provided, and the substrate includes a plurality of device isolation structures to define an active region, and the substrate of the active region is sequentially formed with tunneling dielectric layer and mask layer. Then, a part of each element isolation structure is removed to form a plurality of trenches, and the tops of the remaining element isolation structures are interposed between the tunneling dielectric layer and the mask layer. Then, a dielectric layer is formed on the substrate to cover the mask layer and the surfaces of the grooves. Afterwards, a sacrificial layer is filled in the trenches, wherein the materials of the sacrificial layer and the dielectric layer have different etching selectivities. Then, using the sacrificial layer as a self-alignment mask, part of the dielectric layer is removed. Then, the mask layer is removed to expose the tunnel dielectric layer. Next, a conductor layer is formed on the substrate. Then, remove part of the conductive layer until the top of the sacrificial layer is exposed, wherein the method of removing part of the conductive layer until the top of the sacrificial layer is exposed can be a chemical mechanical polishing method, and the materials of the conductive layer and the sacrificial layer are different. etch selectivity. Afterwards, the sacrificial layer is removed.

Due to the manufacturing method for forming the floating gate of the present invention, the trench is formed on the device isolation structure first, and then the dielectric layer and the sacrificial layer are filled in the trench sequentially, and the dielectric layer and the sacrificial layer are connected to each other. Layers are stacked to form a floating gate. Therefore, using the method of the present invention can save the mask used for making the floating gate, that is, can reduce a lithographic etching process, thereby saving the process cost.

In addition, since the thickness of the floating gate formed in the present invention is related to the total height of the formed dielectric layer and the sacrificial layer, the thickness of the floating gate can be determined by the total height of the formed dielectric layer and the sacrificial layer. To decide, so the thickness of the floating gate can be better controlled.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1C are schematic cross-sectional schematic diagrams illustrating a manufacturing process of a conventional flash memory;

2A to 2F are schematic cross-sectional views showing a manufacturing process of a flash memory according to a preferred embodiment of the present invention.

Explanation of reference signs

100, 200: Substrate

102, 214, 214a: Component isolation structure

104, 204: active area

106, 206, 206a: tunneling dielectric layer

107, 212, 215: Groove

108, 208, 208a, 220, 220a: conductor layer

109: mask layer

110, 221: floating gate

112, 222: inter-gate dielectric layer

114, 224: control grid

202: opening

209, 209a: pad oxide layer

210: mask layer

216, 216a: dielectric layer

217: Sacrificial stack layer

218: Sacrificial layer

W1, W2, W3, W4: Width

Detailed ways

FIG. 2A to FIG. 2F are schematic cross-sectional views illustrating a manufacturing process of a flash memory according to a preferred embodiment of the present invention.

First, please refer to FIG. 2A , a substrate 200 is provided, such as a silicon substrate. Then, a tunneling dielectric layer 206, a conductor layer 208, a pad oxide layer 209, and a patterned mask layer 210 are sequentially formed on the substrate 200, and the patterned mask layer 210 has an opening 202, and the opening 202 A region to be subsequently formed with an element isolation structure is exposed.

Wherein, the material of the tunneling dielectric layer 206 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation, and the formed thickness is, for example, 70 angstroms to 90 angstroms. The material of the conductive layer 208 is, for example, doped polysilicon, and its formation method is, for example, to form an undoped polysilicon layer (not shown) by chemical vapor deposition, and then perform ion implantation to form it. The formed thickness is, for example, is 500 angstroms to 1000 angstroms. In addition, the material of the pad oxide layer 209 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation, and the formed thickness is, for example, 15 angstroms to 50 angstroms. In addition, the material of the mask layer 210 includes a material having a different etching selectivity from the pad oxide layer 209, the conductive layer 208, the tunnel dielectric layer 206, and the substrate 200, such as silicon nitride, and its thickness is, for example, 1500 Angstroms to 2000 Angstroms. The method of patterning the mask layer 210 is, for example, photolithography.

Afterwards, referring to FIG. 2B , using the patterned mask layer 210 as an etching mask, part of the pad oxide layer 209 , the conductive layer 208 , and the tunneling dielectric layer 206 are removed, and a plurality of trenches are formed in the substrate 200 The trench 212 is formed, leaving the tunnel dielectric layer 206 a , the conductive layer 208 a and the pad oxide layer 209 a on the substrate 200 . Wherein, the depth of the formed trench 212 is, for example, 3000 angstroms to 4000 angstroms.

Then, an insulating material is filled in the trenches 212 to form a plurality of device isolation structures 214 and define the active region 204 . The method for forming the device isolation structure 214 is, for example, to use high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDP-CVD) to form a whole layer of insulating material (not shown), and then use chemical mechanical polishing The layer of insulating material outside the trench 212 is removed to form it.

It should be noted that in the above steps, the tunneling dielectric layer 206 is formed first, and then related steps such as forming the device isolation structure 214 are performed. Therefore, it can be avoided that due to the formation of the element isolation structure 214 first, in the subsequent thermal process to form the tunnel dielectric layer 206, a bird's beak (Bird's Beak) will be formed adjacent to the element isolation structure 214, thereby affecting the performance of the element. question.

Next, referring to FIG. 2C , part of the insulating material in each element isolation structure 214 is removed to form a plurality of trenches 215 , and the top of the remaining element isolation structure 214 a is between the tunneling dielectric layer 206 a and the mask. between the mold layers 210 . Wherein, the method of removing part of the insulating material of the device isolation structure 214 to form the plurality of trenches 215 includes an etch-back method performed by dry etching.

Next, a dielectric layer 216 is formed on the substrate 200 to cover the surface of the mask layer 210 and the trench 215 . Wherein, the material of the dielectric layer 216 includes a material having a different etch selectivity from the material of the subsequently formed conductor layer, such as silicon nitride. The dielectric layer 216 is formed by, for example, chemical vapor deposition, and the formed thickness is, for example, 200 angstroms to 1000 angstroms. In addition, in this embodiment, the materials of the dielectric layer 216 and the mask layer 210 are, for example, the same.

Afterwards, a sacrificial layer 218 is filled in the trench 215 , and the sacrificial layer 218 fills the trench 215 . Wherein, the material of the sacrificial layer 218 includes a material having a different etch selectivity from the material of the subsequently formed conductor layer, such as silicon oxide. The sacrificial layer 218 is formed by, for example, forming a whole layer of sacrificial material layer (not shown) on the substrate 200, and then removing the sacrificial material layer outside the trench 215 by chemical mechanical polishing or etching back to form Of. In addition, in another preferred embodiment, the formation method of the sacrificial layer 218 is, for example, coating a whole layer of spin-on glass (Spin-On Glass, SOG) on the substrate 200 by using a spin coating method (Spin Coating). , to form a sacrificial material layer (not shown), and then use an etch-back method to remove the sacrificial material layer outside the trench 215 to form it.

Then, referring to FIG. 2D , using the sacrificial layer 218 as a self-alignment mask, part of the dielectric layer 216 is removed. Since the materials of the sacrificial layer 218 and the dielectric layer 216 have different etching selectivities, only the dielectric layer 216a below the sacrificial layer 218 will be retained, and the rest of the dielectric layer 216 will be removed to form a dielectric layer 216a. The sacrificial stack layer 217 formed by the electrical layer 216 a and the sacrificial layer 218 . Moreover, in this embodiment, since the dielectric layer 216 and the mask layer 210 are made of the same material (for example, both are silicon nitride), the mask layer 210 is removed at the same time during the process of removing part of the dielectric layer 216. .

Next, the pad oxide layer 209a is removed to expose the conductive layer 208a. Wherein, the removal method of the pad oxide layer 209a includes a wet etching method, such as using a hydrofluoric acid solution as an etching solution. After that, the conductor layer 220 is formed on the substrate 200 . Since the conductive layer 208a has been formed under the conductive layer 220, the conductive layer 220 can be formed on it more easily. In addition, the material of the conductive layer 220 is, for example, doped polysilicon, and its formation method is, for example, forming an undoped polysilicon layer (not shown) by chemical vapor deposition, and then performing ion implantation to form it.

After that, referring to FIG. 2E , part of the conductive layer 220 is removed until the top of the sacrificial layer 218 is exposed, and the remaining conductive layer 220 a and the conductive layer 208 a form the floating gate 221 . Wherein, the method of removing part of the conductor layer 220 until the top of the sacrificial layer 218 is exposed is, for example, a chemical mechanical polishing method, and the sacrificial layer 218 having a different etching selectivity is used as the polishing stop layer during the polishing process, so the The thickness of the remaining conductive layer 220 a is related to the total height of the sacrificial stack layer 217 . Therefore, the thickness of the floating gate 221 can be better controlled.

In addition, it is worth mentioning that the thickness of the dielectric layer 216 previously formed on the sidewall of the trench 215 in FIG. The area between the control gates (not shown). Therefore, in the previous step, the width of the trench 215 can be reduced by forming a thicker dielectric layer 216 , thereby reducing the distance between two adjacent conductor layers 220 a to obtain a conductor layer 220 a with a larger size. For example, in FIG. 2C, if the original width W1 of the trenches 215 is 2000 angstroms, and the width W2 of the mask layer 210 between the two trenches 215 is 1500 angstroms, then a dielectric layer of 500 angstroms is deposited. After 216, the width W3 of the trench 215 will be reduced to 1000 angstroms, so that only a conductor layer 220a with a width of 1500 angstroms (that is, the width W2 of the mask layer) can be formed, and the width W4 shown in FIG. 2E is formed as 2500 Angstroms of conductor layer 220a. Therefore, the area between the floating gate 221 and the control gate can be increased by forming a thicker dielectric layer 216, thereby increasing the performance of the device.

Next, referring to FIG. 2F , the sacrificial layer 218 is removed. The removal method of the sacrificial layer 218 includes a wet etching method, such as using a hydrofluoric acid solution as an etching solution. It is worth mentioning that, in the above process of forming the floating gate, the trench 215 is first formed on the element isolation structure 214, and then the dielectric layer 216 and the sacrificial layer 218 are filled in the trench 215 in sequence, and The floating gate 221 is formed by the sacrificial stack structure 217 formed by the dielectric layer 216 a and the sacrificial layer 218 . Therefore, the lithographic etching process of the floating gate can be omitted by using the method of the present invention, thereby saving the process cost.

Next, an inter-gate dielectric layer 222 is formed on the substrate 200 to cover the dielectric layer 216 a and the floating gate 221 . Wherein, the material of the inter-gate dielectric layer 222 is, for example, silicon oxide/silicon nitride/silicon oxide, and its formation method is, for example, to form a silicon oxide layer by thermal oxidation, and then form a nitride layer by chemical vapor deposition. A silicon layer and another silicon oxide layer, and the thickness of the formed silicon oxide/silicon nitride/silicon oxide is, for example, 40 angstrom to 50 angstrom/45 angstrom to 70 angstrom/50 angstrom to 70 angstrom. Certainly, the material of the inter-gate dielectric layer 222 may also be silicon oxide/silicon nitride or the like.

Next, a control gate 224 is formed on the inter-gate dielectric layer 222 . Wherein, the material of the control gate 224 is, for example, doped polysilicon, and its formation method is, for example, forming a whole layer of undoped polysilicon layer (not shown) by chemical vapor deposition, and then performing ion implantation to form it. Afterwards, a source region (not shown) and a drain region (not shown) are respectively formed in the substrate 200 on both sides of the control gate 224. The formation method is, for example, performing ion implantation steps, so that the control gate 224 It is formed by injecting dopants into the substrate 200 on both sides. The subsequent process for completing the flash memory is well known to those skilled in the art, and will not be repeated here.

It is worth noting that, in addition to the above-mentioned embodiment, in another preferred embodiment of the present invention, after the step of removing the pad oxide layer 209a as shown in FIG. The formation of the conductor layer 220 and the subsequent steps shown in FIG. 2E and FIG. 2F are performed sequentially to complete the fabrication of the flash memory. In the flash memory thus formed, the floating gate 221 is only composed of the conductive layer 220a. In addition, in yet another preferred embodiment, in the step of providing the substrate 200 as shown in FIG. The floating gate 221 of the memory is also only composed of the conductor layer 220a. In addition, in another preferred embodiment, after the step of removing the sacrificial layer 218 as shown in FIG. Gate 224 and other steps to complete the fabrication of the flash memory.

In summary, the present invention has at least the following advantages:

1. In the process of forming the floating gate, the present invention first forms a trench on the element isolation structure, and then fills the trench with a dielectric layer and a sacrificial layer in sequence, and through the dielectric layer and the sacrificial layer The sacrificial stack structure formed by the sacrificial layer is used to form the floating gate. Therefore, by using the method of the present invention, the mask for making the floating gate can be omitted, that is, one lithographic etching process can be reduced, thereby saving the process cost.

2. Since the thickness of the floating gate formed in the present invention is related to the total height of the formed dielectric layer and the sacrificial layer, the thickness of the floating gate can be determined by the total height of the formed dielectric layer and the sacrificial layer To decide, so the thickness of the floating gate can be better controlled.

3. Because the present invention can reduce the size of the trench by forming a thicker dielectric layer, thereby forming a larger floating gate. Therefore, the area between the control gate and the floating gate can be increased, thereby increasing the gate coupling rate, so that the device has optimal performance.

4. In the present invention, the tunneling dielectric layer is formed first, and then related steps such as forming an element isolation structure are performed. Therefore, it is possible to avoid the problem that bird's beaks are formed adjacent to the device isolation structure during the subsequent thermal process to form the tunneling dielectric layer due to the device isolation structure being formed first, thereby affecting device performance.

Although the present invention has been disclosed above in conjunction with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention is defined by the appended claims.

Claims (20)

1. the manufacture method of a flash memory comprises:

One substrate is provided, is formed with a mask layer of a tunneling dielectric layer, one first conductor layer, a pad oxide and patterning on this substrate in regular turn;

This mask layer with patterning is a mask, removes this pad oxide of part, this first conductor layer, this tunneling dielectric layer and this substrate, to form a plurality of first grooves in this substrate;

In those first grooves, insert an insulating material, to form a plurality of component isolation structures;

Remove the part of each those component isolation structure, forming a plurality of second grooves, and the top of each those component isolation structure that is remained is between this tunneling dielectric layer and this mask layer;

On this substrate, form a dielectric layer, to cover the surface of this mask layer and those second grooves;

In those second grooves, insert a sacrifice layer;

With this sacrifice layer is an alignment mask voluntarily, removes this dielectric layer of part;

Remove this mask layer, to expose this pad oxide;

Remove this pad oxide, to expose this first conductor layer;

On this substrate, form one second conductor layer;

Remove this second conductor layer of part up to the top that exposes this sacrifice layer, and this second conductor layer and this first conductor series of strata constitute a floating grid;

Remove this sacrifice layer;

On this substrate, form a gate dielectric layer, to cover this floating grid;

On this gate dielectric layer, form a control grid; And

In this substrate of these control grid both sides, form an one source pole district and a drain region respectively.

2. the manufacture method of flash memory as claimed in claim 1, wherein this sacrifice layer has different etching selectivities with the material of this dielectric layer, and this sacrifice layer has different etching selectivities with the material of this second conductor layer.

3. the manufacture method of flash memory as claimed in claim 2, wherein the material of this sacrifice layer comprises silica.

4. the manufacture method of flash memory as claimed in claim 2, wherein the material of this dielectric layer comprises silicon nitride.

5. the manufacture method of flash memory as claimed in claim 1 wherein removes the method for this second conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.

6. the manufacture method of flash memory as claimed in claim 1, wherein this dielectric layer is identical with the material of this mask layer, and in the process that removes this dielectric layer of part, removes this mask layer simultaneously.

7. the manufacture method of flash memory as claimed in claim 1, wherein after removing this sacrifice layer with form before this gate dielectric layer, also comprise removing this dielectric layer.

8. the manufacture method of flash memory as claimed in claim 1, wherein the formation method of those second grooves comprises the etch-back method of utilizing dry ecthing to carry out.

9. the manufacture method of flash memory as claimed in claim 1, wherein after removing this pad oxide with form before this second conductor layer, also comprise removing this first conductor layer, and formed this floating grid is made of this second conductor layer.

10. the manufacture method of a floating grid comprises:

One substrate is provided, and this substrate includes a plurality of component isolation structures defining an active area, and is formed with a tunneling dielectric layer and a mask layer in regular turn on this substrate of this active area;

Remove the part of each those component isolation structure, forming a plurality of grooves, and the top of each those component isolation structure that is remained is between this tunneling dielectric layer and this mask layer;

On this substrate, form a dielectric layer, to cover the surface of this mask layer and those grooves;

In those grooves, insert a sacrifice layer;

With this sacrifice layer is an alignment mask voluntarily, removes this dielectric layer of part;

Remove this mask layer, to expose this tunneling dielectric layer;

On this substrate, form one first conductor layer;

Remove this first conductor layer of part up to the top that exposes this sacrifice layer; And

Remove this sacrifice layer.

11. the manufacture method of floating grid as claimed in claim 10, wherein this sacrifice layer has different etching selectivities with the material of this dielectric layer, and this sacrifice layer has different etching selectivities with the material of this first conductor layer.

12. the manufacture method of floating grid as claimed in claim 11, wherein the material of this sacrifice layer comprises silica.

13. the manufacture method of floating grid as claimed in claim 11, wherein the material of this dielectric layer comprises silicon nitride.

14. the manufacture method of floating grid as claimed in claim 10 wherein removes the method for this first conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.

15. the manufacture method of floating grid as claimed in claim 10, wherein this dielectric layer is identical with the material of this mask layer, and in the process that removes this dielectric layer of part, removes this mask layer simultaneously.

16. the manufacture method of floating grid as claimed in claim 15, wherein the material of this dielectric layer and this mask layer comprises silicon nitride.

17. the manufacture method of floating grid as claimed in claim 10, wherein the formation method of those grooves comprises the etch-back method of utilizing dry ecthing to carry out.

18. the manufacture method of floating grid as claimed in claim 10 wherein after removing this sacrifice layer, also comprises removing this dielectric layer.

19. the manufacture method of floating grid as claimed in claim 10, wherein also comprise between this tunneling dielectric layer of this substrate that is provided and this mask layer and be formed with one second conductor layer and a pad oxide in regular turn, and after removing this mask layer with form before this first conductor layer, also comprise removing this pad oxide, to expose this second conductor layer.

20. the manufacture method of floating grid as claimed in claim 19, wherein after removing this pad oxide with form before this first conductor layer, also comprise removing this second conductor layer.

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