CN1674260A - Manufacturing method of flash memory - Google Patents

Abstract

The invention discloses a manufacturing method of a flash memory, which comprises the following steps: a substrate is provided, and the substrate includes a plurality of device isolation structures to define an active region, and a tunneling dielectric layer and a mask layer are sequentially formed on the substrate of the active region. Then, a sacrificial layer is formed on the substrate. Then, the sacrificial layer is processed by photolithography to retain the sacrificial layer on the device isolation structures. Then, after removing the mask layer, a conductor layer is formed on the substrate. Then, part of the conductor layer is removed until the top of the sacrificial layer is exposed. And finally, after removing the sacrificial layer, forming an inter-gate dielectric layer on the substrate. Then, after forming a control gate on the inter-gate dielectric layer, a source region and a drain region are formed in the substrate at two sides of the control gate.

Description

Manufacturing method of flash memory

technical field

The invention relates to a manufacturing method of a memory element, and in particular to a manufacturing method of a flash memory and a floating gate.

Background technique

Flash memory is a kind of electrically erasable and programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), which has the advantages of being writable, erasable, and can still save data after power failure, so it is A memory element widely used in personal computers and electronic equipment. In addition, flash memory is a non-volatile memory (Non-Volatile Memory, NVM) device, which has the advantages of small size, fast access speed and low power consumption of non-volatile memory, and because of its data erasure ( Erasing) adopts the "block by block" (Block by Block) erasing method, so it has the advantage of fast operation speed.

Typical flash memory devices use doped polysilicon to make floating gates (Floating Gate) and control gates (Control Gate). Moreover, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunneling oxide (Tunneling Oxide) ( Also known as stacked gate flash memory). The flash memory device utilizes the positive or negative voltage applied on the control gate to control the injection and discharge of charges in the floating gate to achieve the storage function.

FIG. 1A to FIG. 1B are schematic cross-sectional views showing part of the manufacturing process of a conventional flash memory device.

Referring to FIG. 1A, a substrate 100 is provided, and a plurality of element isolation structures 102 have been formed in the substrate 100 to define an active region 104 of the element, and a penetrating structure has been formed on the substrate 100 of the active region 104. tunnel dielectric layer 106 .

Then, a conductive layer 108 is formed on the substrate 100 to cover the device isolation structure 102 and the tunneling dielectric layer 106 . Next, a planarization process is performed to remove part of the conductive layer 108 and make the top surface of the conductive layer 108 flat.

After that, referring to FIG. 1B , the conductive layer 108 is patterned to form a plurality of trenches 107 exposing part of the device isolation structure 102 , and the remaining conductive layer 108 is used as a floating gate 110 . Then, an inter-gate dielectric layer 112 is formed on the substrate 100 to cover the floating gate 110 . Next, a control gate 114 is formed on the inter-gate dielectric layer 112 .

In the above process, since the conductive layer 108 is planarized by chemical mechanical polishing (CMP), there is no termination layer as a reference for polishing termination during the chemical mechanical polishing process. Therefore, the thickness of the conductor layer 108 remaining in each process is different, that is, the thickness of the floating gate 110 cannot be effectively controlled.

On the other hand, if the gate coupling ratio (Gate Couple Ratio, GCR) between the floating gate and the control gate is larger, the operating voltage required for its operation will be lower. The method for improving the gate coupling ratio includes increasing the capacitance of the inter-gate dielectric layer or reducing the capacitance of the tunnel oxide layer. Wherein, the method for increasing the capacitance of the inter-gate dielectric layer is to increase the area between the control gate layer and the floating gate. Therefore, if the size of the formed trench 107 is smaller, the area between the floating gate and the control gate will be larger, and the gate coupling ratio will be larger. However, in the process of patterning the conductor layer 108 , the size of the trench 107 is limited by the lithographic etching process for a tiny size, that is, it is impossible to form a finer trench 107 . Therefore, the area between the control gate and the floating gate cannot be further increased, thereby affecting the performance of the device.

Contents of the invention

In view of this, the purpose of the present invention is to provide a method for manufacturing a flash memory, so as to increase the gate coupling ratio between the floating gate and the control gate, thereby improving device performance.

Another object of the present invention is to provide a method for manufacturing a floating gate to solve the problem that the thickness of the existing floating gate is difficult to control.

The invention proposes a method for manufacturing a flash memory. In the method, a substrate is provided first, and a tunnel dielectric layer and a patterned mask layer have been sequentially formed on the substrate. Afterwards, using the mask layer as an etching mask, the tunnel dielectric layer and the substrate are patterned to form a plurality of trenches in the substrate. Then, insulating material is filled into these trenches to form a plurality of element isolation structures. Next, a sacrificial material layer is formed on the substrate to cover the mask layer and the device isolation structure. After that, the sacrificial material layer is patterned to form a sacrificial layer on the device isolation structure. Then, the mask layer is removed to expose the tunnel dielectric layer. Then, a conductor layer is formed on the substrate. Next, remove part of the conductive layer until the top of the sacrificial layer is exposed to form a floating gate, wherein the method of removing part of the body layer until the top of the sacrificial layer is exposed can be a chemical mechanical polishing method, and the conductive layer The material and the material of the sacrificial layer have different etching selectivities. Next, the sacrificial layer is removed. After that, an inter-gate dielectric layer is formed on the substrate to cover the floating gate. Then, a control gate is formed on the inter-gate dielectric layer. Then, a source region and a drain region are respectively formed in the substrate on both sides of the control gate.

Because the thickness of the floating gate of the formed flash memory of the present invention is related to the thickness of the sacrificial material layer, the thickness of the floating gate can be determined by the thickness of the formed sacrificial material layer, so the floating gate The thickness can be better controlled.

In addition, since the present invention can increase the area between the control gate and the floating gate by forming a micro-sized sacrificial layer, the gate coupling rate can be improved, thereby improving device performance.

The present invention proposes a method for manufacturing a floating gate. In this method, a substrate is provided first, and the substrate includes a plurality of element isolation structures to define an active region, and the active region is sequentially formed on the substrate. A tunnel dielectric layer and a mask layer are formed. Then, a sacrificial layer is formed on the substrate. Then, a lithographic etching process is performed on the sacrificial layer to retain the sacrificial layer on the device isolation structures. Afterwards, the mask layer is removed to expose the tunnel dielectric layer. Then, a conductor layer is formed on the substrate. Next, a portion of the conductor layer is removed until the top of the sacrificial layer is exposed. The method for removing part of the conductive layer until exposing the top of the sacrificial layer is, for example, chemical mechanical polishing, and the material of the conductive layer and the material of the sacrificial layer have different etching selectivities. Then, the sacrificial layer is removed.

Because the thickness of the floating gate formed in the present invention is related to the thickness of the sacrificial layer, the thickness of the floating gate can be determined by the thickness of the formed sacrificial layer, so the thickness of the floating gate can be better obtained. control.

In order to make the above and other objects, features, and advantages of the present invention more comprehensible, preferred embodiments are described below in detail with accompanying drawings.

Description of drawings

FIG. 1A to FIG. 1B are schematic cross-sectional views showing a manufacturing process of a conventional flash memory;

FIG. 2A to FIG. 2E are schematic cross-sectional views illustrating a manufacturing process of a flash memory according to a preferred embodiment of the present invention.

Explanation of reference signs

100, 200 Substrate 102, 214 Component isolation structure

104, 204 active region 106, 206, 206a tunnel dielectric layer

107, 212 Groove

108, 208, 208a, 218, 218a conductor layer

110, 220 floating gate 112, 222 inter-gate dielectric layer

114, 224 control grid 202 opening

210 mask layer 216 sacrificial material layer

216a sacrificial layer

Detailed ways

FIG. 2A to FIG. 2E are schematic cross-sectional views illustrating a manufacturing process of a flash memory according to a preferred embodiment of the present invention.

First, please refer to FIG. 2A , a substrate 200 is provided, such as a silicon substrate. Then, a tunnel dielectric layer 206 , a conductive layer 208 and a patterned mask layer 210 are sequentially formed on the substrate 200 . The patterned mask layer 210 has an opening 202 , and the opening 202 exposes a region where a device isolation structure is to be formed later.

Wherein, the material of the tunneling dielectric layer 206 is, for example, silicon oxide, and its formation method is, for example, thermal oxidation, and the formed thickness is, for example, 70 angstroms to 90 angstroms. In addition, the material of the conductive layer 208 is, for example, doped polysilicon, and its formation method is, for example, to form an undoped polysilicon layer (not shown) by chemical vapor deposition, and then perform ion implantation to form it. The thickness is, for example, 500 angstroms to 1000 angstroms. In addition, the material of the mask layer 210 includes a material having a different etching selectivity from the conductor layer 208 , the tunneling dielectric layer 206 and the substrate 200 , such as silicon nitride, and its thickness is, for example, 1000 angstroms to 1500 angstroms. The method of patterning the mask layer 210 is, for example, photolithography.

Afterwards, referring to FIG. 2B , using the patterned mask layer 210 as an etching mask, part of the conductive layer 208 and the tunneling dielectric layer 206 are removed, and a plurality of trenches 212 are formed in the substrate 200, and the substrate The tunnel dielectric layer 206a and the conductive layer 208a are left on the bottom 200 . Wherein, the depth of the formed trench 212 is, for example, 3000 angstroms to 4000 angstroms.

Then, an insulating material is filled in the trenches 212 to form a plurality of device isolation structures 214 and define an active region 204. The method for forming the device isolation structure 214 is, for example, to use high density plasma chemical vapor deposition (High Density Plasma Chemical Vapor Deposition, HDP-CVD) to form a whole layer of insulating material (not shown), and then use chemical mechanical polishing The layer of insulating material outside the trench 212 is removed to form it.

It should be noted that in the above steps, the tunneling dielectric layer 206 is formed first, and then the related steps of forming the element isolation structure 214 are performed. Therefore, it can be avoided that due to the formation of the element isolation structure 214 first, in the subsequent thermal process to form the tunnel dielectric layer 206, a bird's beak (Bird's Beak) will be formed adjacent to the element isolation structure 214, thereby affecting the performance of the element. question.

Next, a sacrificial material layer 216 is formed on the substrate 200 to cover the mask layer 210 and the device isolation structure 214 . Wherein, the material of the sacrificial material layer 216 includes a material having a different etching selectivity from the material of the subsequently formed conductor layer, such as silicon nitride. The formation method of the sacrificial material layer 216 is, for example, chemical vapor deposition, and the formed thickness is, for example, 1000 angstroms to 2000 angstroms.

After that, referring to FIG. 2C , the sacrificial material layer 216 is patterned to form a sacrificial layer 216 a on the device isolation structure 214 . In this embodiment, since the sacrificial material layer 216 and the mask layer 210 are made of the same material (for example, both are silicon nitride), the mask layer 210 is also removed during the process of patterning the sacrificial material layer 216 . The conductive layer 208 a can be retained because it has a different etching selectivity from the sacrificial material layer 216 and the mask layer 210 .

Then, a conductive layer 218 is formed on the substrate 200 . Since the conductive layer 208 a has been previously formed under the conductive layer 218 , the conductive layer 218 can be formed thereon more easily. In addition, the material of the conductive layer 218 is, for example, doped polysilicon, and its formation method is, for example, forming an undoped polysilicon layer (not shown) by chemical vapor deposition, and then performing an ion implantation step to form it.

Afterwards, referring to FIG. 2D , part of the conductive layer 218 is removed until the top of the sacrificial layer 216 a is exposed, and the remaining conductive layer 218 a and the conductive layer 208 a form the floating gate 220 . Wherein, the method of removing part of the conductor layer 218 until the top of the sacrificial layer 216a is exposed is, for example, a chemical mechanical polishing method, and the sacrificial layer 216a having a different etching selectivity is used as the polishing stop layer during the polishing process, so the The thickness of the remaining conductive layer 218a will be the same as that of the sacrificial layer 216a. Thus, the thickness of the floating gate 220 can be better controlled. In other words, in each process, the thickness of the conductive layer 218a can be kept consistent by forming the sacrificial layer 216a with the same thickness, so that the thickness of the floating gate 220 can be kept consistent.

In addition, in the previous process of forming the sacrificial layer 216a, since the sacrificial layer 216a with a smaller size can be formed, the size of the conductor layer 218a can be increased, thereby increasing the area between the floating gate 220 and the control gate. , which increases the gate coupling ratio.

Next, referring to FIG. 2E , the sacrificial layer 216 a is removed. The removal method of the sacrificial layer 216 a includes a wet etching method, for example, using a phosphoric acid solution as an etching solution. Next, an inter-gate dielectric layer 222 is formed on the substrate 200 to cover the floating gate 220 . Wherein, the material of the inter-gate dielectric layer 222 is, for example, silicon oxide/silicon nitride/silicon oxide, and its formation method is, for example, to form a silicon oxide layer by thermal oxidation, and then form a nitride layer by chemical vapor deposition. A silicon layer and another silicon oxide layer, and the thickness of the formed silicon oxide/silicon nitride/silicon oxide is, for example, 40 angstrom to 50 angstrom/45 angstrom to 70 angstrom/50 angstrom to 70 angstrom. Certainly, the material of the inter-gate dielectric layer 222 may also be silicon oxide/silicon nitride or the like.

Next, a control gate 224 is formed on the inter-gate dielectric layer 222 . Wherein, the material of the control gate 224 is, for example, doped polysilicon, and its formation method is, for example, forming a whole layer of undoped polysilicon layer (not shown) by chemical vapor deposition, and then performing ion implantation to form it. Afterwards, a source region (not shown) and a drain region (not shown) are respectively formed in the substrate 200 on both sides of the control gate 224. The formation method is, for example, performing ion implantation steps, so that the control gate 224 It is formed by injecting dopants into the substrate 200 on both sides. The subsequent process for completing the flash memory is well known to those skilled in the art, and will not be repeated here.

It is worth noting that, in addition to the above-mentioned embodiment, in another preferred embodiment of the present invention, after the step of removing the mask layer 210 as shown in FIG. The formation of the conductor layer 218 and subsequent steps shown in FIG. 2D to FIG. 2E are performed sequentially to complete the fabrication of the flash memory. In the flash memory thus formed, the floating gate 220 is only composed of the conductive layer 218a. In addition, in yet another preferred embodiment, in the step of providing the substrate 200 as shown in FIG. The floating gate 220 of the memory is also only composed of the conductive layer 218a.

In summary, the present invention has at least the following advantages:

1. Since the thickness of the floating gate of the formed flash memory of the present invention is related to the thickness of the sacrificial material layer, the thickness of the floating gate can be determined by the thickness of the formed sacrificial material layer, so the floating The thickness of the gate can be better controlled.

2. Since the present invention can increase the area between the control gate and the floating gate by forming a micro-sized sacrificial layer, the gate coupling rate can be improved, thereby improving device performance.

3. In the present invention, the tunneling dielectric layer is formed first, and then the related steps of forming the element isolation structure are performed. Therefore, it is possible to avoid the problem that bird's beaks are formed adjacent to the device isolation structure during the subsequent thermal process to form the tunneling dielectric layer due to the device isolation structure being formed first, thereby affecting device performance.

Although the present invention has been disclosed above in conjunction with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore The scope of protection of the present invention is defined by the appended claims.

Claims (20)

1. the manufacture method of a flash memory comprises:

One substrate is provided, and is formed with a mask layer of a tunneling dielectric layer and patterning on this substrate in regular turn;

With this mask layer is an etching mask, and this tunneling dielectric layer of composition and this substrate are to form a plurality of grooves in this substrate;

In those grooves, insert an insulating material, to form a plurality of component isolation structures;

On this substrate, form a sacrificial material layer, to cover this mask layer and those component isolation structures;

This sacrificial material layer of composition is to form a sacrifice layer on those component isolation structures;

Remove this mask layer, to expose this tunneling dielectric layer;

On this substrate, form one first conductor layer;

Remove this first conductor layer of part up to the top that exposes this sacrifice layer, to form a floating grid;

Remove this sacrifice layer;

On this substrate, form a gate dielectric layer, to cover this floating grid;

On this gate dielectric layer, form a control grid; And

In this substrate of these control grid both sides, form an one source pole district and a drain region respectively.

2. the manufacture method of flash memory as claimed in claim 1, wherein the material of this sacrificial material layer has different etching selectivities with the material of this first conductor layer.

3. the manufacture method of flash memory as claimed in claim 2, wherein the material of this sacrificial material layer comprises silicon nitride.

4. the manufacture method of flash memory as claimed in claim 1 wherein removes the method for this first conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.

5. the manufacture method of flash memory as claimed in claim 1, wherein this sacrificial material layer is identical with the material of this mask layer, and in the process of this sacrificial material layer of composition, removes this mask layer simultaneously.

6. the manufacture method of flash memory as claimed in claim 5, wherein the material of this sacrificial material layer and this mask layer comprises silicon nitride.

7. the manufacture method of flash memory as claimed in claim 1, wherein the material of this first conductor layer comprises doped polycrystalline silicon.

8. the manufacture method of flash memory as claimed in claim 1 wherein also comprises between this tunneling dielectric layer of this substrate that is provided and this mask layer being formed with one second conductor layer, and expose this second conductor layer after removing this mask layer.

9. the manufacture method of flash memory as claimed in claim 8, wherein after removing this mask layer with form before this first conductor layer, also comprise removing this second conductor layer.

10. the manufacture method of flash memory as claimed in claim 8, wherein the material of this second conductor layer comprises doped polycrystalline silicon.

11. the manufacture method of a floating grid comprises:

One substrate is provided, includes a plurality of component isolation structures in this substrate defining an active area, and be formed with a tunneling dielectric layer and a mask layer in regular turn on this substrate of this active area;

On this substrate, form a sacrifice layer;

This sacrifice layer is carried out a lithography technology, be positioned at this sacrifice layer on those component isolation structures with reservation;

Remove this mask layer, to expose this tunneling dielectric layer;

On this substrate, form one first conductor layer;

Remove this first conductor layer of part up to the top that exposes this sacrifice layer; And

Remove this sacrifice layer.

12. the manufacture method of floating grid as claimed in claim 11, wherein the material of this sacrifice layer has different etching selectivities with the material of this first conductor layer.

13. the manufacture method of floating grid as claimed in claim 12, wherein the material of this sacrifice layer comprises silicon nitride.

14. the manufacture method of floating grid as claimed in claim 11 wherein removes the method for this first conductor layer of part up to the top that exposes this sacrifice layer and comprises chemical mechanical milling method.

15. the manufacture method of floating grid as claimed in claim 11, wherein this sacrifice layer is identical with the material of this mask layer, and in the process that forms this sacrifice layer, removes this mask layer simultaneously.

16. the manufacture method of floating grid as claimed in claim 15, wherein the material of this sacrifice layer and this mask layer comprises silicon nitride.

17. the manufacture method of floating grid as claimed in claim 11, wherein the material of this first conductor layer comprises doped polycrystalline silicon.

18. the manufacture method of floating grid as claimed in claim 11 wherein also comprises between this tunneling dielectric layer of this substrate that is provided and this mask layer being formed with one second conductor layer, and expose this second conductor layer after removing this mask layer.

19. the manufacture method of floating grid as claimed in claim 18, wherein after removing this mask layer with form before this first conductor layer, also comprise removing this second conductor layer.

20. the manufacture method of floating grid as claimed in claim 18, wherein the material of this second conductor layer comprises doped polycrystalline silicon.

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