CN1643525A - System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase - Google Patents

Abstract

Systems and methods for placement of dummy metal fills while preventing disturbance of device matching and optionally limiting capacitance increase are disclosed. A computer-automated method for locating dummy fills in an integrated circuit fabrication process generally comprises receiving an input layout of the integrated circuit and specification of device matching for the integrated circuit and locating the dummy fills in the integrated circuit according to dummy rules while preserving device matching. Locating the dummy fills may include locating the dummy fills along the at least one axis of symmetry where device matching is along an axis of symmetry and locating the dummy fills so as to preserve matching of the repeated elements where device matching is repeated matched elements. The method may also include designating at least one net of the integrated circuit as a critical net, the critical nets being only a subset of all nets of the integrated circuit, identifying metal conductors corresponding to each designated critical net from the layout file, and delineating a net blocking exclusion zone extending a distance of a minimum net blocking distance (NBD) from the metal conductor for each metal conductor identified, wherein the step of locating locates the dummy fills outside of the net blocking exclusion zone.

Description

System and method for placing dummy metal fill while ensuring device matching and/or limiting capacitance increase

Related Application Cross Reference

The present invention is filed on March 12, 2002 entitled "System And Method For Limiting Increase In Capacitance Due To Dummy Metal fills And For Limiting Increase In Capacitance Due To Dummy Metal fills Unitized For Improving Planar Profile Uniformity), a continuation-in-part of U.S. Patent Application No. 10/097,978, pending, which is hereby incorporated by reference in its entirety.

technical field

The present invention relates generally to semiconductor processing. More specifically, the present invention discloses systems and methods for placing analog metal fills while preventing disturbances to device matching, and selectively limiting the increase in capacitance.

Background technique

Generally speaking, the fabrication of integrated circuits involves a series of layering processes in which metals, dielectrics, and other materials are applied to the surface of a semiconductor wafer to form layered interconnect structures. Integrated circuits fabricated from semiconductor wafers typically include interlayer circuitry that includes a plurality of metal lines passing through a plurality of layers connected by metal-filled vias. Therefore, a critical step in the manufacturing process is the formation of interconnect structures, which connect the various layers of integrated circuit devices, resulting in high complexity and circuit density of integrated circuit devices.

Especially in the manufacturing process of sub-0.35μm semiconductor devices, in order to avoid reducing the yield in the process of the subsequent layering steps, before the subsequent layering steps, it is necessary to make each layer of the integrated circuit have better flatness very important. The planarized surface usually needs to maintain a necessary focal lithography depth level for subsequent steps to ensure that the metal interconnect structure does not deform throughout the forming steps.

For example, damascene methods are often applied to metallize the interconnect structures between layers. The damascene method involves etching a pattern of vias or trenches within a planar dielectric layer until the active area of the device is reached. To fill the etched vias or trenches, excess metal is typically deposited across the surface of the semiconductor wafer. The excess of the metal layer is then ground and removed from the patterned surface, leaving thin metal lines as interconnects. As with other steps in the fabrication process, it is also important that the ground interconnect structure damascene layer is flat.

In order to achieve the planarity necessary to fabricate ultra-high density integrated circuits, a chemical-mechanical polishing or polishing (CMP) process is used to planarize the topography of films or layers on a substrate. In general, the CMP process is a grinding process that involves removing material from the semiconductor wafer by rotating the polishing pad and wafer relative to each other by applying controlled pressure in the presence of chemical refining. Selectively removed. Using CMP, both on oxides and metals can be used to produce excellent local planarity. After the CMP process, the polished surface is ready for subsequent process steps, such as adding more layers.

However, the planar profile produced by the CMP process usually depends on the pattern density of the underlying layer, and thus can vary by more than 30%-40%. For example, Ouma et al. published in "Proc. of Interconnect Technology Conference Proceedings (Proc. of Interconnect Technology Conference)" February 1998, on pages 67-69 "Integrated features and modeling methods for CMP dielectric planarization (An Integrated Characterization AndModeling Methodology for CMP Dielectric Planarization)" is discussed in the article, which is hereby incorporated by reference in its entirety.

One approach to reduce the variation in the topography of the CMP plane due to pattern dependence uses dummy metal fill. In particular, before the CMP process, dummy metal fillings or features are placed on the wafer to make the pattern density of the IC chip more uniform, that is, to make the intrinsic density of the entire layout become average. Uniform intrinsic density improves wafer processing uniformity during certain operations such as CMP. Thus, dummy metal fills can help reduce profile variations after CMP due to pattern dependence.

The dummy fillings are usually laid out according to traditional dummy filling rules, and dummy objects with uniform density are set to available positions (that is, rule-based virtual filling). For example, see "Analyzing the Effects of Floating Dummy-Fills: Form Feature Scale Analysis to Full- Chip RC Extraction), the entirety of which is hereby incorporated by reference. However, such rule-based virtual filling has such a problem that the allowed range of virtual filling density is relatively large, so that each design usually needs to be determined through a large number of experiments.

Model-based virtual filling can also be used to reduce the variation of the CMP plane profile due to pattern dependence. Since the CMP planar profile is generally proportional to the effective pattern density produced by the averaging effect caused by the rotation of the polishing pad, the model-based dummy filling achieves an effective density within a predetermined range by selectively inserting dummy fillers, which can reduce the Small and large plane shape changes. For example, see "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems" published in July 2001 by Tian et al., Volume 20, Issue 7 pp.902-910 Published "Model-Based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability," the entirety of which is hereby incorporated by reference.

However, the embedded dummy metal fills have a detrimental effect on the electric field and increase the capacitance of the initial metal line. In some long critical nets, the increase in net capacitance can exceed 25%. Some nets span the entire chip and have an impact on the critical performance of the chip. Common critical nets are global control signals such as clocks. In general, the total delay of long interconnects is dominated by the interconnect RC delay such that the total net delay is proportional to the increase in net capacitance. Therefore, a 25% increase in net delay is sufficient to cause malfunction of the circuit function.

As mentioned in the Tian et al. article mentioned above, the capacitance decreases rapidly as the distance between the dummy metal and the original metal line increases. To reduce the capacitance increase, Tian proposes a model-based dummy metal filling method that maximizes the distance between the initial metal line and the dummy metal within the available area constraints within the device. The method proposed by Tian tries to reduce the capacitance increase of all nets. However, it is difficult to reduce the capacitance increase of all nets, and the method proposed by Tian cannot guarantee to reduce the capacitance increase of long timing critical nets within a specified range.

Inserted dummy metal fills can also adversely affect other features of the original circuit or device design. Therefore, there is a need for systems and methods for improving planar profile uniformity after CMP while maintaining or maintaining circuit or device characteristics.

Contents of the invention

Systems and methods are disclosed for placing dummy metal fills while preventing disturbances to device matching, and selectively limiting capacitance increases. The systems and methods take into account the effects of dummy fill metal that is transferred to structures printed on the wafer, thereby limiting disturbances to device matching and optionally limiting capacitance increases. It should be appreciated that the present invention can be implemented in a variety of ways, including as a process, apparatus, system, device, method, or computer-readable medium such as a computer-readable storage medium or a computer network in which instructions are transmitted optically or electronically communication line to send. A number of inventive embodiments of the present invention are described below.

A computer-automated method for locating dummy fillers during the manufacture of integrated circuits, generally comprising: receiving as input the layout of the integrated circuit and specifications for matching of integrated circuit devices, and positioning the dummy fillers to the integrated circuit according to virtual rules circuit while ensuring device matching. For example, an integrated circuit may have device matching by having at least one axis of symmetry along which the integrated circuit has device matching symmetry. In another example, an integrated circuit is device matched by having repeat matched devices, where the repeat may be in rows, columns, or arrays. Accordingly, positioning the dummy filling may include positioning the dummy filling along at least one axis of symmetry along which device matching is achieved, and then positioning the dummy filling to ensure repeat device matching, wherein the device matching is Duplicate matched devices.

In order to also limit capacitance increases caused by dummy fills, the method optionally includes designating at least one integrated circuit net as a critical net, the critical net being only a subset of all integrated circuit nets, Determine the metal conductors corresponding to each specified critical net from the layout file, and determine the net blocking exclusion zone (net blocking exclusion zone) for each determined metal conductor, extending the minimum net blocking distance (net blocking exclusion zone) from the metal conductor blocking distance, NBD) form the line network to block the restricted area. The step of locating the dummy fill may include locating the dummy fill outside of the wire mesh blocking exclusion zone.

The critical line network may be received as input from a user or from a CAD tool output. The method may include setting a minimum NBD. Alternatively, the method may include: setting a maximum allowable capacitance increment, preferably an increment that ensures functionality of the circuit; and determining a minimum NBD to limit the maximum capacitance increment to the maximum allowable capacitance increment. The minimum NBD can be determined using capacitance simulation software such as PASCAL( ^TM) and/or RAPHAEL ^(TM) , preferably by calculating only the critical nets specified.

Typically, metal conductors corresponding to at least one specified critical net are determined using methods such as net tracing, where the layout file is in GDS-II format, and/or notation, where the layout file contains the net connection information. Typically, the layout file containing the wireline connection information is in annotated GDS-II format or LEF/DEF (Library Exchange Format/Design Exchange Format). In general, a net blocking exclusion zone includes at least one blocking area within a designated signal net layer containing a corresponding metal conductor and any other layer within a minimum NBD distance from the corresponding metal conductor . Additionally, positioning of dummy fills may include the use of model-based and/or rule-based dummy fill processes.

The present invention provides a system for locating dummy fillings in the manufacturing process of integrated circuits, comprising: an input terminal for receiving data including the layout of integrated circuits and matching specifications of integrated circuit devices; and a dummy filling locator , which locates the dummy filler according to the dummy rules, while ensuring the matching of devices.

To also limit capacitance increases due to dummy fills, the input can also receive: data specifying only a subset of all integrated circuit nets as designating critical nets; a metal conductor determination processor specifying the metal conductors of the critical net; and an exclusion zone processor for determining, for each identified metal conductor, a net blocking exclusion zone extending a minimum NBD distance from the metal conductor. The dummy fill locator locates dummy fills outside the net-blocking restricted area according to the virtual rules provided by the user, while ensuring the matching of devices, such as ensuring the symmetry of the devices along the symmetry axis, and ensuring the matched devices.

A computerized automated method for locating dummy fills during the manufacture of integrated circuits, generally comprising: reading a layout file specifying the layout of an integrated circuit; designating at least one integrated circuit net as a critical net, the critical net For only a subset of all integrated circuit nets; from the layout file, determine the metal conductors corresponding to each specified critical net; extending the minimum net blocking distance (NBD); and locating the dummy fill outside the net blocking exclusion zone.

A system for locating dummy fills during the manufacture of integrated circuits, generally comprising: an input terminal for receiving a file including a circuit layout and designating only a subset of all integrated circuit nets as designated critical lines The data of the net; the metal conductor determination processor is used to determine the metal conductor corresponding to each designated critical net from the layout file; the forbidden area processor is used to determine the net blocking forbidden area for each determined metal conductor, which is from a metal conductor extending a minimum NBD distance; and a dummy fill locator that positions a dummy fill outside of a net blocking exclusion zone according to user-supplied virtual rules.

These and other features and advantages of the present invention will be set forth in more detail in the following detailed description and accompanying drawings illustrating by way of example the principles of the invention.

Description of drawings

The invention will be better understood from the following detailed description when taken in conjunction with the accompanying drawings, in which like reference numerals indicate like resulting elements, in which:

1 is a partial cross-sectional view of an example circuit having multiple metal layers;

FIG. 2 is a partial top view of a metal layer of the circuit in FIG. 1, wherein the circuit includes designated signal nets;

FIG. 3 is a partial top view of a metal layer of the circuit in FIG. 1, above and below the metal layer including designated signal nets;

4 is a partial cross-sectional view of another example circuit having multiple metal layers, wherein the circuit is device matched by providing device symmetry along an axis of symmetry;

5 is a partial top view of a metal layer of the circuit in FIG. 4, wherein the circuit includes a designated signal net;

Figure 6 shows yet another example circuit with device matching by providing duplicate matched devices;

FIG. 7 is a flowchart of an automated computer program that determines the placement of dummy metal fills to help ensure device matching and/or limit capacitance increases caused by dummy metal fills;

FIG. 8 is a block diagram of a system that may be used to implement the process of FIG. 7 to locate dummy fills during integrated circuit fabrication;

Figure 9 shows an example of a computer system that can be applied according to the methods and processes of the embodiments described herein; and

FIG. 10 shows a system block diagram of the computer system in FIG. 9 .

Detailed ways

Systems and methods for placing dummy metal fills while preventing disturbances to device matching and selectively limiting capacitance increases are disclosed. The following description will enable any person skilled in the art to make and use the present invention. Descriptions of specific embodiments and applications are given by way of example only, and various modifications will be readily apparent to those skilled in the art. The general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Accordingly, the present invention is intended to have the broadest scope covering alternatives, modifications and equivalents consistent with the principles and features disclosed herein. For the purpose of clarity of explanation, descriptions related to technical material that is known in the technical fields related to the invention have not been described in detail so that the present invention is not unnecessarily obscured.

1 is a partial cross-sectional view of an integrated circuit (IC) chip 100 having a plurality of metal layers 102 and 106-112. As can be appreciated, layer 112 is typically a substrate. FIG. 2 is a partial top view of a designated signal net layer 102 that includes a designated signal net 104 . FIG. 3 is a partial top view of the metal layers 106 , 108 located above and below the designated signal net layer 102 containing the designated signal net 104 .

A designated critical signal net 104 represented by a fixed-bias original metal is located in the designated signal net layer 102 . The upper metal layer 106 and the lower metal layer 108 are layers above and below the designated signal mesh layer 102, respectively. In addition, the base layers 110, 112 are the upper base and the lower base, respectively. A floating dummy metal fill 114 is located in the designated signal net layer 102 , as well as in the upper metal layer 106 and the lower metal layer 108 .

In an IC chip such as IC chip 100 as shown in part in FIG. 1 , the total delay of the net typically includes transistor delays and interconnect RC delays. For stub nets, the total delay consists mostly of transistor delays, where interconnect RC delays are usually negligible. In contrast, for long-wire nets, the total delay mainly consists of interconnect RC delays, where transistor delays are usually negligible. Therefore, the capacitance increase due to the dummy metal fill 114 is generally only important for long timing-critical nets. Therefore, limiting the capacitance increase of long-timing critical nets only within a specified range is usually sufficient to ensure circuit functionality.

For a given IC chip, any suitable number of long-timing critical nets can be selected and designated as designated critical signal nets. According to the process described in more detail below, the capacitance increase of a given critical signal net caused by the dummy metal fill can be optionally limited within a specified range to ensure the function of the circuit. Additionally, or alternatively, the dummy metal fill preferably ensures device matching within the circuit, as will be described in more detail with reference to FIGS. 4-6 .

In order to limit the capacitance increase caused by the dummy metal filling within a specified range, it can be known that as the distance between the dummy metal filling and the original metal line increases, the capacitance increase caused by the dummy metal filling decreases rapidly. However, dummy metal removal is a time-consuming task and is practically impossible to perform manually in IC chips with millions of transistors, even if dummy metal removal is performed only in critical nets.

Thus, as shown in FIG. 1 , the flowing dummy metal fill 114 is blocked or excluded from the fixed bias initial metal 104 minimum or net blocking or buffer distance (NBD) 116 from the designated signal net. By maintaining a minimum NBD distance between the initial metal 104 and the flowing dummy metal fill 114, the increase in capacitance in the critical net caused by the dummy fill can be limited.

As shown in FIGS. 1-3 , the dummy metal fill 114 is blocked in the X, Y, and Z directions within a minimum NBD distance from the designated signal net 104 . Specifically, the dummy metal filling 114 is blocked within the minimum NBD distance from the designated signal net 104 along the X direction in the designated signal net layer 102 . It can be understood that if the specified signal net 104 does not extend the length of the specified signal net layer 102 along the Y direction, then the dummy metal filling 114 in the specified signal net layer 102 will also be blocked from entering the specified distance along the Y direction. Within the minimum NBD distance of the signal network 104. In addition, the dummy metal filling 114 is also blocked within the minimum NBD distance from the designated signal net 104 in the Z direction, that is, in a direction perpendicular to the layers 102, 106, 108 as shown in FIG. Do this for the dummy metal fill.

In the particular embodiment shown, only the upper metal layer 106 and the lower metal layer 108 are located within the NBD distance from a given signal net 104 in the Z direction. Therefore, as shown in the partial top view of FIG. 3 , both the upper metal layer 106 and the lower metal layer 108 have an NBD exclusion zone similar to that of the designated signal net layer 102 . Although not shown, it is understood that the dummy metal fill 114 may be blocked within the NBD distance from the designated signal net 104 in zero or more layers above or below the designated signal net layer 102 . For example, if the NBD is small enough, the dummy metal filling is only prevented from entering within the NBD distance from the designated signal net 104 in the designated signal net layer 102 , while it is not restricted in other layers. For another example, if the NBD is relatively large, not only should the dummy metal fillings be prevented from entering within the NDB distance from the designated signal network layer 104 in the designated signal network layer 102, but also in the above and/or below the designated signal network layer 102. In other layers, it should also be prevented from entering within the NDB distance from the designated signal net 104 . In general, the number of layers for dummy metal-fill blocking is equal to the number of layers above and below a given signal net layer 102 .

An NBD exclusion zone is generally defined as an area that covers a minimum NBD distance from a designated signal net 104 . For example, the NBD exclusion zone may be defined by delineating an imaginary sphere around the designated signal net 104 in all directions. In an alternative embodiment, the NBD exclusion zone may be defined by delineating an imaginary sphere at a specified distance from the signal net 104NBD in each of the X, Y, and Z directions. In general, the designated signal net 104 is usually a rectangular prism with six sides, that is, a rectangular polyhedron, so that the NBD forbidden zone is also a rectangular prism. It will be appreciated that any other suitable NBD exclusion zone may be implemented.

NBD is preferably determined such that the increase in capacitance is limited to a preset amount, thereby ensuring the functionality of the circuit. Preferably, a computer automated program is used to determine the location of the dummy metal to exclude the dummy metal within a distance from the critical wire net NBD. The computer automation program will be described below with reference to FIG. 7 .

As known to those skilled in the art, device matching features include noise cancellation. Therefore, positioning the flowing dummy metal fill while ensuring device matching helps to preserve the symmetric characteristics of the device. Matching of the device may be provided by providing symmetry of the device along at least one axis of symmetry, and/or by providing repeatedly matched elements. Device matching can also be provided by row, column, or array. Matching of devices provided by providing device symmetry along at least one axis of symmetry is described below with reference to FIGS. 4 and 5 , while device matching provided by providing repeatedly matched elements is described below with reference to FIG. 6 .

4 is a partial cross-sectional view of another example IC chip 150 having multiple metal layers 152 and 156 - 162 and achieving device matching by providing device symmetry along axis of symmetry 168 . FIG. 5 is a partial top view of layer 152 , which is a designated signal net, including designated signal nets 154 and 154 ′, which are symmetrical to each other along axis of symmetry 168 . Notably, integrated circuit chip 150 is device matched by having at least one axis of symmetry 168 along which the integrated circuit is device matched.

As shown in FIG. 4, layer 162 is generally a substrate. Although only two IC chip components are shown matched along one axis of symmetry, it will be appreciated that a chip with device matching may generally include any number of symmetrically matched components, for example matched in rows, columns, or arrays. The IC chip 150 with symmetrical device matching along the axis of symmetry is similar to the IC chip shown and described above with reference to FIGS. 1-3 , therefore, for clarity of description, the same elements and principles will not be described in detail again.

The signal net represented by the fixed bias initial metal 154 , 154 ′ may be designated as a critical signal net, and the signal net layer containing the designated critical signal net may be designated as the designated signal net layer 152 . The upper metal layer 156 and the lower metal layer 158 are layers above and below the designated signal mesh layer 152, respectively. In addition, base layers 160, 162 are an upper base and a lower base, respectively.

The flowing dummy metal filling 164 can be located in the designated signal net layer 152 , and can also be located in the upper metal layer 156 and the lower metal layer 158 , thereby ensuring the symmetry of the device along the symmetry axis 168 . As discussed above, the flowing dummy metal fill 164 may be selectively blocked or excluded beyond a minimum or net blocking or buffer distance (NBD) 166 from the fixed bias initial metal 154 , 154 ′ of a given signal net. Furthermore, as shown in FIGS. 4 and 5 , flowing dummy metal fills 164 are positioned symmetrically in layers 152 , 156 , and 158 along the axis of symmetry.

FIG. 6 shows another example IC chip 150' having device matching by providing repeating matching elements 140A, 140B, 140C. In other words, the flowing dummy metal-fills 164 are positioned in the matching elements 140A, 140B, 140C such that each matching element 140A, 140B, 140C has the same number and layout of the flowing dummy metal-fills 164, thereby ensuring the match between them.

Preferably, for a given IC chip with device matching, an axis of symmetry and/or repeated matching elements are specified to facilitate virtual layout while ensuring device matching. An automated computer program is used to determine the location of dummy metals to selectively exclude dummy metals within a distance of NBD from the critical line net while ensuring device compatibility by maintaining symmetry along a designated axis of symmetry, or At the same time, the matching between repeated elements is guaranteed. The computer automation program is described below with reference to FIG. 7 .

FIG. 7 is a flowchart illustrating an automated computer program 130 that determines the placement of dummy metal fills to help ensure device matching and/or limit capacitance increases caused by dummy metal fills. It will be appreciated that the program may be implemented with only the device matching feature, or only the capacitive increase limiting feature, or a combination of both. As mentioned above, dummy metal fill improves planar profile uniformity by helping to planarize the feature density of the layout. The computer automation program 130 positions the dummy metal fillings to ensure device matching, and/or limits the capacitance increase caused by the dummy metal fillings within the specified range of the long timing critical net to ensure the function of the circuit. Specifically, the process 130 facilitates ensuring compatibility of devices, and/or preventing or excluding dummy metal fills from entering within a safe buffer distance from critical nets.

In step 132, the device compatibility of the integrated circuit is determined. As discussed above, device matching can be provided by having at least one axis of symmetry along which the integrated circuit has symmetrically matched elements, and/or by having repeating elements matched in rows, columns, or arrays.

If the procedure 130 cannot be used to block or exclude the dummy metal fill within the buffer distance from the critical net to limit the increase in capacitance, then, as shown by the dashed arrow 142, the procedure will proceed to step 140, which It will be described below.

Alternatively, if the process 130 is capable of blocking or excluding dummy metal fill from within a buffer distance from the critical net to limit the increase in capacitance, then in step 132, the net designated as the critical net, and The maximum acceptable capacitance or delay increase due to dummy metal fill can be determined from user input and/or CAD tools.

Next, in step 134 , the computer automation program determines a minimum safe or buffer distance NBD to limit the increase in capacitance or delay due to the dummy metal fill to within the maximum value determined in step 132 . Typically, this step can be performed before, at the same time, or after step 132 . Any suitable simulation software can be used to determine the minimum safety distance, including existing (COTS) capacitance simulation software in the market, such as the capacitance simulator PASCAL ^™ released by Samsung Electronics Co., Ltd., Seoul, Korea. For example, see "A method for applying An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm", full text incorporated herein by reference. Any other suitable 3D capacitance simulator may be used instead, such as by AVANT! of Fremont, CA! The interconnect structure analysis software product RAPHAEL ^TM released by the company.

In step 136 , the automated computer program identifies the metallic conductors corresponding to the critical nets specified in step 132 . For example, this step can be accomplished by using a wire network tracing method using an integrated circuit input layout file such as a GDS-II format layout file. Alternatively, step 136 may be implemented by notation using an annotated circuit layout file such as an annotated GDS-II format layout file.

In step 138, for each metal conductor identified in step 136, the automated computer program delineates the NBD exclusion zone in the designated signal net layer containing the metal conductor and any metal conductors located within the NBD exclusion zone. The layers above and below the specified signal net layer. prevent dummy metal fills from entering the NDB exclusion zone in layers above and below any specified signal net layer and in each of such layers similar to the blocked zone in the specified signal net layer, or place it excluded from it.

In step 140 , the location of the dummy metal filling is determined to ensure compatibility of the device, and is optionally determined according to the blocking area determined in step 138 . In other words, the dummy metal-fill locations are symmetrical along a specified axis of symmetry, and/or the dummy metal-fill locations are matched between repeating elements and, optionally, only in allowed regions outside of the blocking regions. In order to obtain the desired plan shape, any suitable virtual filling method may be implemented, such as a rule-based or model-based virtual filling procedure.

It can be understood that the program 130 is not limited to the specific order of the steps listed herein. Rather, the various steps of procedure 130 may be performed in any suitable order.

It will be appreciated that systems and methods for maintaining device matching and/or limiting capacitance increase due to the dummy metal fill described herein may be used for certain wafer processing operations such as CMP. However, these systems and methods are generally applicable to any suitable wafer processing operation.

FIG. 8 is a block diagram illustrating a system 170 that may be used to implement the procedure of FIG. 7 for positioning dummy fills during an integrated circuit manufacturing process. Specifically, system 170 may include an input 172 that accepts: (a) a specification of component matching, that is, (i) a specification of an axis of symmetry along which the integrated circuit has symmetric device matching, and/or (ii) ) for the specification of repeatedly matched components; (b) for designating at least one net of an integrated circuit as an input to a designated critical net; (c) for setting the maximum allowable capacitance increase due to dummy fill, or The input of the minimum NDB; (d) a layout file, which is used to specify the layout of an integrated circuit; (e) virtual rules; and/or (f) interconnect symmetry information, which is commonly referred to as a technology file. Typically, the layout file is in GDS-II format or annotated GDS-II format, as is well known in the art. While each of these inputs may be received via input 172 , it is understood that virtual rules have been stored into system 170 . It will be appreciated that although each input data is listed and shown as a single input, any or all of the data may be received by input 172 in any suitable number of separate inputs. For example, a layout file may also include specifications for device matching.

It will also be appreciated that inputs (b), (c) are generally only required in this case: the system 170 can also be used to block dummy metal fills from the buffer distance from the critical net, or exclude them from it to limit the increase in capacitance. In this case, the system 170 may also include a capacitive simulator 174 for determining the minimum blocking distance. The capacitance simulator determines the minimum net blocking distance, which limits the maximum capacitance increment to the set maximum capacitance. As discussed above, the capacitance simulator may implement any suitable capacitance simulation software, such as PASCAL ^™ and/or RAPHAEL ^™ . While providing the minimum net blocking distance as an input to the system 170 for a given program, the capacitance simulator 174 need not be part of the system 170 and thus need not be used in a particular program.

Additionally, system 170 may also include a metallic conductor determination processor 176 that determines metallic conductors corresponding to each designated critical net. Each metal conductor is located in the corresponding designated signal net layer. Accordingly, the system 170 may also include a exclusion zone processor 178 that sets a net blocking exclusion zone in a given signal net layer and any other layers that are within the net blocking distance of the metal conductor.

System 170 includes a dummy fill locator 180 that positions dummy fills according to dummy rules. Dummy fill locator 180 helps ensure device matching characteristics by locating dummy fill while ensuring device matching. For example, the dummy fill locator 180 may symmetrically position the dummy fills along a specified axis of symmetry, and/or position the dummy fills so as to ensure matching between repeated elements. The dummy fill locator 180 can also locate the dummy fill outside the net blocking exclusion zone, while the system 170 can also help block or exclude the dummy metal fill to limit the increase in capacitance.

It will be appreciated that although each component or processor is shown and described as a single processor, any suitable number of processors may be used to implement the functions described herein.

Figures 9 and 10 show a schematic diagram and a block diagram, respectively, of a general principle computer system 1001 suitable for executing software programs to implement the methods and procedures described herein. The architecture and configuration of the computer system 1001 shown and described herein is illustrative only, and other computer architectures and configurations are also applicable.

The exemplary computer system 1001 includes: a display 1003; a screen 1005; a chassis 1007; a keyboard 1009; Chassis 1007 typically houses one or more drives to access computer-readable storage medium 1015, system memory 1053, and hard drive 1055, which may be used to store and/or retrieve: software incorporating computer code programs to implement the methods and programs described herein; and/or data for use with the software programs. A CD or floppy disk 1015 is an exemplary computer readable storage medium that can be read using a corresponding floppy disk or CD-ROM or CD-RW drive 1013 . A computer-readable medium generally refers to any data storage device that can store data which can be read by a computer system. Examples of computer-readable storage media include: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as CD-ROM disks; magneto-optical media, such as optically readable disks, and specially structured hardware devices, such as application-specific integrated circuits (ASICs), programmable logic devices (PLDs); and ROM and RAM devices.

In addition, the computer-readable storage medium may also include a data signal, in particular in the form of a carrier wave, such as a data signal in the form of a carrier wave transmitted in a network. Such a network can be an intranet within a company or other environment, the Internet, or any network comprising multiple computers connected so that the computer readable code can be stored and executed in a distributed fashion.

Computer system 1001 includes various subsystems such as microprocessor 1051 (also known as CPU or central processing unit), system memory 1053, fixed storage 1055 (such as a hard disk), removable storage 1057 (such as a CD-ROM drive), Display adapter 1059 , sound card 1061 , converter 1063 (eg, speaker or microphone), network interface 1065 , and/or printer/fax/scanner interface 1067 . The computer system 1001 also includes a system bus 1069 . However, the specific buses shown are schematic only, illustrating any interconnection design used to connect the various subsystems. For example, a local bus can be used to connect a central processing unit to system memory and a display adapter.

The methods and programs described herein may be executed primarily on the CPU 1051, and/or may be implemented over a network, such as the Internet, Intranet, or LANs (Local Area Networks), connected to a remote CPU that offloads a portion of the processing tasks.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of the claims of the present invention.

Claims (43)

1. A computerized automated method for locating dummy fillers during integrated circuit fabrication, comprising the steps of: receiving as input a layout of the integrated circuit and a specification for device matching of the integrated circuit; and The dummy fillers are positioned in the integrated circuit according to dummy rules while ensuring compatibility of devices. 2. The method of claim 1 , wherein the specifications of the device matching are selected from the group consisting of specifications of at least one axis of symmetry and specifications of repetitive matching elements of the integrated circuit along which the integrated circuit Axes are device compatible. 3. The method of claim 2, wherein the step of locating the dummy filler comprises: positioning the dummy filler along at least one axis of symmetry, wherein the specifications of the device match include specifications of at least one axis of symmetry; and The dummy filling is positioned to ensure the matching of the repeated elements, wherein the specifications of the device matching include the specifications of the repeated matching elements of the integrated circuit. 4. The method of claim 1, further comprising the steps of: designating at least one of said integrated circuit nets as a critical net, said at least one critical net comprising only a subset of all said integrated circuit nets; determining metal conductors corresponding to each critical net from the layout file; and For each identified metal conductor, delineating a wire mesh blocking exclusion zone extending from said metal conductor for a minimum wire mesh blocking distance, Wherein the positioning step of the dummy filler includes positioning the dummy filler outside the restricted area of the wire mesh. 5. A computerized automated method for locating dummy fillers during the manufacture of integrated circuits comprising the steps of: reading a layout file specifying the layout of the integrated circuit; designating at least one of the integrated circuit nets as a critical net, the at least one critical net comprising only a subset of all of the integrated circuit nets; determining metal conductors corresponding to each integrated circuit net from the layout file; For each identified metallic conductor, delineating a wire mesh blocking exclusion zone extending from said metallic conductor for a minimum wire mesh blocking distance; and According to virtual rules, the virtual filler is positioned outside the wire mesh blocking restricted area. 6. A method according to claim 4 or 5, further comprising the step of receiving critical net input for at least one critical net to be specified, the received input being from one of a user and a CAD tool output. 7. The method of claim 4 or 5, further comprising receiving as input the minimum net blocking distance from one of a user and a software program output. 8. The method according to claim 4 or 5, further comprising setting the minimum wire web blocking distance. 9. The method of claim 4 or 5, further comprising: receive the maximum allowable capacitance increment; and The minimum wire mesh blocking distance is determined to limit the maximum capacitance increment to the set maximum allowable capacitance increment. 10. The method of claim 9, wherein the step of determining the minimum wire mesh blocking distance includes applying capacitive simulation software. 11. The method of claim 10, wherein the capacitance simulation software is one of PASCAL ^™ and RAPHAEL ^™ . 12. The method of claim 9, wherein determining the minimum net blocking distance comprises calculating only the at least one integrated circuit net. 13. A method according to claim 4 or 5, wherein said determining step comprises determining all metallic conductors corresponding to said at least one specified critical net. 14. The method according to claim 4 or 5, wherein said determining step comprises using said layout file for one of wire-net tracing and marking. 15. The method according to claim 14, wherein said determining step comprises wire-net tracing, wherein said layout file is in GDS-II format, and said determining step comprises notation, wherein said layout file contains Network connection information. 16. The method according to claim 14, wherein when the layout file includes net connection information, the layout file is one of annotated GDS-II format and LEF/DEF format. 17. The method according to claim 4 or 5, wherein said net blocking exclusion zone comprises at least one blocking area located within a designated signal net layer and any other layer, said signal net layer containing corresponding metal conductors , any other layer is located within said minimum wire mesh blocking distance from said corresponding metal conductor. 18. The method according to claim 4 or 5, wherein the locating step of virtual filling comprises applying at least one of a model-based virtual filling process and a rule-based virtual filling process. 19. A system for locating dummy fills in integrated circuit fabrication, comprising: an input for receiving data including a layout of the integrated circuit and specifications for device matching of the integrated circuit; and A dummy fill locator, which locates the dummy fill in the integrated circuit according to dummy rules, while ensuring the compatibility of devices. 20. The system of claim 19 , wherein specifications of said device matching are selected from the group consisting of specifications of said at least one axis of symmetry and specifications of repeating matching elements of said integrated circuit along said integrated circuit. The above-mentioned axis of symmetry has device matching. 21. The system according to claim 20, wherein the virtual filling locator ensures that The matching of the repeated elements ensures the matchability of the device, wherein the specification of the device matching includes the specification of the at least one symmetry axis, and the specification of the device matching includes the specification of the repeated matching elements of the integrated circuit. 22. The system of claim 19, wherein said input data also designates at least one of said integrated circuit nets as a designated critical net, said at least one critical net comprising only all of said integrated circuit nets A subset of one and less than all of , also including: a metal conductor determination processor configured to determine a metal conductor corresponding to each specified critical net from the layout file; and an exclusion zone processor for, for each determined metal conductor, delineating a wire mesh blocking exclusion zone extending from said metal conductor for a minimum wire mesh blocking distance, Wherein the dummy filling locator also locates the dummy filling outside the forbidden area of the wire mesh according to the virtual rules. 23. A system for locating dummy fills in integrated circuit fabrication, comprising: an input terminal for receiving data including a layout file for determining the layout of the integrated circuit, and designating at least one of the integrated circuit nets as designated critical nets, the at least one critical net comprising only a subset of all said integrated circuit nets; a metal conductor determination processor configured to determine a metal conductor corresponding to each specified critical net from the layout file; an exclusion zone processor for, for each determined metallic conductor, delineating a mesh blocking exclusion zone extending from said metallic conductor for a minimum mesh blocking distance; and A dummy filling locator, which locates the dummy filling outside the forbidden area of the wire mesh according to a virtual rule. 24. The system of claim 22 or 23, wherein the input of the critical network is from one of a user and a CAD tool output. 25. The system of claim 22 or 23, wherein the input also receives as input the minimum wire web blocking distance. 26. The system of claim 22 or 23, wherein the input also receives as input a maximum capacitance increment, the system further comprising: A minimum net blocking distance processor configured to determine the minimum net blocking distance, the minimum net blocking distance being the distance that limits the maximum capacitance increment to the received maximum capacitance. 27. The system of claim 26, wherein the maximum capacitance delta input is a capacitance delta level used to ensure functionality of the integrated circuit. 28. The system of claim 26, wherein the maximum wire mesh blocking distance processor includes capacitive simulation software to determine the minimum wire mesh blocking distance. 29. The system of claim 28, wherein the capacitance simulation software is one of PASCAL ^(TM) and RAPHAEL ^(TM) . 30. The system of claim 26, wherein the minimum net blocking distance processor computes only the at least one specified critical net. 31. The system of claim 22 or 23, wherein the metallic conductor determination processor is configured to determine all metallic conductors corresponding to the at least one specified critical net. 32. The system of claim 22 or 23, wherein the metallic conductor determination processor performs at least one of the wire-net tracing and notation using the layout file. 33. The system of claim 32, wherein the metal conductor determination processor is configured to perform a wire-net tracing method, wherein the layout file is in GDS-II format, and the metal conductor determination processor performs a notation method, Wherein the layout file is one of GDS-II format with annotations and LEF/DEF format. 34. The system of claim 22 or 23, wherein the exclusion zone processor determines the net blocking exclusion zone to include at least one blocking region in a specified signal net layer and any other layer, wherein the specified signal net A layer contains the corresponding metal conductor, and the other layer is located within a minimum wire mesh blocking distance from the corresponding metal conductor. 35. The system of claim 22 or 23, wherein the virtual population locator employs at least one of a model-based virtual population locator and a rule-based virtual population locator. 36. An integrated circuit comprising: a plurality of signal nets having a device matching layout; and A plurality of dummy fillers positioned in a manner that assures compatibility of the device. 37. The integrated circuit of claim 36 , wherein by having said device having at least one device symmetry along at least one axis of symmetry, device symmetry possessed by repeating matching elements, row symmetry, column symmetry, and At least one of array symmetry, matching the devices. 38. The integrated circuit of claim 37, wherein: the dummy filler is positioned along the at least one axis of symmetry, wherein the device compatibility includes at least one axis of symmetry; and The dummy fillers are positioned so as to ensure matching of the repeating elements, wherein the matching of the device includes elements having repeated matching. 39. The integrated circuit of claim 36, wherein said at least one signal net is designated as a critical signal net and the remaining signal nets are non-critical signal nets, said at least one critical signal net includes less than all of said integrated circuit signal nets sets, each critical signal net having a metallic conductor associated with itself; and wherein the dummy fill is positioned outside of a net blocking exclusion zone extending a minimum net blocking distance from the metal conductor associated with each of the critical signal nets, wherein the at least some of the dummy filling An object is positioned within the minimum net blocking distance from a metallic conductor associated with the non-critical signal net. 40. An integrated circuit comprising: a plurality of signal nets, at least one of which is designated as a critical signal net and the remainder are designated as non-critical signal nets, said at least one critical signal net comprising less than all of said integrated circuit signal nets a subset, each critical signal net having a metallic conductor associated with itself; and multiple dummy fillers, wherein the dummy fills are positioned outside of net blocking exclusion zones extending a minimum net blocking distance from the metallic conductors associated with respective critical signal nets, wherein the at least some of the dummy fillings are positioned within a distance of Within a minimum net blocking distance of metallic conductors associated with the non-critical signal net. 41. An integrated circuit according to claim 39 or 40, wherein said minimum net blocking distance depends only on said at least one specified critical signal net. 42. An integrated circuit according to claim 39 or 40, wherein said net blocking exclusion zone comprises at least one blocking area within each designated signal net layer and any other layer, said designated signal net layer comprising The respective metal conductor associated with said at least one critical signal net, said any other layer is located within a minimum net blocking distance from said corresponding metal conductor. 43. An integrated circuit as claimed in claim 39 or 40, wherein the dummy fill is positioned according to at least one of a model-based dummy fill process and a rule-based dummy fill process.

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