AU2003218093A1 - System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase - Google Patents

System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Info

Publication number: AU2003218093A1
Authority: AU; Australia
Prior art keywords: placement; dummy metal; device matching; preserving device; metal fills
Prior art date: 2002-03-12
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Abandoned

Application number

AU2003218093A

Inventor

Soo-Young Oh

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Ubitech Inc

Original Assignee

Ubitech Inc

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

2002-03-12

Filing date

2003-03-12

Publication date

2003-09-29

2002-03-12 Priority claimed from US10/097,978 external-priority patent/US6751785B1/en

2003-03-12 Application filed by Ubitech Inc filed Critical Ubitech Inc

2003-09-29 Publication of AU2003218093A1 publication Critical patent/AU2003218093A1/en

Status Abandoned legal-status Critical Current

Classifications

- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/18—Manufacturability analysis or optimisation for manufacturability
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

Engineering & Computer Science (AREA)
Computer Hardware Design (AREA)
Physics & Mathematics (AREA)
Theoretical Computer Science (AREA)
Evolutionary Computation (AREA)
Geometry (AREA)
General Engineering & Computer Science (AREA)
General Physics & Mathematics (AREA)
Design And Manufacture Of Integrated Circuits (AREA)
Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Semiconductor Integrated Circuits (AREA)

AU2003218093A 2002-03-12 2003-03-12 System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase Abandoned AU2003218093A1 (en)

Applications Claiming Priority (5)

Application Number	Priority Date	Filing Date	Title
US10/097,978 US6751785B1 (en)	2002-03-12	2002-03-12	System and method for limiting increase in capacitance due to dummy metal fills utilized for improving planar profile uniformity
US10/097,978		2002-03-12
US10/158,617 US6904581B1 (en)	2002-03-12	2002-05-30	System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase
US10/158,617		2002-05-30
PCT/US2003/007497 WO2003079240A2 (en)	2002-03-12	2003-03-12	System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Publications (1)

Publication Number	Publication Date
AU2003218093A1 true AU2003218093A1 (en)	2003-09-29

Family

ID=28044138

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
AU2003218093A Abandoned AU2003218093A1 (en)	2002-03-12	2003-03-12	System and method for placement of dummy metal fills while preserving device matching and/or limiting capacitance increase

Country Status (5)

Country	Link
EP (1)	EP1493111A2 (en)
JP (1)	JP2005520336A (en)
CN (1)	CN1643525A (en)
AU (1)	AU2003218093A1 (en)
WO (1)	WO2003079240A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
WO2003104921A2 (en)	2002-06-07	2003-12-18	Praesagus, Inc.	Characterization adn reduction of variation for integrated circuits
US7712056B2 (en)	2002-06-07	2010-05-04	Cadence Design Systems, Inc.	Characterization and verification for integrated circuit designs
US20030229875A1 (en)	2002-06-07	2003-12-11	Smith Taber H.	Use of models in integrated circuit fabrication
US7393755B2 (en)	2002-06-07	2008-07-01	Cadence Design Systems, Inc.	Dummy fill for integrated circuits
US7152215B2 (en)	2002-06-07	2006-12-19	Praesagus, Inc.	Dummy fill for integrated circuits
US7363099B2 (en)	2002-06-07	2008-04-22	Cadence Design Systems, Inc.	Integrated circuit metrology
US7774726B2 (en)	2002-06-07	2010-08-10	Cadence Design Systems, Inc.	Dummy fill for integrated circuits
US7124386B2 (en)	2002-06-07	2006-10-17	Praesagus, Inc.	Dummy fill for integrated circuits
US7188321B2 (en)	2003-11-06	2007-03-06	International Business Machines Corporation	Generation of metal holes by via mutation
JP5180625B2 (en) *	2007-03-12	2013-04-10	ルネサスエレクトロニクス株式会社	Semiconductor device
CN102130043B (en) *	2010-12-30	2013-10-02	中国科学院微电子研究所	Method for filling redundant metal
US12261109B2 (en)	2021-05-19	2025-03-25	Changxin Memory Technologies, Inc.	Semiconductor structure
US12341094B2 (en)	2021-05-19	2025-06-24	Changxin Memory Technologies, Inc.	Semiconductor structure
CN115705459B (en) *	2021-08-13	2025-11-14	长鑫存储技术有限公司	A virtual graphics filling method and semiconductor device layout
CN114722768B (en) *	2022-06-08	2022-09-30	珠海妙存科技有限公司	Chip virtual component design method and device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US5763955A (en) *	1996-07-01	1998-06-09	Vlsi Technology, Inc.	Patterned filled layers for integrated circuit manufacturing
US6323113B1 (en) *	1999-12-10	2001-11-27	Philips Electronics North America Corporation	Intelligent gate-level fill methods for reducing global pattern density effects

2003
- 2003-03-12 JP JP2003577169A patent/JP2005520336A/en not_active Withdrawn
- 2003-03-12 CN CNA038068435A patent/CN1643525A/en active Pending
- 2003-03-12 WO PCT/US2003/007497 patent/WO2003079240A2/en not_active Ceased
- 2003-03-12 AU AU2003218093A patent/AU2003218093A1/en not_active Abandoned
- 2003-03-12 EP EP03714076A patent/EP1493111A2/en not_active Withdrawn

Also Published As

Publication number	Publication date
CN1643525A (en)	2005-07-20
EP1493111A2 (en)	2005-01-05
WO2003079240A3 (en)	2004-07-15
WO2003079240A2 (en)	2003-09-25
JP2005520336A (en)	2005-07-07

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Legal Events

Date	Code	Title	Description
2004-12-02	MK6	Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase