CN1591675B - 具有双磁态的磁性元件 - Google Patents
具有双磁态的磁性元件 Download PDFInfo
- Publication number
- CN1591675B CN1591675B CN2004100641168A CN200410064116A CN1591675B CN 1591675 B CN1591675 B CN 1591675B CN 2004100641168 A CN2004100641168 A CN 2004100641168A CN 200410064116 A CN200410064116 A CN 200410064116A CN 1591675 B CN1591675 B CN 1591675B
- Authority
- CN
- China
- Prior art keywords
- layer
- ferromagnetic layer
- ferromagnetic
- magnetic
- coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000005291 magnetic effect Effects 0.000 title claims abstract description 184
- 230000009977 dual effect Effects 0.000 title abstract 4
- 230000008878 coupling Effects 0.000 claims abstract description 59
- 238000010168 coupling process Methods 0.000 claims abstract description 59
- 238000005859 coupling reaction Methods 0.000 claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 221
- 230000005294 ferromagnetic effect Effects 0.000 claims description 143
- 239000000758 substrate Substances 0.000 claims description 12
- 230000005415 magnetization Effects 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 9
- 230000003313 weakening effect Effects 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 10
- 239000010409 thin film Substances 0.000 abstract 3
- 238000000034 method Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 14
- 239000002184 metal Substances 0.000 description 14
- 230000005303 antiferromagnetism Effects 0.000 description 10
- 230000015654 memory Effects 0.000 description 10
- 230000004043 responsiveness Effects 0.000 description 10
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 8
- 238000003475 lamination Methods 0.000 description 7
- 230000001681 protective effect Effects 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 229910052707 ruthenium Inorganic materials 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 241000675108 Citrus tangerina Species 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- SHMWNGFNWYELHA-UHFFFAOYSA-N iridium manganese Chemical compound [Mn].[Ir] SHMWNGFNWYELHA-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000005292 diamagnetic effect Effects 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000005307 ferromagnetism Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 239000000696 magnetic material Substances 0.000 description 1
- IGOJMROYPFZEOR-UHFFFAOYSA-N manganese platinum Chemical compound [Mn].[Pt] IGOJMROYPFZEOR-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/10—Magnetoresistive devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3254—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y25/00—Nanomagnetism, e.g. magnetoimpedance, anisotropic magnetoresistance, giant magnetoresistance or tunneling magnetoresistance
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F10/00—Thin magnetic films, e.g. of one-domain structure
- H01F10/32—Spin-exchange-coupled multilayers, e.g. nanostructured superlattices
- H01F10/324—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer
- H01F10/3268—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn
- H01F10/3272—Exchange coupling of magnetic film pairs via a very thin non-magnetic spacer, e.g. by exchange with conduction electrons of the spacer the exchange coupling being asymmetric, e.g. by use of additional pinning, by using antiferromagnetic or ferromagnetic coupling interface, i.e. so-called spin-valve [SV] structure, e.g. NiFe/Cu/NiFe/FeMn by use of anti-parallel coupled [APC] ferromagnetic layers, e.g. artificial ferrimagnets [AFI], artificial [AAF] or synthetic [SAF] anti-ferromagnets
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Power Engineering (AREA)
- Nanotechnology (AREA)
- Computer Hardware Design (AREA)
- Hall/Mr Elements (AREA)
- Semiconductor Memories (AREA)
- Mram Or Spin Memory Techniques (AREA)
- Magnetic Heads (AREA)
- Thin Magnetic Films (AREA)
- Measuring Magnetic Variables (AREA)
Abstract
一种改进且新颖的磁性元件(10；10’；50；50’；80)，它含有许多薄膜层，其中单元端部静磁退磁场将抵消这种结构的全部正耦合以在零外磁场下获得双磁态。另外还公开了一种通过提供多个薄膜层来构成一种磁性元件(10)的方法，其中单元端部静磁退磁场将抵消这种结构的全部正耦合以在零外磁场下获得双磁态。
Description
本申请申请日为2000年12月15日的中国专利申请00136605.X的分案申请。
技术领域
本发明涉及信息存储和/或读出用的磁性元件及其制造方法，尤其涉及一种双磁态磁性元件及其制造方法。
背景技术
在此引入与本申请有关且属于同一受让人的下述共同未决申请作参考：Motorola卷号为CR 97-133而美国系列号为09/144,686的专利申请，它于1998年8月31日提出，其名称为“磁随机存取存储器及其制造方法”(“MAGNETIC RANDOM ACCESS MEMORY ANDFABRICATING METHOD THEREOF”)；Motorola卷号为CR 97-158而美国系列号为08/986,764的专利申请，它于1997年12月8日提出，其名称为“磁膜图形构成方法”(“PROCESS OF PATTERNINGMAGNETIC FILMS”)；Motorola卷号为CR 99-001而美国系列号为09/356，864的专利申请，它于1999年7月19日提出，其名称为“具有改进的磁场响应的磁性元件及其制造方法”(“MAGNETICELEMENT WITH IMPROVED FIELD RESPONSE ANDFABRICATING METHOD THEREOF”)；此外，还引入受让人相同而专利号为5,768,181的美国专利作为参考，其颁证日是1998年6月16日，名称为“具有绝热和传导层的多层磁性器件”(“MAGNETICDEVICE HAVING MULTI-LAYER WITH INSULATING ANDCONDUCTIVE LAYERS”)。
一般而言，一种磁性元件诸如磁隧道结存储元件，在结构上它含有用一种非磁性衬垫层隔离的许多铁磁层。信息可按磁化向量的方向存储在磁性层中。例如，另一磁性层中的磁化向量自由地在同向和反向即所谓的“平行”和“反平行”状态间换向，相应地，某一磁性层中的磁化向量会在这个磁场作用范围内被固定或锁定。对应于平行和反平行状态，磁性存储元件表现出两种不同的阻抗。当两磁性层中的磁化向量大体上指向同向和反向时，相应地，阻抗就出现最小值和最大值。而阻抗变换的检测使得可用一种诸如MRAM(磁随机存取存储器)的器件，将信息存储在磁性存储元件中。阻抗的最大值和最小值之差除以最小阻抗值就是公知的磁阻率(MR)。
一种MRAM装置集成着磁性元件，尤其是许多磁性存储元件以及其它电路，例如磁性存储元件控制电路、检测某一磁性存储元件状态用的比较器、输入/输出电路等等。这些线路都是用CMOC(互补金属氧化物半导体)工艺制造的，以便降低器件的能耗。
另外，在结构上，磁性元件含有许多薄层，其中有些是数十埃厚的。磁性元件的阻抗对磁场响应是受这些薄层表面结构所制约的。为了使磁性元件能作为一种存储单元来操作，它处于闲置状态或没有外加磁场作用于它的状态时，至少需具备两种阻抗状态。对磁性元件的这种要求相当于它应有一个相对磁场响应的居中阻抗，必须纠正存在的拓朴正耦合和针孔耦合以形成居中阻抗。
在典型的MTJ(磁隧道结)磁性元件制造中，诸如MRAM存储元件制造中，会含有一种通过溅射沉积，蒸发，或外延工艺而生成的金属膜，其膜表面不是真正平的而是呈现出表面或界面波纹。这种表面和/或铁磁层间界面的波纹是自由铁磁层和其他铁磁层诸如固定层或被牵制层之间存在的磁性耦合的原因，这就是公知的拓扑耦合或尼氏(Neel’s)桔皮耦合。这种耦合一般是不希望在磁性元件中存在的，因为它会造成自由层对外磁场响应的偏移。此外，在常用的自旋阀磁性元件的构成中，还存在电子交换耦合。为了补偿这类耦合，以及其他在MTJ和自旋阀元件中发现的各种耦合作用，必须进行补偿以产生一种居中阻抗，这样才能使器件在双态中操作。
还有，在MRAM存储单元磁场换向时一般存在两种偏移。第一种如前所述是铁磁耦合或正耦合，它是由与拓扑结构相关的静磁耦合引起的，在零外磁场下只能导致低阻抗存储状态。事实上这种存储单元不能工作。要使存储器发挥作用，在零磁场下至少要具备两种存储状态。单元的另一种换向偏移可称作反铁磁性耦合或负耦合。它是由处于长宽比等于或大于1的存储单元端部的静磁耦合引起的。它的作用在于当零外磁场时出现高阻抗存储状态。没有外加的读入磁场这种存储器也不工作。较佳地，应当在不施加由电流脉冲引起的磁场下即可进行读取，以节约能耗并达到高速度。
所以，必须制造一种含有存储单元端部静磁边缘磁场(bit endmagnetostatic fringing fields)的器件，它将抵消这种结构的全部正耦合，从而在零外磁场下实现双磁态。
据称，铁磁耦合强度正比于表面磁荷密度而且确定为夹层厚度指数值的倒数。有一项1998年6月9日颁证且专利号为5,764,567的美国专利，它的名称是“具有用于改进磁场响应的非铁磁性界面层的磁隧道结器件”(“MAGNETIC TUNNEL JUNCTION DEVICE WITHNONFERROMAGNETIC INTERFACE LAYER FOR IMPROVEDMAGNETIC FIELD RESPONSE”)，其中指出：在磁隧道结结构中于靠近氧化铝隧道阻挡层处加一种非磁性的铜层，可以提高磁性层间的间距，达到降低铁磁性桔皮耦合或拓扑耦合。但是，附加铜层会降低隧道结的MR，从而使器件性能恶化。另外，铜层的夹杂也会增加金属蚀刻工艺的复杂性。
发明内容
因而，本发明的目的在于提供一种经过改进的磁性元件，相对外加磁场它有居中阻抗响应曲线，因而能够实现双态操作。
本发明的另一目的在于提供一种经改进的磁性元件，它可对存在的铁磁耦合，尤其是拓扑起因的铁磁耦合或交换耦合予以补偿。
本发明进一步的目的在于提供一种磁性元件，其中的单元端部退磁场(bit end demagnetizing fields)将抵消这种结构的全部正耦合以在零外磁场下获得双磁态。
本发明更进一步的目的在于提供一种制造磁性元件的方法，该元件有对磁场响应的居中阻抗，从而能够实现双态操作。
本发明进一步的目的还在于提供一种制造磁性元件的方法，该元件有对磁场响应的居中阻抗且可改进为适合于大批量生产。
所有这些以及其他需求基本上都是通过提供一种磁性元件来满足的，它含有许多薄膜层，其中的单元端部退磁场可抵消这种结构的全部正耦合以在零外磁场下获得双磁态。此外，也公开了一种通过许多薄膜层制造磁性元件的方法，其中，各薄膜层上的单元端部退磁场将抵消这种结构的全部正耦合以在零外磁场下获得双磁态。
具体而言，本发明提供一种磁性元件(10，10’，50，50’，80)，其特征在于包括：自由铁磁层(30，30’，70，70’，94)；衬垫层(16，16’，56，56’，86)；以及具有多个薄膜层的多层叠片(18，18’，54，54’，84)，其中各个薄膜层具有厚度和磁化强度或偏移特性，使得从多层叠片到自由铁磁层的退磁场消除跨越该磁性元件的衬垫层的正耦合，其中该磁性元件适于在零外磁场下获得双磁态。
根据本发明的上述磁性元件，其中，多个薄膜层形成一种自旋阀结构或磁隧道结结构。
根据本发明的上述磁性元件，其中，多个薄膜层形成一种SAF结构，它含有固定铁磁层(28)和被牵制铁磁层(24)，固定铁磁层具有第一厚度，第一厚度大于被牵制铁磁层的第二厚度，从而消除固定铁磁层与自由铁磁层之间的所述正耦合。
根据本发明的上述磁性元件，其中，多个薄膜层形成一种结构，它含有具有不同的换向磁场的多个铁磁层，其中所述铁磁层之间的偏移提供了铁磁层之间的退磁场的减弱，从而消除铁磁层之间的正耦合。
根据本发明的上述磁性元件，其中，多个铁磁层含有被牵制铁磁层(24)和自由铁磁层(30)，且所述偏移提供了所述多个铁磁层中从被牵制铁磁层向自由铁磁层的退磁场的减弱，从而消除所述多个铁磁层中被牵制铁磁层和自由铁磁层之间的正耦合。
本发明还提供一种磁性元件，其特征在于包括：第一电极(14)，该第一电极的特征在于有固定铁磁层(28)，在存在一特定强度的施加磁场时其磁化强度可固定在某一优选方向，该固定铁磁层具有厚度t1，被牵制铁磁层(24)具有厚度t2，以及位于固定铁磁层和被牵制铁磁层之间的耦合夹层(26)；第二电极(18)，该第二电极的特征在于有自由铁磁层(30)，它有一表面，其磁化强度当存在足够的施加磁场时可自由翻转；衬垫层(16)，它位于第一电极的固定铁磁层和第二电极的自由铁磁层之间；其中固定铁磁层的厚度t1大于被牵制铁磁层的厚度t2，从而消除固定铁磁层和自由铁磁层之间的正耦合；以及衬底(12)，第一和第二电极以及衬垫层都是在该衬底上形成的。
附图说明
图1～5表示许多磁性元件的横剖视图，它们都有本发明所述的已改进的磁场响应；
图6说明拓扑耦合磁场和根据本发明计算的相对于固定磁性层厚度的退磁场的实验结果；
图7说明本发明所述磁性元件的金属薄膜层的磁极。
叙述时，用于说明本发明各图中相同的元件都用同样的数字标记。
具体实施方式
图1和图2用横剖视图说明本发明所述MTJ磁性元件的二种实施例的结构。具体地，在图1中说明了一种构图完整的磁性元件结构10。它含有合成的反铁磁性结构11。这种结构含有衬底12，底层电极多层叠片14，含氧化铝的衬垫层16以及顶层电极多层叠片18。底层电极多层叠片14和顶层电极多层叠片18都含有铁磁层。底层电极层14是形成在金属引线13上的，金属引线13又是形成在衬底12上的。底层电极层14含有许多沉积在底部金属引线13上的底层20，它起仔晶层和模板层的作用，还含有反铁磁性牵制材料层22，被牵制铁磁层24，钌制夹层26以及形成在其上且与下面的反铁磁性牵制层22交换耦合的固定铁磁层28。
底层20一般用钽和钌(Ta/Ru)形成。它们对反铁磁性牵制层22起定向底座的作用。反铁磁性牵制层22一般由铱锰(IrMn)或铂锰(PtMn)组成。
被牵制铁磁层24是受牵制的，它的磁矩交换耦合于牵制层22，以便当出现一个足够大的外磁场去使自由磁性层30翻转时它的磁矩保持不翻转。铁磁层24一般由镍(Ni)、铁(Fe)和钴(Co)中一种或多种的合金形成。其次，夹层26一般由钌形成，其作用是在被牵制铁磁层24和固定铁磁层28间诱发反铁磁性交换耦合。最后，固定铁磁层28是做在钌制夹层26的上表面的。固定铁磁层28是受固定或牵制的，以便当出现一个足够大的外磁场去使自由铁磁层30翻转时，它的磁矩被阻止翻转。
顶层电极叠片18含有自由铁磁层30和保护层32。自由铁磁层30的磁矩是不固定的，或不受交换耦合牵制的，在出现外磁场时它可自由地在两种状态之间翻转。自由铁磁层30一般用镍铁合金(NiFe)形成。
固定铁磁层28的厚度用t1表示，一般在范围。被牵制铁磁层24的厚度用t2表示，一般小于
衬垫层16的厚度用t3表示，一般小于这是对于磁隧道结结构或带铜衬垫的自旋阀型薄膜而言的。在这个具体实施例中，为了补偿横越衬垫层16的正耦合，固定铁磁层28的厚度要做得比被牵制铁磁层24的大，即t1＞t2。应该明白：在这里的披露中考虑到了反向或倒装结构。具体地，考虑到了所公开的磁性元件可以通过包含一个顶层固定或被牵制层来形成，由此描述为一种顶层受牵制结构。
所有磁性层可以是一种单一的磁性材料，或者是用多层磁性层制成的一种组合磁性层，彼此相邻而很好地调整它们的磁参数，诸如换向磁场，磁阻等等。在本实施例中，固定铁磁层28有M1和T1两个参数，M＝磁化强度，T＝厚度，被牵制铁磁层24有M2和T2两个参数，自由铁磁层30有M3和T3两个参数。
为了补偿固定铁磁层28和自由铁磁层30之间存在的正拓扑耦合，乘积M1T1应大于M2T2。可以使T1＞T2，M1＝M2，或使T1＝T2，M1＞M2，或使T1＞T2，M1＞M2来达到。调整M1和T1，与M2T2间的差值即可使正耦合得以全部消除。当M1T1＞M2T2时，在固定铁磁层28的端部将会有未补偿的磁极或磁荷。在长/宽比等于或大于1的高密度存储单元中，存在于自由铁磁层30和固定以及被牵制铁磁层端部之间的静磁耦合是反磁性的，形成了闭合磁通。这种反铁磁性耦合可通过M1T1和M2T2之差来予以调整以完全消除正耦合。
图2是构图完整的磁性元件结构的一种可供选择的实施例，请参阅10’，它含有合成的反铁磁性结构11’。应当指出：第一实施例与第二实施例所有相同的部件都标以相同的标号，加一个撇号以表示不同的实施例。与图1所示的结构相同，此结构含有衬底12’，底层电极多层叠片14’，衬垫层16’以及顶层电极多层叠片18’。底层电极多层叠片14’和顶层电极多层叠片18’都含有铁磁层，与图1中的叠片14和18基本相同。底层电极层14’是形成在金属引线13’上的，而金属引线13’又是形成在衬底12’上的；该电极层14’还含有许多底层20’，底层20’包括沉积在金属引线13’上的第一仔晶层21和一个模板层23。电极层14’还有反铁磁材料层22’，在其上形成且和下面的反铁磁层22’交换耦合的被牵制铁磁层24’，耦合夹层26’以及和被牵制层反铁磁性耦合的固定铁磁层28’。铁磁层24’和28’是受牵制或固定的，在出现外磁场时它们的磁矩是被阻止翻转的。顶层电极叠片18’含有自由铁磁层30’和保护层32’。自由铁磁层30’的磁矩是不固定或不受交换耦合牵制的，在出现外磁场时它的磁矩可自由地在两种状态间翻转。
固定铁磁层28’的厚度用T1表示。被牵制铁磁层24’的厚度用T2表示。在这个具体实施例中，为了补偿横越衬垫层16’的正耦合，固定铁磁层28’的厚度要形成得比被牵制铁磁层24的大些，即T1＞T2。应当明白：在这里的披露中考虑到了反向或倒装结构。具体地，考虑到了所公开的具有SAF结构的磁性元件可以包含顶层固定或被牵制层来形成，由此描述为一种顶层受牵制结构。
这项具体实施例的制造含有两项蚀刻工序。首先，所有各层被蚀刻以确定该磁性器件10’，然后，保护层32’和自由铁磁层30’被蚀刻以确定偏移40。具体地，低于自由铁磁层30’的各层要大于自由铁磁层30’一个偏移量40。对器件10’的这种蚀刻保证了避免跨过衬垫层16’的短路。
现在参阅图3，示出了本发明所述磁性器件的另一种实施例的简化横剖视图。具体地，示出了器件50，它和图1的器件10基本相同，只是在本具体实施例中，磁性元件50不合耦合夹层和固定铁磁层。与图1所述的结构一样，该结构含有衬底52，底层电极多层叠片54，衬垫层56以及顶层电极多层叠片58。底层电极多层叠片54和顶层电极多层叠片58都含有铁磁层，与图1中的叠片14和18基本相同。底层电极层54是形成在金属引线53上的，而金属引线53又形成在衬底52上的；该电极层54含有许多底层60，包括在金属引线53上沉积形成的第一仔晶层61和一个模板层63。底层电极多层叠片54还含有被牵制铁磁层64。被牵制铁磁层64是固定或受牵制的，在出现低于一定强度的外磁场时它的磁矩是被阻止翻转的。顶层电极叠片58含有自由铁磁层70和保护层72。自由铁磁层70的磁矩是不固定或不受交换耦合牵制的，在出现高于一定强度的外磁场时它的磁矩可自由地在两种状态之间翻转。
与图2所述的实施例基本相同，器件50可以含有一个偏移74，见图4。应当明白：图3的实施例与图4的实施例所有相同的部件都标以相同的标号，加一个撇号以表示不同的实施例
在图4所述实施例中，偏移74提供了降低从被牵制铁磁层64’向自由铁磁层70’的退磁场的作用，从而消除被牵制铁磁层64’和自由铁磁层70’之间的正耦合。应当明白：在这里的披露中考虑到了反向或倒装结构。具体地，考虑到了所公开的磁性元件可以通过包含一个顶层固定或被牵制层来形成，由此描述为一种顶层受牵制结构。
再次参阅图4，这项具体实施例的制造含有两项蚀刻工艺。首先，所有各层被蚀刻以确定磁性器件50’。然后，保护层72’和自由铁磁层70’被蚀刻以确定偏移74。具体地，位于自由铁磁层70’以下的各层要大于自由铁磁层70’一个偏移量74。对器件50’的这种蚀刻保证了避免跨过衬垫层56’的短路。
现在参阅图5，示出了本发明所述磁性元件另一种实施例的简化横剖视图。具体地，示出了磁性元件80，它没有耦合夹层和固定铁磁层。与图4提示的结构相同，它含有衬底82，底层电极多层叠片84，第一衬垫层86，第二衬垫层或隧道阻挡层88以及顶层电极多层叠片90。底层电极多层叠片84和顶层电极多层叠片90都含铁磁层，和图1中的叠片14和18基本相同。底层电极多层叠片84是形成在底层金属引线83上的，而该引线83又是形成在衬底82上的；底层电极多层叠片84还含有许多底层，包括在底层金属引线83上沉积形成的第一仔晶层81和选择性的模板层85。底层电极多层叠片84还含有铁磁层92。铁磁层92是固定或受牵的，在出现低于一定强度的外磁场时它的磁矩被阻止翻转。底层电极多层叠片84另外还含有衬垫层86和自由铁磁层94。自由铁磁层94的磁矩是不固定或不受交换耦合牵制的，在出现大于一定强度的外磁场时它可自由地在两种状态间翻转。顶层电极叠片90含有第二固定铁磁层96和保护层98。铁磁层92和96由于端静磁耦合(end-magneto static coupling)而具有反平行排列。
与图4所述的实施例基本相同，器件80可选择性地含有偏移100，如图5所示。偏移100提供了降低从铁磁层92或96的至少一个向自由铁磁层94的退磁场的作用，从而消除铁磁层92或96与自由铁磁层96之间的正耦合。应当明白：在这里的披露考虑到了一种反向或倒装结构。
本具体实施例的制造在存在偏移100时含有二项蚀刻工序。首先，各层被蚀刻以确定磁性器件80，然后保护层98和铁磁层96被蚀刻以确定偏移100。具体地，位于铁磁层96以下的各层要大于被牵制铁磁层96一个偏移量。对器件80的这种蚀刻保证了避免跨过衬垫层88的短路。
现在参阅图6，它图解说明诸如图1中的固定铁磁层28厚度相对于这类磁性元件的拓扑耦合磁场(Hcp1)和单元端部退磁场或负磁场的作用。如图所示，随着图2和图4所述器件层的偏移的增大，退磁场将会减小。偏移小于则会引发一个较大的负磁场或退磁场。磁性元件通常是用在信息存储和/或读出装置上的，它必须利用薄的自由层保持低的换向磁场，然而，当设计的器件具有这些薄自由层时会使拓扑耦合磁场Hcp1增强。相应地，为了补偿或消除这种拓扑磁场Hcp1，可以对在此公开的磁性元件其余结构作出调整，以利用退磁场去补偿或消除这类正耦合磁场。
参阅图7，它示意了利用调整磁层厚度的方法来减弱耦合磁场，诸如调整图1中相对于被牵制层24的固定层28的层厚。如其所示，固定层28的层厚提高到比被牵制层24的大时，存在的正耦合磁场Hcp1就会受到补偿。存在的正端磁极和相对的负端磁极可消除诸如拓扑、针孔和正电子交换等各种正耦合。相应地，如图7所示，一种和图1中的磁性元件10基本相同的磁性元件，它除了包含自由层30，还有层厚大于被牵制层24的固定层28，在层28和30间提供某一差值，从而抵消正耦合并提供相对于磁场响应的居中阻抗并能操作于双态的平衡器件。
更具体地参阅图7，磁端极在层24和28之间形成。固定层28的厚度增加到比被牵制层24的大，便可在磁性元件10中实现对正耦合的补偿。
下面将公开：非磁性的仔晶和模板层，如图3中的层61和63，它的利用将会导致磁场响应耦合的减弱而不需包含SAF结构。该模板层不向该结构施加磁矩，由此，唯一的端静磁耦合是结构中薄被牵制层导致的结果。相应地可以对此进行调整以便消除其耦合强度使器件能在双态下进行操作。当模板层63是非磁性的且不存在SAF结构时，存在由于已构图形状端部的磁极引起的负静磁耦合，因此，通过被牵制层64相对于自由层70的厚度便可控制正耦合。可以选择被牵制层64的厚度以抵消静磁耦合，给出居中回线。因此，通过减小被牵制层64的厚度使其厚度小于被牵制层70，正耦合的抵消作用便可以在磁性元件50中得以实现。
再次参阅图7，示出了图1中磁性元件10的结构，显示出磁极，其中单元端部静磁退磁场消除了该结构的全部正耦合，以便在零外磁场下获得双磁态。
因而，公开了一种能在双态下操作的磁性元件及其构成方法，其中磁耦合被消除，或补偿，这是基于彼此相对的各磁性层厚度或磁化强度与厚度的乘积之上的。该技术可应用于使用构图的磁性元件的器件，诸如磁传感器、磁记录头、磁记录介质以及其他等等。相应地，这些例举也为本公开说明所覆盖。
Claims (6)
1.一种磁性元件(10，10，，50，50，，80)，其特征在于包括：
自由铁磁层(30，30’，70，70’，94)；
衬垫层(16，16’，56，56’，86)；以及
具有多个薄膜层的多层叠片(18，18’，54，54’，84)，其中各个薄膜层具有厚度和磁化强度或偏移特性，使得从所述多层叠片到所述自由铁磁层的退磁场消除跨越该磁性元件的所述衬垫层的正耦合，其中该磁性元件适于在零外磁场下获得双磁态。
2.根据权利要求1所述的磁性元件，其中，所述多个薄膜层形成一种自旋阀结构或磁隧道结结构。
3.根据权利要求2所述的磁性元件，其中，所述多个薄膜层形成一种如下结构，该结构含有固定铁磁层(28)和被牵制铁磁层(24)，所述固定铁磁层具有第一厚度，第一厚度大于被牵制铁磁层的第二厚度，从而消除所述固定铁磁层与自由铁磁层之间的正耦合。
4.根据权利要求2所述的磁性元件，其中，所述多个薄膜层形成一种结构，它含有具有不同的换向磁场的多个铁磁层，其中所述铁磁层之间的偏移提供了所述铁磁层之间的退磁场的减弱，从而消除所述铁磁层之间的正耦合。
5.根据权利要求4所述的磁性元件，其中，所述多个铁磁层含有被牵制铁磁层(24)和自由铁磁层(30)，且所述偏移提供了所述多个铁磁层中从被牵制铁磁层向自由铁磁层的退磁场的减弱，从而消除所述多个铁磁层中被牵制铁磁层和自由铁磁层之间的正耦合。
6.一种磁性元件，其特征在于包括：
第一电极(14)，该第一电极的特征在于有固定铁磁层(28)，该固定铁磁层(28)的磁矩在存在大到足以使自由铁磁层(30)翻转的施加磁场时被阻止翻转，该固定铁磁层具有厚度t1，被牵制铁磁层(24)具有厚度t2，以及位于所述固定铁磁层和所述被牵制铁磁层之间的耦合夹层(26)；
第二电极(18)，该第二电极的特征在于有自由铁磁层(30)，它有一表面，其磁化强度当存在足够的施加磁场时可自由翻转；
衬垫层(16)，它位于所述第一电极的所述固定铁磁层和所述第二电极的所述自由铁磁层之间；
其中所述固定铁磁层的厚度t1大于所述被牵制铁磁层的厚度t2，从而消除所述固定铁磁层和所述自由铁磁层之间的正耦合；以及
衬底(12)，所述第一和第二电极以及所述衬垫层都是在该衬底上形成的。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/464,807 US6233172B1 (en) | 1999-12-17 | 1999-12-17 | Magnetic element with dual magnetic states and fabrication method thereof |
| US09/464,807 | 1999-12-17 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB00136605XA Division CN1171323C (zh) | 1999-12-17 | 2000-12-15 | 具有双磁态的磁性元件 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1591675A CN1591675A (zh) | 2005-03-09 |
| CN1591675B true CN1591675B (zh) | 2011-11-09 |
Family
ID=23845310
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB00136605XA Expired - Fee Related CN1171323C (zh) | 1999-12-17 | 2000-12-15 | 具有双磁态的磁性元件 |
| CN2004100641168A Expired - Fee Related CN1591675B (zh) | 1999-12-17 | 2000-12-15 | 具有双磁态的磁性元件 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB00136605XA Expired - Fee Related CN1171323C (zh) | 1999-12-17 | 2000-12-15 | 具有双磁态的磁性元件 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US6233172B1 (zh) |
| EP (1) | EP1109168B1 (zh) |
| JP (1) | JP4969725B2 (zh) |
| KR (1) | KR100748069B1 (zh) |
| CN (2) | CN1171323C (zh) |
| DE (1) | DE60013079T2 (zh) |
| SG (1) | SG87195A1 (zh) |
Families Citing this family (137)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6172904B1 (en) * | 2000-01-27 | 2001-01-09 | Hewlett-Packard Company | Magnetic memory cell with symmetric switching characteristics |
| US6297983B1 (en) * | 2000-02-29 | 2001-10-02 | Hewlett-Packard Company | Reference layer structure in a magnetic storage cell |
| DE10113853B4 (de) * | 2000-03-23 | 2009-08-06 | Sharp K.K. | Magnetspeicherelement und Magnetspeicher |
| JP4309075B2 (ja) * | 2000-07-27 | 2009-08-05 | 株式会社東芝 | 磁気記憶装置 |
| US6429497B1 (en) * | 2000-11-18 | 2002-08-06 | Hewlett-Packard Company | Method for improving breakdown voltage in magnetic tunnel junctions |
| US6657888B1 (en) | 2001-05-11 | 2003-12-02 | Board Of Regents Of The University Of Nebraska | Application of high spin polarization materials in two terminal non-volatile bistable memory devices |
| DE10128964B4 (de) * | 2001-06-15 | 2012-02-09 | Qimonda Ag | Digitale magnetische Speicherzelleneinrichtung |
| US6510080B1 (en) * | 2001-08-28 | 2003-01-21 | Micron Technology Inc. | Three terminal magnetic random access memory |
| US6485989B1 (en) | 2001-08-30 | 2002-11-26 | Micron Technology, Inc. | MRAM sense layer isolation |
| FR2830971B1 (fr) * | 2001-10-12 | 2004-03-12 | Commissariat Energie Atomique | Dispositif magnetoresistif a vanne de spin a performances ameliorees |
| US6545906B1 (en) | 2001-10-16 | 2003-04-08 | Motorola, Inc. | Method of writing to scalable magnetoresistance random access memory element |
| US6531723B1 (en) * | 2001-10-16 | 2003-03-11 | Motorola, Inc. | Magnetoresistance random access memory for improved scalability |
| KR100638380B1 (ko) * | 2001-11-14 | 2006-10-26 | 노키아 코포레이션 | ＩＰｖ6 용 이동 라우터 지원 |
| DE10158795B4 (de) * | 2001-11-30 | 2005-12-22 | Infineon Technologies Ag | Magnetoresistive Speicherzelle mit dynamischer Referenzschicht |
| JP4157707B2 (ja) * | 2002-01-16 | 2008-10-01 | 株式会社東芝 | 磁気メモリ |
| US6893893B2 (en) * | 2002-03-19 | 2005-05-17 | Applied Materials Inc | Method of preventing short circuits in magnetic film stacks |
| US6728132B2 (en) * | 2002-04-03 | 2004-04-27 | Micron Technology, Inc. | Synthetic-ferrimagnet sense-layer for high density MRAM applications |
| US6724652B2 (en) * | 2002-05-02 | 2004-04-20 | Micron Technology, Inc. | Low remanence flux concentrator for MRAM devices |
| US6879512B2 (en) * | 2002-05-24 | 2005-04-12 | International Business Machines Corporation | Nonvolatile memory device utilizing spin-valve-type designs and current pulses |
| US6683815B1 (en) | 2002-06-26 | 2004-01-27 | Silicon Magnetic Systems | Magnetic memory cell and method for assigning tunable writing currents |
| CN100461419C (zh) * | 2002-07-09 | 2009-02-11 | 日本电气株式会社 | 磁随机存取存储器 |
| US7095646B2 (en) * | 2002-07-17 | 2006-08-22 | Freescale Semiconductor, Inc. | Multi-state magnetoresistance random access cell with improved memory storage density |
| JP2004128237A (ja) * | 2002-10-03 | 2004-04-22 | Sony Corp | 磁気抵抗効果素子および磁気メモリ装置 |
| US6898112B2 (en) * | 2002-12-18 | 2005-05-24 | Freescale Semiconductor, Inc. | Synthetic antiferromagnetic structure for magnetoelectronic devices |
| US7002228B2 (en) * | 2003-02-18 | 2006-02-21 | Micron Technology, Inc. | Diffusion barrier for improving the thermal stability of MRAM devices |
| US6885073B2 (en) * | 2003-04-02 | 2005-04-26 | Micron Technology, Inc. | Method and apparatus providing MRAM devices with fine tuned offset |
| JP4863151B2 (ja) * | 2003-06-23 | 2012-01-25 | 日本電気株式会社 | 磁気ランダム・アクセス・メモリとその製造方法 |
| US6956763B2 (en) * | 2003-06-27 | 2005-10-18 | Freescale Semiconductor, Inc. | MRAM element and methods for writing the MRAM element |
| US7573737B2 (en) * | 2003-08-19 | 2009-08-11 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
| US8755222B2 (en) | 2003-08-19 | 2014-06-17 | New York University | Bipolar spin-transfer switching |
| US7911832B2 (en) * | 2003-08-19 | 2011-03-22 | New York University | High speed low power magnetic devices based on current induced spin-momentum transfer |
| US6967366B2 (en) * | 2003-08-25 | 2005-11-22 | Freescale Semiconductor, Inc. | Magnetoresistive random access memory with reduced switching field variation |
| JP2005129801A (ja) * | 2003-10-24 | 2005-05-19 | Sony Corp | 磁気記憶素子及び磁気メモリ |
| JP4631267B2 (ja) * | 2003-10-27 | 2011-02-16 | ソニー株式会社 | 磁気記憶素子及び磁気メモリ |
| US7045838B2 (en) * | 2003-10-31 | 2006-05-16 | International Business Machines Corporation | Techniques for coupling in semiconductor devices and magnetic device using these techniques |
| US7053429B2 (en) * | 2003-11-06 | 2006-05-30 | Honeywell International Inc. | Bias-adjusted giant magnetoresistive (GMR) devices for magnetic random access memory (MRAM) applications |
| KR100988086B1 (ko) * | 2003-11-14 | 2010-10-18 | 삼성전자주식회사 | 자기 모멘트가 낮은 프리 자성막을 구비하는 자기터널접합셀 및 이를 포함하는 자기램 |
| US7031183B2 (en) * | 2003-12-08 | 2006-04-18 | Freescale Semiconductor, Inc. | MRAM device integrated with other types of circuitry |
| US7072209B2 (en) * | 2003-12-29 | 2006-07-04 | Micron Technology, Inc. | Magnetic memory having synthetic antiferromagnetic pinned layer |
| JP4737437B2 (ja) * | 2004-03-05 | 2011-08-03 | 日本電気株式会社 | トグル型磁気ランダムアクセスメモリ |
| WO2005098953A1 (ja) * | 2004-03-31 | 2005-10-20 | Nec Corporation | 磁化方向制御方法、及びそれを応用したｍｒａｍ |
| US7067330B2 (en) * | 2004-07-16 | 2006-06-27 | Headway Technologies, Inc. | Magnetic random access memory array with thin conduction electrical read and write lines |
| JP4868198B2 (ja) * | 2004-08-19 | 2012-02-01 | 日本電気株式会社 | 磁性メモリ |
| US7129098B2 (en) * | 2004-11-24 | 2006-10-31 | Freescale Semiconductor, Inc. | Reduced power magnetoresistive random access memory elements |
| JP5077802B2 (ja) | 2005-02-16 | 2012-11-21 | 日本電気株式会社 | 積層強磁性構造体、及び、ｍｔｊ素子 |
| JP4877575B2 (ja) * | 2005-05-19 | 2012-02-15 | 日本電気株式会社 | 磁気ランダムアクセスメモリ |
| US7301801B2 (en) * | 2005-10-28 | 2007-11-27 | International Business Machines Corporation | Tuned pinned layers for magnetic tunnel junctions with multicomponent free layers |
| US20080112214A1 (en) * | 2006-10-30 | 2008-05-15 | Young Sir Chung | Electronic assembly having magnetic tunnel junction voltage sensors and method for forming the same |
| JP4380693B2 (ja) * | 2006-12-12 | 2009-12-09 | ソニー株式会社 | 記憶素子、メモリ |
| JP4380707B2 (ja) * | 2007-01-19 | 2009-12-09 | ソニー株式会社 | 記憶素子 |
| US9812184B2 (en) | 2007-10-31 | 2017-11-07 | New York University | Current induced spin-momentum transfer stack with dual insulating layers |
| US7821771B2 (en) * | 2008-04-11 | 2010-10-26 | Northern Lights Semiconductor Corp. | Apparatus for storing electrical energy |
| US8705212B2 (en) | 2011-04-25 | 2014-04-22 | Seagate Technology Llc | Magnetic element with enhanced coupling portion |
| US8686484B2 (en) * | 2011-06-10 | 2014-04-01 | Everspin Technologies, Inc. | Spin-torque magnetoresistive memory element and method of fabricating same |
| US8755154B2 (en) | 2011-09-13 | 2014-06-17 | Seagate Technology Llc | Tuned angled uniaxial anisotropy in trilayer magnetic sensors |
| US8829901B2 (en) * | 2011-11-04 | 2014-09-09 | Honeywell International Inc. | Method of using a magnetoresistive sensor in second harmonic detection mode for sensing weak magnetic fields |
| WO2013101203A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Balancing energy barrier between states in perpendicular magnetic tunnel junctions |
| US9082888B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Inverted orthogonal spin transfer layer stack |
| US9082950B2 (en) | 2012-10-17 | 2015-07-14 | New York University | Increased magnetoresistance in an inverted orthogonal spin transfer layer stack |
| US8982613B2 (en) | 2013-06-17 | 2015-03-17 | New York University | Scalable orthogonal spin transfer magnetic random access memory devices with reduced write error rates |
| US10158065B2 (en) * | 2014-07-07 | 2018-12-18 | Intel Corporation | Spin-transfer torque memory (STTM) devices having magnetic contacts |
| US9263667B1 (en) | 2014-07-25 | 2016-02-16 | Spin Transfer Technologies, Inc. | Method for manufacturing MTJ memory device |
| US9337412B2 (en) | 2014-09-22 | 2016-05-10 | Spin Transfer Technologies, Inc. | Magnetic tunnel junction structure for MRAM device |
| EP3045928B1 (en) * | 2015-01-16 | 2017-07-12 | Crocus Technology | Magnetic logic unit (MLU) cell for sensing magnetic fields with improved programmability and low reading consumption |
| US10468590B2 (en) | 2015-04-21 | 2019-11-05 | Spin Memory, Inc. | High annealing temperature perpendicular magnetic anisotropy structure for magnetic random access memory |
| US9728712B2 (en) | 2015-04-21 | 2017-08-08 | Spin Transfer Technologies, Inc. | Spin transfer torque structure for MRAM devices having a spin current injection capping layer |
| US9853206B2 (en) | 2015-06-16 | 2017-12-26 | Spin Transfer Technologies, Inc. | Precessional spin current structure for MRAM |
| US9773974B2 (en) | 2015-07-30 | 2017-09-26 | Spin Transfer Technologies, Inc. | Polishing stop layer(s) for processing arrays of semiconductor elements |
| US10163479B2 (en) | 2015-08-14 | 2018-12-25 | Spin Transfer Technologies, Inc. | Method and apparatus for bipolar memory write-verify |
| US9741926B1 (en) | 2016-01-28 | 2017-08-22 | Spin Transfer Technologies, Inc. | Memory cell having magnetic tunnel junction and thermal stability enhancement layer |
| US11119910B2 (en) | 2016-09-27 | 2021-09-14 | Spin Memory, Inc. | Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments |
| US10991410B2 (en) | 2016-09-27 | 2021-04-27 | Spin Memory, Inc. | Bi-polar write scheme |
| US10360964B2 (en) | 2016-09-27 | 2019-07-23 | Spin Memory, Inc. | Method of writing contents in memory during a power up sequence using a dynamic redundancy register in a memory device |
| US10546625B2 (en) | 2016-09-27 | 2020-01-28 | Spin Memory, Inc. | Method of optimizing write voltage based on error buffer occupancy |
| US11119936B2 (en) | 2016-09-27 | 2021-09-14 | Spin Memory, Inc. | Error cache system with coarse and fine segments for power optimization |
| US10446210B2 (en) | 2016-09-27 | 2019-10-15 | Spin Memory, Inc. | Memory instruction pipeline with a pre-read stage for a write operation for reducing power consumption in a memory device that uses dynamic redundancy registers |
| US10460781B2 (en) | 2016-09-27 | 2019-10-29 | Spin Memory, Inc. | Memory device with a dual Y-multiplexer structure for performing two simultaneous operations on the same row of a memory bank |
| US10628316B2 (en) | 2016-09-27 | 2020-04-21 | Spin Memory, Inc. | Memory device with a plurality of memory banks where each memory bank is associated with a corresponding memory instruction pipeline and a dynamic redundancy register |
| US11151042B2 (en) | 2016-09-27 | 2021-10-19 | Integrated Silicon Solution, (Cayman) Inc. | Error cache segmentation for power reduction |
| US10437723B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of flushing the contents of a dynamic redundancy register to a secure storage area during a power down in a memory device |
| US10366774B2 (en) | 2016-09-27 | 2019-07-30 | Spin Memory, Inc. | Device with dynamic redundancy registers |
| US10437491B2 (en) | 2016-09-27 | 2019-10-08 | Spin Memory, Inc. | Method of processing incomplete memory operations in a memory device during a power up sequence and a power down sequence using a dynamic redundancy register |
| US10818331B2 (en) | 2016-09-27 | 2020-10-27 | Spin Memory, Inc. | Multi-chip module for MRAM devices with levels of dynamic redundancy registers |
| US10665777B2 (en) | 2017-02-28 | 2020-05-26 | Spin Memory, Inc. | Precessional spin current structure with non-magnetic insertion layer for MRAM |
| US10672976B2 (en) | 2017-02-28 | 2020-06-02 | Spin Memory, Inc. | Precessional spin current structure with high in-plane magnetization for MRAM |
| US10032978B1 (en) | 2017-06-27 | 2018-07-24 | Spin Transfer Technologies, Inc. | MRAM with reduced stray magnetic fields |
| US10529439B2 (en) | 2017-10-24 | 2020-01-07 | Spin Memory, Inc. | On-the-fly bit failure detection and bit redundancy remapping techniques to correct for fixed bit defects |
| US10489245B2 (en) | 2017-10-24 | 2019-11-26 | Spin Memory, Inc. | Forcing stuck bits, waterfall bits, shunt bits and low TMR bits to short during testing and using on-the-fly bit failure detection and bit redundancy remapping techniques to correct them |
| US10656994B2 (en) | 2017-10-24 | 2020-05-19 | Spin Memory, Inc. | Over-voltage write operation of tunnel magnet-resistance (“TMR”) memory device and correcting failure bits therefrom by using on-the-fly bit failure detection and bit redundancy remapping techniques |
| US10481976B2 (en) | 2017-10-24 | 2019-11-19 | Spin Memory, Inc. | Forcing bits as bad to widen the window between the distributions of acceptable high and low resistive bits thereby lowering the margin and increasing the speed of the sense amplifiers |
| US10679685B2 (en) | 2017-12-27 | 2020-06-09 | Spin Memory, Inc. | Shared bit line array architecture for magnetoresistive memory |
| US10395712B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Memory array with horizontal source line and sacrificial bitline per virtual source |
| US10395711B2 (en) | 2017-12-28 | 2019-08-27 | Spin Memory, Inc. | Perpendicular source and bit lines for an MRAM array |
| US10424726B2 (en) | 2017-12-28 | 2019-09-24 | Spin Memory, Inc. | Process for improving photoresist pillar adhesion during MRAM fabrication |
| US10360962B1 (en) | 2017-12-28 | 2019-07-23 | Spin Memory, Inc. | Memory array with individually trimmable sense amplifiers |
| US10516094B2 (en) | 2017-12-28 | 2019-12-24 | Spin Memory, Inc. | Process for creating dense pillars using multiple exposures for MRAM fabrication |
| US10891997B2 (en) | 2017-12-28 | 2021-01-12 | Spin Memory, Inc. | Memory array with horizontal source line and a virtual source line |
| US10811594B2 (en) | 2017-12-28 | 2020-10-20 | Spin Memory, Inc. | Process for hard mask development for MRAM pillar formation using photolithography |
| US10424723B2 (en) | 2017-12-29 | 2019-09-24 | Spin Memory, Inc. | Magnetic tunnel junction devices including an optimization layer |
| US10236048B1 (en) | 2017-12-29 | 2019-03-19 | Spin Memory, Inc. | AC current write-assist in orthogonal STT-MRAM |
| US10199083B1 (en) | 2017-12-29 | 2019-02-05 | Spin Transfer Technologies, Inc. | Three-terminal MRAM with ac write-assist for low read disturb |
| US10270027B1 (en) | 2017-12-29 | 2019-04-23 | Spin Memory, Inc. | Self-generating AC current assist in orthogonal STT-MRAM |
| US10840439B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Magnetic tunnel junction (MTJ) fabrication methods and systems |
| US10840436B2 (en) | 2017-12-29 | 2020-11-17 | Spin Memory, Inc. | Perpendicular magnetic anisotropy interface tunnel junction devices and methods of manufacture |
| US10367139B2 (en) | 2017-12-29 | 2019-07-30 | Spin Memory, Inc. | Methods of manufacturing magnetic tunnel junction devices |
| US10784439B2 (en) | 2017-12-29 | 2020-09-22 | Spin Memory, Inc. | Precessional spin current magnetic tunnel junction devices and methods of manufacture |
| US10236047B1 (en) | 2017-12-29 | 2019-03-19 | Spin Memory, Inc. | Shared oscillator (STNO) for MRAM array write-assist in orthogonal STT-MRAM |
| US10546624B2 (en) | 2017-12-29 | 2020-01-28 | Spin Memory, Inc. | Multi-port random access memory |
| US10886330B2 (en) | 2017-12-29 | 2021-01-05 | Spin Memory, Inc. | Memory device having overlapping magnetic tunnel junctions in compliance with a reference pitch |
| US10360961B1 (en) | 2017-12-29 | 2019-07-23 | Spin Memory, Inc. | AC current pre-charge write-assist in orthogonal STT-MRAM |
| US10236439B1 (en) | 2017-12-30 | 2019-03-19 | Spin Memory, Inc. | Switching and stability control for perpendicular magnetic tunnel junction device |
| US10339993B1 (en) | 2017-12-30 | 2019-07-02 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with skyrmionic assist layers for free layer switching |
| US10255962B1 (en) | 2017-12-30 | 2019-04-09 | Spin Memory, Inc. | Microwave write-assist in orthogonal STT-MRAM |
| US10319900B1 (en) | 2017-12-30 | 2019-06-11 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with precessional spin current layer having a modulated moment density |
| US10141499B1 (en) | 2017-12-30 | 2018-11-27 | Spin Transfer Technologies, Inc. | Perpendicular magnetic tunnel junction device with offset precessional spin current layer |
| US10229724B1 (en) | 2017-12-30 | 2019-03-12 | Spin Memory, Inc. | Microwave write-assist in series-interconnected orthogonal STT-MRAM devices |
| US10468588B2 (en) | 2018-01-05 | 2019-11-05 | Spin Memory, Inc. | Perpendicular magnetic tunnel junction device with skyrmionic enhancement layers for the precessional spin current magnetic layer |
| US10438995B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Devices including magnetic tunnel junctions integrated with selectors |
| US10438996B2 (en) | 2018-01-08 | 2019-10-08 | Spin Memory, Inc. | Methods of fabricating magnetic tunnel junctions integrated with selectors |
| US10388861B1 (en) | 2018-03-08 | 2019-08-20 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
| US10446744B2 (en) | 2018-03-08 | 2019-10-15 | Spin Memory, Inc. | Magnetic tunnel junction wafer adaptor used in magnetic annealing furnace and method of using the same |
| US11107974B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Magnetic tunnel junction devices including a free magnetic trench layer and a planar reference magnetic layer |
| US20190296223A1 (en) | 2018-03-23 | 2019-09-26 | Spin Memory, Inc. | Methods of Manufacturing Three-Dimensional Arrays with Magnetic Tunnel Junction Devices Including an Annular Free Magnetic Layer and a Planar Reference Magnetic Layer |
| US11107978B2 (en) | 2018-03-23 | 2021-08-31 | Spin Memory, Inc. | Methods of manufacturing three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
| US10784437B2 (en) | 2018-03-23 | 2020-09-22 | Spin Memory, Inc. | Three-dimensional arrays with MTJ devices including a free magnetic trench layer and a planar reference magnetic layer |
| US10411185B1 (en) | 2018-05-30 | 2019-09-10 | Spin Memory, Inc. | Process for creating a high density magnetic tunnel junction array test platform |
| US10593396B2 (en) | 2018-07-06 | 2020-03-17 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
| US10559338B2 (en) | 2018-07-06 | 2020-02-11 | Spin Memory, Inc. | Multi-bit cell read-out techniques |
| US10692569B2 (en) | 2018-07-06 | 2020-06-23 | Spin Memory, Inc. | Read-out techniques for multi-bit cells |
| US10600478B2 (en) | 2018-07-06 | 2020-03-24 | Spin Memory, Inc. | Multi-bit cell read-out techniques for MRAM cells with mixed pinned magnetization orientations |
| US10650875B2 (en) | 2018-08-21 | 2020-05-12 | Spin Memory, Inc. | System for a wide temperature range nonvolatile memory |
| US10699761B2 (en) | 2018-09-18 | 2020-06-30 | Spin Memory, Inc. | Word line decoder memory architecture |
| US11621293B2 (en) | 2018-10-01 | 2023-04-04 | Integrated Silicon Solution, (Cayman) Inc. | Multi terminal device stack systems and methods |
| US10971680B2 (en) | 2018-10-01 | 2021-04-06 | Spin Memory, Inc. | Multi terminal device stack formation methods |
| US10580827B1 (en) | 2018-11-16 | 2020-03-03 | Spin Memory, Inc. | Adjustable stabilizer/polarizer method for MRAM with enhanced stability and efficient switching |
| US11107979B2 (en) | 2018-12-28 | 2021-08-31 | Spin Memory, Inc. | Patterned silicide structures and methods of manufacture |
| US11500042B2 (en) | 2020-02-28 | 2022-11-15 | Brown University | Magnetic sensing devices based on interlayer exchange-coupled magnetic thin films |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648885A (en) * | 1995-08-31 | 1997-07-15 | Hitachi, Ltd. | Giant magnetoresistive effect sensor, particularly having a multilayered magnetic thin film layer |
| CN1196814A (zh) * | 1996-05-24 | 1998-10-21 | Mke－昆腾部件科罗拉多责任有限公司 | 垂面电流自旋阀式磁阻传感器 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5764567A (en) * | 1996-11-27 | 1998-06-09 | International Business Machines Corporation | Magnetic tunnel junction device with nonferromagnetic interface layer for improved magnetic field response |
| US5801984A (en) * | 1996-11-27 | 1998-09-01 | International Business Machines Corporation | Magnetic tunnel junction device with ferromagnetic multilayer having fixed magnetic moment |
| JP3253557B2 (ja) * | 1997-05-07 | 2002-02-04 | 株式会社東芝 | 磁気抵抗効果素子とそれを用いた磁気ヘッドおよび磁気記憶装置 |
| US5898612A (en) * | 1997-05-22 | 1999-04-27 | Motorola, Inc. | Magnetic memory cell with increased GMR ratio |
| US5828598A (en) * | 1997-05-23 | 1998-10-27 | Motorola, Inc. | MRAM with high GMR ratio |
| JP3137288B2 (ja) * | 1997-11-17 | 2001-02-19 | 松下電器産業株式会社 | 交換結合膜、磁気抵抗効果素子、磁気抵抗効果型ヘッドおよび磁気抵抗効果素子の製造方法 |
| US5959880A (en) * | 1997-12-18 | 1999-09-28 | Motorola, Inc. | Low aspect ratio magnetoresistive tunneling junction |
| JP3831573B2 (ja) * | 1998-07-21 | 2006-10-11 | アルプス電気株式会社 | スピンバルブ型薄膜素子の製造方法及びこのスピンバルブ型薄膜素子を用いた薄膜磁気ヘッドの製造方法 |
-
1999
- 1999-12-17 US US09/464,807 patent/US6233172B1/en not_active Expired - Lifetime
-
2000
- 2000-12-08 SG SG200007285A patent/SG87195A1/en unknown
- 2000-12-11 EP EP00127093A patent/EP1109168B1/en not_active Expired - Lifetime
- 2000-12-11 DE DE60013079T patent/DE60013079T2/de not_active Expired - Fee Related
- 2000-12-12 KR KR1020000075640A patent/KR100748069B1/ko not_active Expired - Lifetime
- 2000-12-15 CN CNB00136605XA patent/CN1171323C/zh not_active Expired - Fee Related
- 2000-12-15 CN CN2004100641168A patent/CN1591675B/zh not_active Expired - Fee Related
- 2000-12-18 JP JP2000383163A patent/JP4969725B2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5648885A (en) * | 1995-08-31 | 1997-07-15 | Hitachi, Ltd. | Giant magnetoresistive effect sensor, particularly having a multilayered magnetic thin film layer |
| CN1196814A (zh) * | 1996-05-24 | 1998-10-21 | Mke－昆腾部件科罗拉多责任有限公司 | 垂面电流自旋阀式磁阻传感器 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1109168A2 (en) | 2001-06-20 |
| DE60013079T2 (de) | 2005-01-27 |
| CN1309301A (zh) | 2001-08-22 |
| SG87195A1 (en) | 2002-03-19 |
| JP4969725B2 (ja) | 2012-07-04 |
| KR20010062357A (ko) | 2001-07-07 |
| CN1591675A (zh) | 2005-03-09 |
| EP1109168A3 (en) | 2002-04-03 |
| KR100748069B1 (ko) | 2007-08-09 |
| JP2001250999A (ja) | 2001-09-14 |
| US6233172B1 (en) | 2001-05-15 |
| DE60013079D1 (de) | 2004-09-23 |
| CN1171323C (zh) | 2004-10-13 |
| EP1109168B1 (en) | 2004-08-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1591675B (zh) | 具有双磁态的磁性元件 | |
| EP1132919B1 (en) | Memory cell | |
| US6469926B1 (en) | Magnetic element with an improved magnetoresistance ratio and fabricating method thereof | |
| US6205052B1 (en) | Magnetic element with improved field response and fabricating method thereof | |
| US8178363B2 (en) | MRAM with storage layer and super-paramagnetic sensing layer | |
| US6376260B1 (en) | Magnetic element with improved field response and fabricating method thereof | |
| US6396735B2 (en) | Magnetic memory element, magnetic memory and manufacturing method of magnetic memory | |
| KR100713270B1 (ko) | 스핀 이동 스위칭을 이용하고 다중 비트를 저장하는마그네틱 메모리 부재 | |
| US6593608B1 (en) | Magneto resistive storage device having double tunnel junction | |
| EP1248265A2 (en) | Magnetic memory cell | |
| US20130005052A1 (en) | Magnetic tunnel junction with iron dusting layer between free layer and tunnel barrier | |
| US6649960B1 (en) | Synthetic free layer structure for MRAM devices | |
| JP2007515075A (ja) | Ｍｒａｍ技術のｍｔｊに使用される合成反強磁性体構造 | |
| EP1547101A1 (en) | Amorphous alloys for magnetic devices | |
| US8456903B2 (en) | Magnetic memory with porous non-conductive current confinement layer | |
| US7173300B2 (en) | Magnetoresistive element, method for making the same, and magnetic memory device incorporating the same | |
| US7200035B2 (en) | Magneto-resistive memory cell structures with improved selectivity | |
| HK1075125A (zh) | 具有双磁态的磁性元件及其制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1075125 Country of ref document: HK |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20090306 Address after: Arizona USA Applicant after: EVERSPIN TECHNOLOGIES, Inc. Address before: Texas in the United States Applicant before: FreeScale Semiconductor |
|
| ASS | Succession or assignment of patent right |
Owner name: EVERSPIN TECHNOLOGIES, INC. Free format text: FORMER OWNER: FREEDOM SEMICONDUCTORS CO. Effective date: 20090306 |
|
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: WD Ref document number: 1075125 Country of ref document: HK |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20111109 Termination date: 20171215 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |