CN1567719A - Minimum pulse width detection and regeneration circuit - Google Patents
Minimum pulse width detection and regeneration circuit Download PDFInfo
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- CN1567719A CN1567719A CN 03142981 CN03142981A CN1567719A CN 1567719 A CN1567719 A CN 1567719A CN 03142981 CN03142981 CN 03142981 CN 03142981 A CN03142981 A CN 03142981A CN 1567719 A CN1567719 A CN 1567719A
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Abstract
本发明是一种最小脉冲宽度侦测与重生电路。首先，该电路包括一脉冲宽度侦测器，其能够侦测一输入讯号脉冲是否在最小宽度与最大宽度之间的范围内；其次，如果输入讯号脉冲在该范围内，脉冲宽度延伸器能够延伸输入讯号脉冲宽度至该最大宽度。最后，如果输入讯号脉冲小于最小宽度，干扰讯号滤波器能够滤除输入讯号脉冲。
The present invention is a minimum pulse width detection and regeneration circuit. First, the circuit includes a pulse width detector, which can detect whether an input signal pulse is within a range between a minimum width and a maximum width; second, if the input signal pulse is within the range, a pulse width stretcher can stretch the input signal pulse width to the maximum width. Finally, if the input signal pulse is less than the minimum width, an interference signal filter can filter out the input signal pulse.
Description
Technical field
The invention relates to a kind of input signal condition circuit, especially a kind of about the minimum pulse width detecting and the circuit of living again.
Background technology
Electronic circuit often meets with small pulse duration signal or disturbs signal problems such as (glitch).Disturb signal to betide the interface place of the various integrated circuit packages in the system usually, especially when various assemblies were asynchronous with shared system clock pulse, the interference signal also can be owing to excessive fan-out (fan-out), load or noise betide in the synchro system.
Now see also Fig. 1, it is to illustrate a kind of common previous memory signal sequential chart.In the figure, system's clock pulse CLK is represented by a fixed cycle signal.The address bus ADDR of memory storage is represented by a string bus-bar state and state variation (transition).For the position in the memory storage of access such as Dynamic Random Access Memory (DRAM), for the reading (read) or write (write) of data, microcontroller must be by forcing address bus to the memory address of being desired, with chosen position.On specification, must carry out address and set, and make stable address at minimum time (setup time) t
sWithin arrive the clock pulse edge, be the drop edge in this example.In addition, address must be at the minimum hold time after the CLK of drop edge (hold time) t
HWithin keep stable.The specification of these times and retention time value is the internal interference signal that is used for eliminating in the memory storage, and can be at address, data and instruction.
The use of the specification of time and retention time value can't avoid forever because the interference signals that problem caused such as above-mentioned fan-out, load, noise and other.System design meeting sometimes causes asynchronous interface, and forms the problem that is difficult to overcome.Now see also Fig. 2, it is to be presented at the case that produces the internal interference signal in the Prior Art.In present case, and lock (AND gate) 10 is used for logically in conjunction with signal A and B, to produce signal C.Its sequential chart shows a kind of problematic situation, and wherein the state variation of A and B is very approaching.So cause the interference signal 14 of C.One to disturb signal 14 be not what have a mind to usually for this, and when simplation validation since for parasitics define or since the parameter drift of installing can not occur usually.Yet, disturb the propagation of signal 14 to have and seriously influence for circuit operation.
In case short time pulse or interference signal are introduced in the digital circuit, it can use filter circuit to be removed.Now seeing also Fig. 3, is the filter circuit that shows Prior Art.In this circuit, the having from the low level to the high levels of IN signal, the just interference signal of at once getting back to the brief burst of low level from high levels can be filtered again.Have only the length that has of IN signal to see through with and not b gate (NAND) 20 greater than the just interference signal of the propagation delay of delay element 28 and arrive output OUT with inverter 24.The subject matter of this prior art filtered method is, if input pulse has the propagation delay less times greater than delay element, filter itself will produce a new interference signal.Therefore, prior art approach still is not enough to solve this problem.
Now seeing also Fig. 4, is to show to disturb the signal extension circuit.This circuit uses a delay element 36 and an anti-or lock (NOR) 32, has been extended the time span that delay circuit is introduced to cause the positive pulse length on the input signal IN.This mode comes in handy for some case, and its shortcoming may produce from little or nondestructive interference signal for big and destructive interference signal.
The invention of some prior arts is described the input signal processing and is removed circuit with disturbing signal.Tedrow is at United States Patent (USP) the 6th, 075, described a kind of detecting in No. 751 and with the synchronized circuit of input signal, it comprises a filter and a pulse generator.Teymouri is at United States Patent (USP) the 5th, 113, disclosed a kind of interference signal that is used to transmit binding in No. 098 and removed circuit, and it uses a hysteresis input buffer and a filter circuit.People such as Wu are at United States Patent (USP) the 5th, 563, and a kind of interference signal filter that comprises a schmitt trigger and three active filters of connecting has been described in No. 532.
Summary of the invention
Main purpose of the present invention is to provide a kind of effective and very feasible minimum pulse width detecting and lives again circuit.
Another object of the present invention is to provide a kind of circuit, but its detection signal pulse duration is whether in the scope between a minimum widith and a Breadth Maximum.
The present invention's another purpose is to provide a kind of circuit, when it surpasses minimum widith in the signal pulse duration, this pulse signal is passed through; And it is in the signal pulse duration during less than minimum widith, can be with this pulse signal filtering.
A further object of the present invention is to provide a kind of circuit, and it is when input pulse is in this scope, and the pulse duration of extensible signal pulse is to Breadth Maximum.
According to purpose of the present invention, provide a kind of minimum pulse width detecting and live again circuit.At first, this circuit comprises a pulse duration detector, and it can detect an input signal pulse whether in the scope between minimum widith and Breadth Maximum.Secondly, if the input signal pulse in this scope, the pulse duration stretcher can extend the input signal pulse duration to this Breadth Maximum.At last, if the input signal pulse less than minimum widith, disturbs the signal filter can the pulse of filtering input signal.
In addition, according to purpose of the present invention, provide a kind of minimum pulse width detecting and live again circuit.At first, this circuit comprises the breech lock that has setting, resets and export.This setting is coupled to an input signal.Secondly, one disturb the signal filter to have an input and an output.This input is coupled to this breech lock output.This input is delayed to produce one and postpones input.At last, a delay element has an input and an output.This Delay Element input is coupled to the input that this interference signal filter is postponed.This delay element output is coupled to this breech lock and resets.
As for detailed construction of the present invention, application principle, effect and effect, then the explanation of doing with reference to following accompanying drawing can be understood completely:
Description of drawings
Fig. 1 is that the address of note note body device is set up and the prior art example that keeps sequential;
Sequential is disturbed the prior art example of the generation of signal on Fig. 2;
Fig. 3 is the prior art circuit that sequential is disturbed the signal filtering;
Fig. 4 is the prior art circuit that extends the signal pulse length;
Fig. 5 is first preferred embodiment of the present invention;
Fig. 6 is second preferred embodiment of the present invention;
Fig. 7 to Fig. 9 is that second preferred embodiment of the present invention is respectively for T
Th≤ T
w≤ T
Ew, T
w＜T
ThWith T
w＞T
EwSequential performance figure etc. case;
Figure 10 is the 3rd preferred embodiment of the present invention;
Figure 11 to Figure 12 is that the 3rd preferred embodiment of the present invention is respectively for T
w〉=T
ThWith T
wSequential performance figure etc. case.
Embodiment
Preferred embodiment is the minimum pulse width detecting of the present invention and the circuit of living again.This minimum pulse width detecting is illustrated with three specific embodiments with the circuit of living again.Should be understood that for being familiar with this operator the present invention can be employed and extend within its spiritual scope.
See also Fig. 5, it is first preferred embodiment of the present invention.In Fig. 5, show some important features, such as the minimum pulse width detecting and the circuit of living again.At first, this circuit comprises a pulse duration detector 50, and it can detect the width T of an input signal pulse IN
wWhether at minimum widith T
ThWith Breadth Maximum T
EwBetween scope in.Input signal IN comprises, for example a memory address or such as controlling signal, document signal, controlling signal, a clock pulse signal or a pulse of address wire.
The critical T of minimum pulse width
ThIt is minimum time for the input signal pulse IN that is about to be defined by effective signal state.If burst length T
wLess than T
Th, disturb the signal filter 58 will this pulse of filtering so, make output OUT can not see state variation.Maximum pulse is extended time T
EwBe to be defined as the maximum time that pulse length is extended by pulse duration extension circuit 54.Therefore, if the input pulse time T
wMore than or equal to T
ThBut be less than or equal to T
Ew, pulse duration will be extended by pulse duration extension circuit 54 so, and by disturbing the signal filter to become output signal OUT, it has T
Ow=T
EwOutput pulse width.
If the input signal pulse is in the critical T of minimum pulse width
ThExtend time T with maximum pulse
EwBetween scope in, pulse duration extension circuit 54 can extend the input signal pulse width T
wTo Breadth Maximum T
EwIf input signal pulse width T
wLess than minimum widith T
Th, interference signal filter 58 can the pulse of filtering input signal.
Note that pulse duration detector 50 is to be key feature of the present invention.Unlike prior art, the invention is characterized in different in width T
wInput pulse between.Pulse extension or pulse bandwidth filtering are then selectively carried out.In this way, the invention provides detecting of a kind of pulse duration and the single solution of proofreading and correct, it eliminates the interference signal on the successive range of whole pulse duration.Owing to producing, the interference signal that filtering caused is eliminated less times greater than the filter delay place at input pulse.Be eliminated owing to extending the interference signal generation that is caused at the very little place of input pulse.
Consult Fig. 6, it is second preferred embodiment of the present invention.One specific embodiment more specifically below will be described.At this, flip-flop 64 is to be connected in the mode of the pulse duration detector among Fig. 5 50 with pulse duration stretcher 54 with delay circuit 68.Disturbing signal filter 72 is to be a resolution element, as shown in Figure 5, sees also Fig. 6 again, in conjunction with detector and stretcher partly comprise, at first, a breech lock or flip-flop 64, it has settings, replacement and exports.This setting is coupled to the input signal IN of circuit.Secondly, a delay element 68 has an input and an output.The input of this Delay Element is coupled to this breech lock output LAT.The output RESET of this delay element 68 is coupled to the replacement of this flip-flop 64.At last, one disturb signal filter 72 to have an input and an output.This interference signal filter input is coupled to this breech lock output LAT, and should disturb the output of signal filter to form circuit output OUT.
The operation of flip-flop 64 is to put in order in state table shown in Figure 6.If flip-flop is reset and is enabled, then the output LAT of flip-flop is output IN.Yet if flip-flop is reset by forbidden energy, flip-flop 64 is in output LAT place breech lock input IN position standard, to trigger breech lock as positive edge.
Consult Fig. 7 to Fig. 9, detect and the operation of the circuit of living again can fully be understood.Consult Fig. 7 especially, it is the pulse T of input signal IN
wHave between minimum value T
ThWith maximum extension width T
EwThe situation of width.The state variation of input signal IN from the low level to the high levels cause the output LAT of flip-flop 64 from the low level to the high levels, to change and in high levels by breech lock.The LAT signal is by disturbing signal filter 72 to be handled, and it is in the filter delay time T
ThAfter the OUT signal is converted to high levels from low level.Delay circuit 68 output RESET are at process T time of delay
dAfter, be converted to high levels from low level.Note that T
dBe substantially equal to T
EwIn case RESET becomes high levels (by forbidden energy), flip-flop is reset, and makes output LAT follow input IN once more, and it is low level at present.Disturb signal filter 72 then in the filter delay time T
ThThe LAT signal is passed through to OUT.
Consult Fig. 8, it is T
wLess than minimum critical T
ThThe situation of very little input pulse.Again, the LAT signal changes to high levels at input pulse IN from low level.Yet, because input pulse width T
wLess than disturbing signal filter delay time T
Th, output OUT can't change state.The RESET signal will be at T time of delay
dChange afterwards.
Consult Fig. 9, it is the pulse width T of input signal IN
wGreater than maximum extension width T
EwSituation.The state variation of input signal IN causes the state variation of output LAT signal.Yet, time of delay T
dBe exceeded.Although the RESET signal is activated, the LAT signal keeps high levels, because reset when only being carried out at breech lock and being eliminated.The output of flip-flop 64 is equal to the input shown in the state table of Fig. 6.Consult Fig. 9 once more, disturb output OUT reflection IN, the wherein T of signal filter 72
OwApproximate T greatly
wDisturb signal delay T and have
ThOffset.
The pulse detection that note that first specific embodiment is to be bipolarity with the general type of the circuit of living again, no matter make positive pulse or negative pulse all can by detecting with live again.Yet in the more specifically situation of the second and the 3rd specific embodiment, the negative pulse of living again (from high levels to low level) or positive pulse (from low level to high levels) are detected and made to circuit only.The example pulse of second specific embodiment that Fig. 7 is extremely shown in Figure 9 is the circuit function for the positive pulse on the input signal IN.This function can be by suitable conversion and the non-conversion and easily extend to negative pulse of input with output, as will further showing in the 3rd specific embodiment.
Consult Figure 10, it is the 3rd specific embodiment of the present invention.This specific embodiment is to be the more specifically version of pulse detection of the present invention with the circuit of living again.This circuit comprises a flip-flop 64 and delay circuit 68, and its combination is to provide pulse detection and extension function.Disturb signal filter 72 to be provided to filtering less than T
ThThe interference signal.
Flip-flop or breech lock 64 preferably comprise hands over coupling and not b gate 84 and 88.Replacedly, can be used such as other frameworks such as handing over coupling or lock.In this specific embodiment, pulse detection is to design at positive pulse with the circuit of living again.Therefore, input IN is anti-phase by 80 of inverters.In addition, disturb the output of signal filter 72 to comprise an inverter 108.If input inverter 80 is removed with output inverter 108, this circuit can be used in the detecting of negative pulse and live again.The replacement signal RESETB that note that the flip-flop 64 in present case starts for negative.The critical T of minimum pulse width
ThDetermined by setting flip-flop 64 required minimum pulse widths.This value can be changed by changing the plant bulk in the flip-flop 64.
Delay circuit comprises a string inverter 112,116,120,124,92,96 and 100 of coupling in regular turn between input signal LAT and the output signal RESETB.In this specific embodiment, the part of the delay path of LAT is shared in delay circuit 68 and is disturbed between the signal filter 72.Especially, LAT is shared with 124 between delay circuit 68 and interference signal filter 72 with the inverter 112,116,120 that the breech lock of delay is exported between the LAT D.Electric capacity 101 shown in delay circuit 68 more can comprise.The purpose of electric capacity is to provide the output of first inverter 92 of heavy load electric capacity in delay circuit 68, uses long relatively T time of delay of generation
dIn present case, electric capacity 101 comprises a mos device, and its gate is coupled to the signal path, and matrix, drain and source electrode are coupled to earth terminal 102.
Now see also Figure 11, it is input pulse width T
wGreater than critical value T
ThSituation.Because RESETB is by forbidden energy, input signal IN passes through to LAT.At T time of delay
dAfterwards, RESETB is enabled with the replacement breech lock.The OUT signal transmits the IN signal, but extends pulse duration to T
d
Now see also Figure 12, it is T
wLess than minimum critical T
ThThe situation of very small-pulse effect width.Flip-flop can't be set by burst pulse, and the change of the state of IN is transferred into LAT.Yet, because T
wLess than disturbing signal filter delay time T
Th, the state of output OUT can't change.
Advantage of the present invention can be done a summary at this.The invention provides a kind of effectively and the detecting of the minimum pulse width that can make with live again circuit, it provides a kind of circuit, but whether its detection signal pulse duration in the scope between minimum widith and Breadth Maximum.If the signal width surpasses minimum widith, this circuit can make this signal pulse pass through; If the signal width is less than minimum widith, but this signal pulse of this circuit filtering.If the signal width is in this scope, this circuit can extend the pulse duration of signal pulse to Breadth Maximum.
As described in above preferred embodiment, novel input disturb the signal detecting and the circuit of living again provide a kind of at prior art effectively and the replacement scheme that can make.
Therefore, the present invention has had the progressive on the industry, has the value of industry, and is utilization not seen before on the market at present.
But the above only is a preferred embodiment of the present invention, is not to be used for limiting scope of the present invention.Be that the equalization that all the present patent application claims are done changes and modification, be all the contained lid of claim of the present invention.
The figure number explanation:
10-and lock
14-disturbs signal
The 20-not b gate
The 24-phase inverter
The 28-Delay Element
Anti-or the lock of 32-
The 36-delay element
50-pulse width detector
54-pulse width extension circuit
58-disturbs the signal filter
The 64-flip-flop
The 68-delay circuit
72-disturbs the signal filter
The 80-inverter
The 84-and not b gate
The 88-and not b gate
The 92-inverter
The 96-inverter
The 100-inverter
101-electric capacity
The 102-earth terminal
The 104-and not b gate
The 108-inverter
The 112-inverter
The 116-inverter
The 120-inverter
The 124-inverter
Claims (20)
- Minimum pulse width detecting with live again circuit, comprising: a pulse duration detector, a pulse duration stretcher, disturb signal filter etc. to constitute; It is characterized in that: described pulse duration detector, it can detect a pulse input signal pulse whether in the scope between minimum widith and Breadth Maximum; Described pulse duration stretcher, if this input signal pulse in this scope, this pulse duration stretcher can extend this input signal pulse duration to this Breadth Maximum; Described interference signal filter, if this input signal pulse less than this minimum widith, this disturbs signal filter can this input signal pulse of filtering.
- 2. the minimum pulse width detecting as claimed in claim 1 and the circuit of living again, it is characterized in that: described pulse duration detector and this pulse duration stretcher comprise a single circuit, more include: a breech lock, it has setting, resets and output, and wherein this setting is coupled to this input signal; And a Delay Element, it has an input and an output, and wherein this input is coupled to this breech lock output, and wherein this output is coupled to this breech lock and resets.
- 3. the minimum pulse width detecting as claimed in claim 2 and the circuit of living again, it is characterized in that: described breech lock comprises one of following group: hand over the coupling and not b gate and hand over the anti-or lock of coupling.
- 4. as claim, the minimum pulse width detecting with live again circuit, it is characterized in that: described Delay Element comprises a string inverter of coupling in regular turn.
- 5. the minimum pulse width detecting as claimed in claim 4 and the circuit of living again is characterized in that: described Delay Element comprises that more one postpones electric capacity.
- 6. the minimum pulse width detecting as claimed in claim 1 and the circuit of living again, it is characterized in that: described interference signal filter comprises: an and not b gate, it has first and second input and an output, and wherein this first input is coupled to this input signal; And a string inverter of coupling in regular turn, it has an input and an output, and wherein this input is coupled to second input that this input signal and this output are coupled to this and not b gate.
- 7. the minimum pulse width detecting as claimed in claim 1 and the circuit of living again, it is characterized in that: described input signal comprises one of following group: address lines, document signal, controlling signal, time pulse signal and pulse signal.
- Minimum pulse width detecting with live again circuit, comprising: a pulse duration detector, a pulse duration stretcher etc. constitute; It is characterized in that: described pulse duration detector, it can detect a pulse input signal pulse whether in the scope between minimum widith and Breadth Maximum; Described pulse duration stretcher, if this input signal pulse is in this scope, this pulse duration stretcher can extend this input signal pulse duration to this Breadth Maximum, wherein this pulse duration detector and this pulse duration stretcher comprise a single circuit, it more comprises: a breech lock, it has setting, resets and output, and wherein this setting is coupled to this input signal; And a Delay Element, it has an input and an output, and wherein this input is coupled to this breech lock output, and wherein this output is coupled to this breech lock and resets; And one disturb the signal filter, if this input signal pulse less than this minimum widith, this disturbs signal filter can this input signal pulse of filtering.
- 9. the minimum pulse width detecting as claimed in claim 8 and the circuit of living again, it is characterized in that: described breech lock comprises one of following group: hand over the coupling and not b gate and hand over the anti-or lock of coupling.
- 10. the minimum pulse width detecting as claimed in claim 8 and the circuit of living again is characterized in that: described Delay Element comprises a string inverter of coupling in regular turn.
- 11. the minimum pulse width detecting as claimed in claim 10 and the circuit of living again is characterized in that: described Delay Element comprises that more one postpones electric capacity.
- 12. the minimum pulse width detecting as claimed in claim 8 and the circuit of living again, it is characterized in that: described interference signal filter comprises: an and not b gate, and it has first and second input and an output, and wherein this first input is coupled to this input signal; And a string inverter of coupling in regular turn, it has an input and an output, and wherein this input is coupled to second input that this input signal and this output are coupled to this and not b gate.
- 13. the minimum pulse width detecting as claimed in claim 8 and the circuit of living again, it is characterized in that: described input signal comprises one of following group: address lines, document signal, controlling signal, time pulse signal and pulse signal.
- A circuit 14. minimum pulse width is detected and lived again comprises: a breech lock, disturbs signal filter, a delay element etc. to constitute; It is characterized in that: described breech lock has setting, resets and output, and wherein this setting is coupled to an input signal; Described interference signal filter, it has an input and an output, and wherein this input is coupled to this breech lock output, and wherein this input is delayed to produce a delay input; Described Delay Element, it has an input and an output, and wherein this input is coupled to the input that this interference signal filter is postponed, and wherein this output is coupled to this breech lock replacement.
- 15. the minimum pulse width detecting as claimed in claim 14 and the circuit of living again, it is characterized in that: described breech lock comprises one of following group; Hand over the coupling and not b gate and hand over the anti-or lock of coupling.
- 16. the minimum pulse width detecting as claimed in claim 14 and the circuit of living again is characterized in that: described delay element comprises a string inverter of coupling in regular turn.
- 17. the minimum pulse width detecting as claimed in claim 16 and the circuit of living again is characterized in that: described delay element comprises that more one postpones electric capacity.
- 18. the minimum pulse width detecting as claimed in claim 14 and the circuit of living again, it is characterized in that: described interference signal filter comprises: an and not b gate, it has first and second input and an output, and wherein this first input is coupled to this breech lock output; And a string inverter of coupling in regular turn, it has an input and an output, and wherein this input is coupled to this breech lock output, and this output is coupled to second input of this and not b gate.
- 19. require 14 described minimum pulse width detectings and live again circuit as profit, it is characterized in that: described minimum pulse width comprises a negative pulse.
- 20. require 14 described minimum pulse width detectings and live again circuit as profit, it is characterized in that: described minimum pulse width comprises a positive pulse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03142981 CN1567719A (en) | 2003-06-13 | 2003-06-13 | Minimum pulse width detection and regeneration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03142981 CN1567719A (en) | 2003-06-13 | 2003-06-13 | Minimum pulse width detection and regeneration circuit |
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| Publication Number | Publication Date |
|---|---|
| CN1567719A true CN1567719A (en) | 2005-01-19 |
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ID=34471229
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|---|---|---|---|
| CN 03142981 Pending CN1567719A (en) | 2003-06-13 | 2003-06-13 | Minimum pulse width detection and regeneration circuit |
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|---|---|
| CN (1) | CN1567719A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115542035A (en) * | 2021-06-30 | 2022-12-30 | 纬颖科技服务股份有限公司 | Intrusion detection device and method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115542035A (en) * | 2021-06-30 | 2022-12-30 | 纬颖科技服务股份有限公司 | Intrusion detection device and method thereof |
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