CN1585312A - A method for converting an asynchronous clock domain into a synchronous clock domain - Google Patents

Abstract

The present invention provides a method for converting an asynchronous clock domain into a synchronous clock domain, directly using the synchronous clock to sample the asynchronous write address status signal in the asynchronous clock domain, and applying preset rules, at a specific read address position The read address in the synchronous clock domain is adjusted, so that the frame header alignment processing between different asynchronous data frames is realized while realizing the conversion of the asynchronous signal clock domain. The application of the present invention realizes simple structure and is easy to understand, avoids complex processing such as Gray code transformation, greatly simplifies the design process, and saves logic resources for realization.

Description

A method for converting an asynchronous clock domain into a synchronous clock domain

technical field

The present invention relates to the technical field of clock domain conversion, in particular to a method for converting an asynchronous clock domain into a synchronous clock domain.

Background technique

In the logical design of the interface chip, the signals that enter the internal processing of the chip from the interface are transmitted in the form of data frames, and are asynchronous signals relative to the main processing clock of the chip. Since there will be a certain phase difference or short-term frequency jitter between different clocks, in order to make the chip work stably, it is necessary to convert the asynchronous signal from the asynchronous clock domain to the synchronous clock domain to obtain a stable synchronous signal, and then perform Subsequent processing.

Because the frame headers between asynchronous signals are usually not aligned, and the interface chip needs to process signals with completely aligned frame headers, therefore, after the asynchronous signal completes the clock domain conversion, frame header alignment processing is required.

Taking the uplink primary and diversity signals in the Wideband Code Multiple Access (WCDMA) system as an example, the method for converting the asynchronous signal from the asynchronous clock domain to the synchronous clock domain and realizing frame header alignment is described in detail below.

Generally, the conversion of the asynchronous clock domain to the synchronous clock domain is usually realized by a method of caching data in a dual-port RAM. FIG. 1 is a structural diagram for realizing clock domain conversion of an asynchronous signal in the prior art. The asynchronous clock signal is used to generate the write address of the dual-port RAM, and the synchronous clock is used to generate the read address of the dual-port RAM. The depth of the dual-port RAM is determined according to the short-term frequency difference range that needs to be tolerated. Convert the read and write addresses into corresponding Gray codes, and then use the synchronous clock to sample and compare to determine whether the distance between the read and write addresses is less than the minimum distance that may cause read and write conflicts, that is, the "dangerous distance". , then jump the read address by 180 degrees, that is, jump the read address to the address farthest from the current position, and then execute the read operation; otherwise, do not need to adjust the read address, and directly execute the read operation. The data read out in this way is stable and correct, and the phase difference between the asynchronous clock and the local synchronous clock and the short-term frequency jitter are shielded.

The method of jumping 180 degrees of the above read address is: set the read address as r_add, and the RAM depth is a, when r_add>=a/2, and when the read and write addresses are less than the dangerous distance, the read address jumps to r_add-a/ 2; when r_add<a/2, and the read-write address is less than the dangerous distance, the read address jumps to r_add+a/2. For example, suppose the write address is 13, the read address is 11, the "dangerous distance" is set to 3, and the RAM depth is 16, since |13-11|<3, and 11>16/2=8, the read address needs to be adjusted to 11-16/2=3.

Generally, the alignment processing of two-way data frame headers is achieved by using a 2-level dual-port RAM. FIG. 2 is a structural diagram for realizing alignment of frame headers in the prior art taking the above row-master and diversity frame headers as an example. For the convenience of illustration, it is assumed that the frame length is 8, and the dual-port RAM depth is 16. To meet the requirements of frame header alignment, it is necessary to know the specific position of the frame header in the dual-port RAM. In order to facilitate the processing of frame header alignment, the depth of the dual-port RAM is usually an integer multiple of the frame length. For the main and diversity data, it has been converted to the synchronous clock domain at this time. Therefore, the main and diversity frame headers are respectively counted by modulo 2, and the corresponding address generation counter is set according to the frame header counting results. The specific setting The rules are as follows: when the frame header count value is 0 and the corresponding frame header arrives, set the corresponding address occurrence counter to 8; when the frame header count value is 1 and the corresponding frame header arrives, set the corresponding address occurrence counter to 0, and the process is set The value of the bit address generation counter is used as the write address of the corresponding dual-port RAM, so that the first data of each frame is at address 0 or address 8; the read address of the dual-port RAM is only generated by a modulo 16 counter. Similarly, the local synchronous frame header signal is counted modulo 2, and the read address counter is set according to the frame header counting result. The setting rule is the same as above, so that the first data of the local synchronous frame header is always from address 0 or Address 8 is read; the initial value of the write address counter is set to 0, and the initial state of the read address counter is set to 8, thereby ensuring that the read and write address distances have the largest difference at the beginning, and realize the processing of frame header alignment.

The disadvantage of the above method is that the clock domain conversion and frame header alignment processing need to be completed in two steps, and the data frame header alignment processing cannot be implemented at the same time as the clock domain conversion is completed. Moreover, the implementation is relatively complicated, difficult to understand and causes waste of resources.

Contents of the invention

In view of this, the object of the present invention is to provide a method for converting an asynchronous clock domain into a synchronous clock domain, and realize frame header alignment processing while completing the clock domain conversion.

For achieving the above object, technical scheme of the present invention is achieved in that way:

A method for converting an asynchronous clock domain into a synchronous clock domain, the method comprising the steps of:

a. Set each asynchronous signal in the asynchronous clock domain to correspond to an address generation counter, and the frame header signal of each asynchronous signal periodically sets the address generation counter corresponding to it, and the address generation counter that has been set is set The value is used as the write address of the dual-port RAM corresponding to each asynchronous signal, and the write address status indication signal of the dual-port RAM is set according to the write address of the dual-port RAM;

b. Sampling the asynchronous write address status indication signal with a synchronous clock to obtain a synchronous write address status indication signal;

c. The same number of address generation counters as in the asynchronous clock domain are set in the synchronous clock domain, and the frame header signal of each synchronous signal is periodically set to the address generation counter corresponding to it, and the value of the address generation counter is used as each The read address of the dual-port RAM corresponding to the synchronous signal determines the judging position of the read address according to the pre-set rules according to the synchronous write address state indication signal, and adjusts the read address accordingly.

Preferably, the periodic setting further includes the following steps:

Set the depth of the dual-port RAM as a to be a positive integer multiple t of the frame length K, and count the frame header modulo t;

When the frame header count value is less than the value of t minus 1, and when the frame header is encountered, the value of the address generation counter is set to the value of the frame header count value plus 1 multiplied by the frame length K; when the frame header count value is t minus 1 , and when a frame header is encountered, the value of the address generation counter is set to 0.

Preferably, setting the write address state indication signal of the dual-port RAM according to the write address of the dual-port RAM is: setting the write address state indication signal corresponding to the write address frame header signal to a high level, and the write address state indication signal The length of is greater than the length of the corresponding write address frame header signal.

Preferably, when the frame length of the asynchronous signal is greater than or equal to 4, the method for determining the judging position of the read address according to the preset rules described in step c is: the judging position of the read address is equal to n multiplied by the frame length K and then minus 1, And n is a natural number less than or equal to the dual-port RAM depth a divided by the frame length K;

The corresponding adjustment method for the read address described in step c is: judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L at the judging position of the read address, and if so, make the asynchronous The read address corresponding to the signal is equal to the read address minus the frame length K plus 1, otherwise the read address will not be adjusted.

Preferably, the preset danger distance L is less than half of the frame length.

Preferably, when the frame length of the asynchronous signal is less than 4,

The method for determining the judging position of the read address according to the preset rules described in step c is: the judging position of the read address is extracted with equal interval cK in n multiplied by the frame length K and then minus 1, and n is less than or equal to the dual-port RAM Depth a is divided by the natural number of frame length K;

The corresponding adjustment method for the read address described in step c is: judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L at the judging position of the read address, and if so, make the asynchronous The read address corresponding to the signal is equal to the read address minus the extraction interval cK plus 1, otherwise the read address is not adjusted.

Preferably, the preset risk distance L is less than half of the extraction interval value.

Preferably, there are two or more asynchronous signals in the asynchronous clock domain.

Applying the present invention directly uses the synchronous clock to sample the asynchronous write address state signal in the asynchronous clock domain, and applies preset rules to adjust the read address in the synchronous clock domain at a specific read address position, so that when the asynchronous signal is realized At the same time as the clock domain conversion, the frame header alignment processing between different asynchronous data frames is realized. The application of the present invention realizes simple structure and is easy to understand, avoids complex processing such as Gray code transformation, greatly simplifies the design process, and saves logic resources for realization.

Description of drawings

FIG. 1 is a structural diagram for realizing clock domain conversion of asynchronous signals in the prior art;

Fig. 2 is the structural diagram of realizing frame header alignment by taking WCDMA system uplink master and diversity frame headers as an example in the prior art;

Fig. 3 is the structural diagram of simultaneously realizing clock domain conversion and frame header alignment by taking WCDMA system uplink main and diversity frame headers as an example for applying the present invention;

Fig. 4 is a sequence relationship diagram for applying the present invention to write address judgment;

Fig. 5 is a schematic diagram of applying the synchronous clock of the present invention to the sampling of the asynchronous write address state indication signal;

Fig. 6 is the timing diagram after applying the read address adjustment of the present invention;

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

The idea of the present invention is: each asynchronous clock signal in the asynchronous clock domain corresponds to an address generation counter, and the frame header signal of each asynchronous signal performs periodic setting to its corresponding address generation counter, and the set The value of the counter is used as the write address of the dual-port RAM corresponding to each asynchronous signal, and the asynchronous write address status indication signal of the dual-port RAM is set according to the write address of the dual-port RAM; the asynchronous write address status indication signal is sampled with a synchronous clock , to obtain the synchronous write address status indication signal; the same number of address generation counters as in the asynchronous clock domain are set in the synchronous clock domain, and the frame header signal of each synchronous signal is periodically set to its corresponding address generation counter. The value is used as the read address of the corresponding dual-port RAM. According to the synchronous write address status indication signal, the judgment position of the read address is determined according to the preset rules, and the read address is adjusted accordingly.

The rule that the counter is periodically set according to the frame header signal is: set the RAM depth as a, the frame length as K, and a=tK, t is a positive integer, and the frame header is counted modulo t, when the frame header count value is m, m<t-1 and when a frame header is encountered, the value of the address generation counter is set to (m+1)K; when the frame header count value m is t-1 and a frame header is encountered, the count value The cycle counts, so the value of the address generation counter is set to 0.

The following takes the uplink main and diversity signals in the WCDMA system as an example to describe its implementation in detail. In the present embodiment, it is still set that the frame length is 8, the depth of the dual-port RAM is 16, and the minimum "dangerous distance" that read-write conflicts may occur is 3, then t=16/8=2, because in each RAM Only two frames are possible, therefore, the frame header count value m can only be 0 and 1.

FIG. 3 is a structural diagram for implementing clock domain conversion and frame header alignment in this embodiment. In the asynchronous clock domain, use the asynchronous clock to start two modulo 16 address generation counters (cnt16 301 and cnt16302), and perform modulo 2 counting on the main and diversity frame headers respectively, and periodically reset the corresponding address generation counters according to the frame header counting results Bit, the value of the set counter is used as the write address of the dual-port RAM connected to it; at the same time, the status of the write address status of the two dual-port RAMs is judged separately to obtain the write address status of the two dual-port RAMs respectively Indication signal; the synchronous clock samples the asynchronous write address status indication signal respectively, thus obtains the synchronous write address status indication signal; in the synchronous clock domain, the synchronous clock drives two modulo 16 address generation counters (cnt16 303 and cnt16 304), simultaneously Carry out modulo 2 counting on the local synchronous frame header, and set the corresponding address generation counter according to the frame header counting result. Indicates the signal, and adjusts the corresponding dual-port RAM read address according to the preset rules. The following is a detailed description of each step:

Firstly, the asynchronous clock domain uses the asynchronous clock to start two modulo 16 address generation counters cnt16301 and cnt16 302, and simultaneously performs modulo 2 counting on the main and diversity frame header signals, and generates the corresponding modulo 16 address respectively according to the frame header counting results The counter is periodically set, that is, when the frame header count value m is 0 (m<t-1) and the frame header arrives, the corresponding modulo 16 counter is set to (0+1)×8=8, when the frame header counts When the value m is 1 (m=n-1) and the frame header arrives, the corresponding modulo 16 counter is set to 0. The value of the counter after the period setting operation is used as the write address of the two dual-port RAMs, and the write address states of the two RAMs are respectively judged to obtain the write address state indication signals of the two dual-port RAMs respectively. As shown in Figure 4, since the frame length of the incoming two-way asynchronous signal is 8, and the modulus of the address generation counter is 16, the position where the frame header is written can only be at address 0 or address 8 of the dual-port RAM. Since each asynchronous signal is written twice, two write address state indication signals, namely write address state indication signal 1 (state_ind1) and write address state indication signal 2 (state_ind2) are used to represent the states of these two writes, state_ind1 Indicates that the write address is near the asynchronous data frame head of the second frame, and state_ind2 represents the state of the write address near the asynchronous data frame head of the first frame. In this embodiment, the write address is {6, 7, 8, 9 , 10}, state_ind1 is high level, and when the write address is {14, 15, 0, 1, 2}, state_ind2 is high level.

Secondly, the synchronous clock is used to sample the asynchronous write address status indication signal to obtain the synchronous write address status indication signal. FIG. 5 is a schematic diagram of sampling the asynchronous write address status indication signal by applying the synchronous clock of the present invention. Since the frame header signal representing the state of the asynchronous write address has 1 bit and lasts for a long time, the asynchronous write address state indication signal can be directly sampled by the synchronous clock. At the same time, since the signal in the asynchronous clock domain is sampled by the synchronous clock , so there will be a certain fuzzy state at the edge of the collected signal, that is, the shaded part in Figure 5, but because the fuzzy part only affects whether the read address is adjusted this time or the next time, and once the read address is adjusted , then this fuzzy part has no effect on the correct transformation of the data.

Finally, drive two modulo 16 address generation counters cnt16 303 and cnt16304 with a synchronous clock, and carry out modulo 2 counting to the local synchronous frame header signal at the same time, according to the counting result of the local synchronous frame header to its corresponding two modulo 16 The address generation counter performs periodic setting processing, that is, when the frame header count value m is 0 (m<n-1) and the frame header arrives, the corresponding modulo 16 counter is set to 8 ((m+1)×8), When the frame header count value m is 1 (m=n-1) and the frame header arrives, the corresponding modulo 16 counter is set to 0. The value of the counter after the setting operation is used as the read address of the dual-port RAM, and the read address of the dual-port RAM is adjusted according to the synchronous write address status indication signal. FIG. 6 is a timing diagram after the read address adjustment of the present invention is applied. Since each address generation counter in the synchronous clock domain corresponds to an address generation counter in the asynchronous clock domain, that is, each address generation counter in the synchronous clock domain corresponds to an asynchronous signal, the specific adjustment scheme is as follows:

Determine the judgment position of the read address. The specific determination method is to set n as a natural number less than or equal to the RAM depth a divided by the frame length K, where the RAM depth is an integer multiple of the frame length; the judgment position of the read address is n multiplied by the frame length Then subtract 1, that is, the judgment position of the read address is nK-1, and n<=a/K, n is a natural number.

At the judging position of the read address, judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L. The preset dangerous distance L needs to satisfy 2L<K, if |r_add-w_add|< =L, then make the read address equal to the read address minus the frame length K plus 1, that is, make r_add=r_add-K+1, otherwise the read address will not be adjusted.

In this embodiment, a=16, K=8, L=3, then n=2;

The judging position of the read address is 8-1=7, 2×8-1=15;

When the read address is 7, and |w_add-7|<=3, judge whether the synchronous write address state indicator signal 1 (sync_state_ind1) is high level, if yes, then adjust the read address corresponding to the asynchronous signal to r_add=7-8+1=0, otherwise the read address will not be adjusted;

When the read address is 15, and |w_add-15|<=3, judge whether the synchronous write address state indication signal 2 (sync_state_ind2) is high level, if so, adjust the read address to r_add=15-8+1 =8, otherwise the read address will not be adjusted.

After such adjustment, the data read from the RAM storing the main and diversity data realizes the process of aligning the frame headers of the main and diversity data while completing the clock domain conversion.

The formula in the above adjustment scheme is only applicable when the frame length is greater than or equal to 4. If the frame length is less than 4, the following methods are used to determine the judgment position of the read address and the adjustment position of the read address.

When determining the judgment position of the read address, set n to be a natural number less than or equal to the RAM depth a divided by the frame length K, wherein the RAM depth is an integer multiple of the frame length, and the judgment position of the read address is n multiplied by the frame length and then minus 1, That is, the judging position of the read address is nK-1, and n<=a/K, where n is a natural number. Since the frame length is short, the judgment position of the read address can be extracted from K-1, 2K-1, 3K-1...nK-1 at equal intervals cK, then the judgment position of the read address is cK-1, 2cK -1...rcK-1, (r<n).

At the judging position of the read address, judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L, and the preset dangerous distance L must satisfy 2L<ck, if |w_add-r_add|< =L, then make the read address corresponding to the asynchronous signal equal to the read address minus the value of the extraction interval cK plus 1, that is, make r_add=r_add-cK+1, otherwise the read address will not be adjusted.

For example, set a=16, K=2, then n=2, and set L=1, ck=4,

The judgment position of the read address can be 3, 7, 11, 15;

The positions where the read address may be adjusted are:

When |w_add-3|<=1, r_add=3-4+1=0;

When |w_add-7|<=1, r_add=7-4+1=4;

When |w_add-11|<=1, r_add=11-4+1=8;

When |w_add-15|<=1, r_add=15-4+1=12;

The present invention is not only applicable to the case of two asynchronous signals, but also applicable to the case of converting more than two asynchronous signals into the same clock domain and aligning their frame headers.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (8)

1. A method for converting an asynchronous clock domain into a synchronous clock domain, characterized in that the method comprises the following steps: a. Set each asynchronous signal in the asynchronous clock domain to correspond to an address generation counter, and the frame header signal of each asynchronous signal periodically sets the address generation counter corresponding to it, and the address generation counter that has been set is set The value is used as the write address of the dual-port RAM corresponding to each asynchronous signal, and the write address status indication signal of the dual-port RAM is set according to the write address of the dual-port RAM; b. Sampling the asynchronous write address status indication signal with a synchronous clock to obtain a synchronous write address status indication signal; c. The same number of address generation counters as in the asynchronous clock domain are set in the synchronous clock domain, and the frame header signal of each synchronous signal is periodically set to the address generation counter corresponding to it, and the value of the address generation counter is used as each The read address of the dual-port RAM corresponding to the synchronous signal determines the judging position of the read address according to the pre-set rules according to the synchronous write address state indication signal, and adjusts the read address accordingly. 2. The method according to claim 1, wherein the periodic setting further comprises the following steps: Set the depth of the dual-port RAM as a to be a positive integer multiple t of the frame length K, and count the frame header modulo t; When the frame header count value is less than the value of t minus 1, and when the frame header is encountered, the value of the address generation counter is set to the value of the frame header count value plus 1 multiplied by the frame length K; when the frame header count value is t minus 1 , and when a frame header is encountered, the value of the address generation counter is set to 0. 3. The method according to claim 1, characterized in that, setting the write address state indication signal of the dual-port RAM according to the write address of the dual-port RAM is: setting the write address state indication signal corresponding to the write address frame header signal is high level, and the length of the write address status indication signal is greater than the length of the corresponding write address frame header signal. 4. The method according to claim 1, wherein when the frame length of the asynchronous signal is greater than or equal to 4, the method for determining the judgment position of the read address according to the preset rules in step c is: the judgment position of the read address It is equal to n multiplied by the frame length K and then minus 1, and n is a natural number less than or equal to the dual-port RAM depth a divided by the frame length K; The corresponding adjustment method for the read address described in step c is: judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L at the judging position of the read address, and if so, make the asynchronous The read address corresponding to the signal is equal to the read address minus the frame length K plus 1, otherwise the read address will not be adjusted. 5. The method according to claim 4, characterized in that the preset danger distance L is less than half of the frame length. 6. The method according to claim 1, wherein when the frame length of the asynchronous signal is less than 4, The method for determining the judging position of the read address according to the preset rules described in step c is: the judging position of the read address is extracted with equal interval cK in n multiplied by the frame length K and then minus 1, and n is less than or equal to the dual-port RAM Depth a is divided by the natural number of frame length K; The corresponding adjustment method for the read address described in step c is: judge whether the distance between the read address r_add and the write address w_add is less than or equal to the preset dangerous distance L at the judging position of the read address, and if so, make the asynchronous The read address corresponding to the signal is equal to the read address minus the extraction interval cK plus 1, otherwise the read address is not adjusted. 7. The method according to claim 6, characterized in that the preset risk distance L is less than half of the extraction interval value. 8. The method according to claim 1, wherein there are two or more asynchronous signals in the asynchronous clock domain.

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