CN1564462A

CN1564462A - Voltage level shifter and continuous pulse generator

Info

Publication number: CN1564462A
Application number: CN 200410031858
Authority: CN
Inventors: 郭俊宏; 尤建盛
Original assignee: AU Optronics Corp
Current assignee: AUO Corp
Priority date: 2004-03-30
Filing date: 2004-03-30
Publication date: 2005-01-12
Anticipated expiration: 2024-03-30
Also published as: CN100417021C

Abstract

A voltage level conversion device includes a conversion unit and a control unit. The conversion unit outputs a third signal according to the levels of a first and a second signal which are inverted from each other. When the first signal is maintained at a first level, the control unit blocks a current path formed in the conversion unit.

Description

Voltage level conversion device and continuous impulse generator

Technical field

The present invention is relevant for a kind of voltage level conversion device, particularly relevant for the voltage level conversion device that is applicable to LCD, and the energy loss that is caused when being reduced in the voltage level of converted input signal.

Background technology

Fig. 1 is the structure chart of the known liquid crystal display system of expression.The conventional liquid crystal system comprises viewing area 10, gate drivers 11, data driver 12, level shifter 13 and time schedule controller 14.Wherein, level shifter 13 receptions are from a plurality of clock signals of time schedule controller 14.Because the level of clock signal is lower, causes correctly identification clock signal of aft-end assembly.In order to make aft-end assembly can correctly read clock signal, level shifter 13 improves the level of the clock signal that received.Then, the clock signal that is enhanced level is exported by level shifter 13, and driving grid driver 11 and data driver 12, with 10 display frames in the viewing area.

Generally speaking, the circuit kenel of level shifter can be divided into two kinds, as shown in Figures 2 and 3.In these two kinds of circuit typess, main difference is, the position difference of level shifter receiving inputted signal.As shown in Figure 2, the input signal Vin20 of level shifter 20 inputs to the grid of nmos pass transistor N20; And input signal XVin20 inputs to the grid of nmos pass transistor N21, and wherein input signal Vin20 and XVin20 are anti-phase each other.In addition, because level shifter 20 needs the long time switching signal level of cost,, generally more often use level shifter 30 in order to save time.

As shown in Figure 3, the input signal Vin30 of level shifter 30 inputs to the source electrode of nmos pass transistor N30; And input signal XVin30 inputs to the source electrode of nmos pass transistor N31, and wherein input signal Vin30 and XVin30 are anti-phase each other.In level shifter 30, the source electrode of PMOS transistor P30 and P31 connects and is coupled to power vd D30.Because the grid of nmos pass transistor N30 and N31 is coupled to the power vd D30 of high level, so nmos pass transistor N30 and N31 keep conducting state.When the input signal Vin30 that source electrode received of nmos pass transistor N30 maintains low level and input signal XVin30 and maintains high level, PMOS transistor P31 conducting, PMOS transistor P30 turn-offs.At this moment because the level of power vd D30 is unequal with the high level of input signal XVin30, so between the source electrode of the source electrode of PMOS transistor P31 and nmos pass transistor N31 formation one direct current current path.The formation of this current path increases the energy loss of system, also reduces the reliability of thin-film transistor in the viewing area 10.

Summary of the invention

In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of voltage level conversion device, is applicable to LCD, in order to solve the energy loss that is caused when the converted input signal of voltage level conversion device.

For realizing above-mentioned purpose, the present invention proposes a kind of voltage level conversion device (voltage levelshifter), comprises converting unit and control unit.To export one the 3rd signal, wherein, when first signal maintained first level, the electric current road was through being formed at described converting unit according to the level of anti-phase first and second signal each other for converting unit.Control unit couples described converting unit, when first signal maintains first level, in order to the blocking-up current path.

For realizing above-mentioned purpose, the present invention more proposes a kind of voltage level conversion device, comprises converting unit and control unit.Converting unit has a PMOS transistor, first nmos pass transistor, the 2nd PMOS transistor and second nmos pass transistor, and a PMOS transistor AND gate first nmos pass transistor is serially connected with mutually between first voltage source and the first node, the 2nd PMOS transistor AND gate second nmos pass transistor is serially connected with mutually between first voltage source and the Section Point, in addition, first and second node couples the grid of the 2nd PMOS and a PMOS respectively, and the grid of first nmos pass transistor and second nmos pass transistor couples first voltage source.

Control unit has first switch, second switch and at least one the 3rd switch.First output that first switch has first control end, couples the first input end of positive input and couple first node.First output that second switch has second control end, couples second input of reverse input end and couple Section Point.The 3rd output that the 3rd switch has the 3rd control end, couples the 3rd input of first voltage source and couple first and second node.

Wherein, first to the 3rd control end all couples initiating signal.When initiating signal is in first level, described first and second switch conduction, and the 3rd not conducting of switch, and first and second signal of the complementation that will be imported by forward and inverting input is delivered to first and second node, carries out voltage transitions by converting unit.When initiating signal is in second level, first and second not conducting of switch, and the 3rd switch conduction, and send described first and second node with the voltage of first voltage source, so that first be changed to after the 4th level by the 3rd level, no DC path takes place between itself and first voltage source.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail as follows:

Fig. 1 represents the structure chart of known liquid crystal display system.

Fig. 2 and Fig. 3 represent the known level shift unit.

Fig. 4 represents an example of operation of the voltage level conversion device of the embodiment of the invention.

Fig. 5 is illustrated in the known LCD, the calcspar of the pulse generator of gate drivers and level shifter (level shifter).

The sequential chart of Fig. 6 indicating impulse generator pulsing.

Fig. 7 represents another example of operation of the voltage level conversion device of the embodiment of the invention.

The time sequential routine figure of the voltage level conversion device of Fig. 8 presentation graphs 7.

Symbol description:

10～viewing area; 11～gate drivers; 12～data driver; 13～level shifter; 14～time schedule controller; 20,30～level shifter; 40～converting unit; 41～control unit; 50～pulse generator; 51～level shifter; 70～converting unit; 71～control unit; 72～initiating signal generating unit; 73～pulse generator; NO1, NO2～node; N20, N21, N30, N31, N40...N43～nmos pass transistor; P20, P21, P30, P31, P40...P43～PMOS transistor; P ₅₁... P _5N, P ₇₁... P _7M～pulse; SB30, SB40, VB70～initiating signal T30, T40～inverter; VDD20, VDD30, VDD40～voltage source; VDD20～voltage source; Vin20, Vin30, Vin40, Vin50, Vin70～input signal; XVin20, XVin30, XVin40, XVin50, XVin70～input signal; Vout20, Vout30, Vout40, Vout50～output signal;

Embodiment

Fig. 4 is an example of operation of the voltage level conversion device of the expression embodiment of the invention.The voltage level conversion device comprises converting unit 40 and control unit 41.Converting unit 40 has nmos pass transistor N40 and N41, PMOS transistor P40 and P41 and inverter T40.The grid of nmos pass transistor N40 is coupled to the power vd D40 with high level, and the source electrode of nmos pass transistor N40 couples node NO1.The grid of nmos pass transistor N41 is coupled to the power vd D40 with high level, and the source electrode of nmos pass transistor N41 couples node NO2.The grid of PMOS transistor P40 couples node NO2, and the source electrode of PMOS transistor P40 couples power vd D40, and the drain electrode of PMOS transistor P40 couples the drain electrode of nmos pass transistor N40.The grid of PMOS transistor P41 couples node NO1, and the source electrode of PMOS transistor P41 couples power vd D40, and the drain electrode of PMOS transistor P41 couples the drain electrode of nmos pass transistor N41.The input of inverter T40 couples the drain electrode of nmos pass transistor N41 and PMOS transistor P41.

Control unit 41 comprises nmos pass transistor N42 and N43 and PMOS transistor P42 and P43.The grid of nmos pass transistor N42 receives a starting signal SB40, and the drain electrode of nmos pass transistor N42 couples node NO1, and the source electrode receiving inputted signal Vin40 of nmos pass transistor N42.The grid of nmos pass transistor N43 receives initiating signal SB40, and the drain electrode of nmos pass transistor N43 couples node NO2, and the source electrode receiving inputted signal XVin40 of nmos pass transistor N43.The grid of PMOS transistor P42 receives initiating signal SB40, and the source electrode of PMOS transistor P42 couples node NO1, and the drain electrode of PMOS transistor P42 couples power vd D40.The grid of PMOS transistor P43 receives initiating signal SB40, and the source electrode of PMOS transistor P43 couples node NO2, and the drain electrode of PMOS transistor P43 couples power vd D40.Wherein, input signal Vin40 and input signal XVin40 are anti-phase each other.

When input signal Vin40 maintained high level, initiating signal SB40 was a high level, and PMOS transistor P42 and P43 turn-off, and nmos pass transistor N42 and N43 conducting.This moment, input signal Vin40 inputed to the source electrode of nmos pass transistor N40, and input signal XVin40 inputs to the source electrode of nmos pass transistor N41.In addition, PMOS transistor P40 is that conducting and PMOS transistor P41 are shutoff.Because the grid of nmos pass transistor N40 and N41 couples power vd D40, so nmos pass transistor N40 and N41 are maintained at conducting state.By above-mentioned transistorized operation as can be known, inverter T40 input is a low level.After the effect by inverter T40, inverter T40 exports the output signal VOUT40 of a high level.

When input signal Vin40 maintained high level, initiating signal SB40 was a high-voltage level, nmos pass transistor N42 and N43 conducting, and PMOS transistor P42 and P43 shutoff.Input signal Vin40 and XVin40 are sent to node NO1 and NO2 respectively, and carry out level conversion by converting unit 40, at last by inverter T40 output.

When input signal Vin40 maintained low level, initiating signal SB40 was a low level, PMOS transistor P42 and P43 conducting, and nmos pass transistor N42 and N43 shutoff.At this moment, the level of the source electrode of nmos pass transistor N40 and N41 is identical with the level value of power vd D40, is the magnitude of voltage of power vd D40.PMOS transistor P40 and P41 turn-off.By above-mentioned transistorized operation as can be known, the input of inverter T40 is a high level.After the effect by inverter T40, inverter T40 exports a low level output signal Vout40, to realize the effect of voltage level conversion.Maintain under the low level situation at input signal Vin40,, reduce the electric flux loss though nmos pass transistor N41 for continuing conducting, by the control of initiating signal SB40, turn-offs to have broken off the direct current path PMOS transistor P41.In addition, because the input end signal of inverter T40 is a high level, so the output signal Vout40 of converting unit 40 is a low level, and the level value of output signal Vout40 also does suitable adjustment by inverter 401, with the enforcement level shifter operation should be arranged.

The level change of the initiating signal in the embodiment of the invention can utilize a pulse generator to operate.Consult Fig. 5, in the gate drivers of known LCD, have pulse generator 50.When level shifter 51 was exported driving pulse to pulse generator 50 according to input signal Vin50, pulse generator 50 recurred a plurality of pulses.Fig. 6 is the sequential chart of indicating impulse generator 50 pulsings.When input signal Vin50 was high level, N pulse (P took place in pulse generator 50 beginnings in regular turn ₅₁To P _5N).N impulse duration input signal Vin50 maintains low level in generation, up to pulsing P _5NAfter, input signal Vin50 becomes high level pulse, with N pulse of drive-pulse generator 50 generations once more.

Fig. 7 is the example of another operation of the voltage level conversion device of the expression embodiment of the invention.This voltage level conversion device also comprises initiating signal generating unit 72 and pulse generator 73 except comprising converting unit 70 and control unit 71.Circuit structure in converting unit 70 and the control unit 71 as shown in Figure 4.First and M pulse that initiating signal generating unit 72 received pulse generators 73 are taken place.At input signal Vin70 is high level, and after the voltage transitions by converting unit 70 comes drive-pulse generator 73 that first pulses take place with output Vout70, input signal Vin70 becomes low level, and maintain low level, after M pulse took place, input signal Vin70 just reverted to high level.Therefore, initiating signal generating unit 72 is according to first and M pulse and can learn the level of Vin70, with the level of decision initiating signal VB70.

As shown in Figure 8, input signal Vin70 comes drive-pulse generator 73 that M pulse (P takes place with a high level pulse ₇₁To P _7M), when input signal Vin70 input, behind the drive-pulse generator 73, return back to low level at once.For initiating signal VB70, as pulse P ₇₁When being changed to low level by high level, initiating signal VB70 is changed to low level by high level, and maintains low level.As pulse P _7MWhen being changed to low level by high level, initiating signal VB70 is changed to high level by low level.

In sum, when input signal Vin70 was low level, initiating signal generating unit 72 was according to pulse P ₇₁Initiating signal VB70 with output low level.After control unit 71 received initiating signal VB70, it was operated as previously mentioned, to disconnect in known technology the direct current path that is taken place, and the loss of reduction electric flux when input signal maintains low level.On the other hand, when input signal Vin70 was high level, initiating signal generating unit 72 was with according to pulse P _7MInitiating signal VB70 with the output high level.After control unit 71 received initiating signal VB70, it was operated as previously mentioned, carried out general operation.

So, voltage level conversion device of the present invention utilizes when LCD, can utilize the pulse generator of gate drivers to learn the level of input signal, with the level of further change initiating signal.The energy loss that is caused when input signal is low level, the control by drive signal reduces.

In the embodiments of the invention, with pulse P ₇₁And P _7MFalling edge to trigger the change of initiating signal VB70.In practical application not as limit, also can pulse P ₇₁And P _7MRising edge to trigger the change of initiating signal VB70.73 pulsings of pulse generator are counted M, can be according to required and definite its value of system.

Initiating signal VB70 of the present invention can directly be provided by external circuit, and does not need to be taken place by initiating signal generating unit 72.In addition, initiating signal VB70 can directly take place providing to control unit 71 in initiating signal generating unit 72, and need be by pulse P ₇₁And P _7MInitiating signal VB70 takes place.

In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various changes and modification, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.

Claims

1. A voltage level conversion device, comprising:

a conversion unit, which outputs a third signal according to the levels of a first and second signal which are opposite to each other, wherein, when the first signal is maintained at a first level, a current path is formed in the conversion unit; and

A control unit, coupled to the conversion unit, is used to block the current path when the first signal is maintained at the first level.

2. The voltage level conversion device according to claim 1, wherein the control unit receives a start signal, and when the first signal is maintained at the first level, the control unit according to the start signal to block the current path.

3. The voltage level conversion device as claimed in claim 1, wherein the conversion unit has a plurality of transistors, and the first and second signals are provided to sources or drains of the two transistors.

4. The voltage level conversion device according to claim 1, further comprising a start signal generator for providing a start signal to the control unit, when the first signal is maintained at the first level, The control unit blocks the current path according to the start signal.

5. The voltage level shifting device of claim 1, further comprising:

a pulse generating unit, according to the third signal, a plurality of continuous pulses are generated each time, and the pulses that occur each time include a first pulse that occurs first and a final pulse that occurs last; and

A starting signal generator, coupled to the first and final pulses, when the first pulse signal changes from a second level to a third level, the starting signal generator outputs a fourth level together An activation signal is sent to the control unit, so that the control unit blocks the current path according to the activation signal.

6. The voltage level conversion device according to claim 5, wherein when the final pulse signal changes from the second level to the third level, the start signal generator outputs a fifth level the start signal to the control unit.

7. The voltage level shifting device according to claim 5, wherein when the first signal is at the sixth level, the pulse generating unit generates the pulse, wherein the first signal maintains The time at the first level is longer than the time at the sixth level.

8. The voltage level conversion device according to claim 1, wherein the first and second signals are directly input to the conversion unit.

9. The voltage level conversion device as claimed in claim 1, wherein the first and second signals are input to the conversion unit through the control unit.

10. A voltage level shifting device comprising:

A conversion unit, comprising: a first PMOS transistor and a first NMOS transistor connected in series between a first voltage source and a first node; and a second PMOS transistor and a second NMOS transistor connected to each other connected in series between the first voltage source and a second node, wherein the first and second nodes are respectively coupled to the gates of the second PMOS and the first PMOS, and the first NMOS transistor and the gate of the second NMOS transistor is coupled to the first voltage source; and

A control unit, comprising: a first switch having a first control terminal, a first input terminal coupled to a non-inverting input terminal, and a first output terminal coupled to the first node; a second switch having A second control terminal, a second input terminal coupled to an inverting input terminal, a second output terminal coupled to the second node; and, at least one third switch has a third control terminal, a third an input terminal coupled to the first voltage source, a third output terminal coupled to the first and second nodes;

Wherein, the first to third control terminals are all coupled to a start signal;

When the start signal is at a first level, the first and second switches are turned on, the third switch is not turned on, and a complementary first The first and second signals are sent to the first and second nodes, and the conversion unit performs voltage conversion;

When the start signal is at a second level, the first and second switches are not turned on, the third switch is turned on, and the voltage of the first voltage source is sent to the first and second switches. Two nodes, so that after the first signal changes from a third level to a fourth level, there is no direct current path between the positive or negative input terminal and the first voltage source.

11. The voltage level shifting device of claim 10, wherein the first and second switches are NMOS transistors, and the third switch is a PMOS transistor.

12. A continuous pulse generator, suitable for a liquid crystal display panel, comprising:

A voltage level conversion device has a positive input terminal coupled to a first signal, and an inverting input terminal coupled to a second signal, for converting the level of the first signal and outputting a start pulse signal ;

A pulse generator, coupled to the voltage level conversion device, is used to sequentially generate a first to an Nth continuous pulse signal according to the start pulse signal; and

A starting signal generating unit is used to output a starting signal, and is coupled to the first and Nth sequential pulse signals, when the first sequential pulse signal changes from a first level to a second level, the The starting signal generator drives the starting signal to change from a third level to a fourth level, and when the Nth sequential pulse signal changes from the first level to the second level, the The starting signal generator drives the starting signal to change from the fourth level to the third level;

Wherein, the voltage level conversion device includes:

A conversion unit, comprising: a first PMOS transistor and a first NMOS transistor connected in series between a first voltage source and a first node; and a second PMOS transistor and a second NMOS transistor connected to each other connected in series between the first voltage source and a second node, wherein the first and second nodes are respectively coupled to the gates of the second PMOS and the first PMOS, and the first NMOS the gates of the transistor and the second NMOS transistor are coupled to the first voltage source; and

A control unit, comprising: a first switch having a first control terminal, a first input terminal coupled to a positive input terminal, and a first output terminal coupled to the first node; a second switch having A second control terminal, a second input terminal coupled to an inverting input terminal, a second output terminal coupled to the second node; and, at least one third switch has a third control terminal, a third an input terminal coupled to the first voltage source, a third output terminal coupled to the first and second nodes;

Wherein, the first to third control terminals are all coupled to the start signal;

When the start signal is at the third level, the first and second switches are turned on, the third switch is not turned on, and the complementary one input from the positive and negative input terminals The first and second signals are sent to the first and second nodes, and the conversion unit performs voltage conversion;

When the start signal is at the fourth level, the first and second switches are not turned on, the third switch is turned on, and the voltage of the first voltage source is sent to the first and second switches. The second node, so that after the first sequential pulse signal changes from the first level to the second level, there is no direct current between the positive or negative input terminal and the first voltage source path happens.

13. The continuous pulse generator of claim 12, wherein the first and second switches are NMOS transistors, and the third switch is a PMOS transistor.

14. The continuous pulse generator according to claim 12, wherein the conversion unit further comprises an inverter coupled to the connection between the second PMOS transistor and the second NMOS transistor for outputting The start pulse signal.