1258723 14734pif.doc 九、發明說明： 【發明所屬之技術領域】 且特別是有關於 器電路。 本發明是有關於一種放大器電路， 種用於TFT-LCD系統之高迴轉率於 【先前技術】 液晶顯示器（LCD)是目前平板顯示中使 顯示器之-。液晶顯示器一般包括兩個基板”夜曰= 偏振片。其中’在兩個基板上’配置有用於產生二 個電極’而液晶層則填充在兩個基板之間。另外 器則配置在兩個基板的外表面。經由施加電壓在電=振 可以將液晶分子重新排列，以進而控制液晶顯示哭的真 度。此外’數個例如薄膜電晶體（TFTs)的開關元件係酉^ 置在基板上，以用來切換施加於電極上的電壓。 ，晶顯示器還包括源極驅動電路和閘極驅動電路等的 驅動單元，以及用來控制驅動單元的控制電路，以便通過 開關兀件對電極提供電壓。通常，控制器位於基板的外部， 而驅動電路則位於基板中或者外部。 圖1係緣示一種習知用於緩衝供給液晶顯示器之電壓 的輸出緩衝器之結構方塊圖。在圖i中，輸出緩衝器在此 做為N軌對軌(Rail-to-Rail)放大器102,已用來處理通過輸 出緩衝器之平行緩衝的N位元資料。儘管圖1所示的轨對 轨放大器1〇2具有很好的輸出迴轉率（Slew Rate)，但是還 存在彳艮多問題。諸如，減弱了大量的電流、以及耗費了魔 大的體積用於組裝源驅動元件 ，即大的印跡。 1258723 14734pif.doc 圖2係繪示另一種習知用於緩衝供給液晶顯示器之電 壓的輸出緩衝器之結構方塊圖，其用於嘗試改善圖1之元 件的性能。在圖2中，沒有採用如圖1所示的N軌對軌放 大器102’而採用了由多個放大電路202和一個控制器208 所組成的輸出緩衝器。每個放大電路202又包括··使用p 型電晶體（P型運算放大器）204的一位元運算放大器， 以及使用N型電晶體（N型運算放大器）206: —位元運 算放大器。 眾所周知，為了更好地避免液晶顯示器中之液晶材料 的品質衰退，由輸出緩衝器提供的信號應該在共壓 Vcx>m，如Vcom=l/2VDD上下振盪而不應該是固定不變 的。因此，P型運算放大器204係用來處理輸出緩衝器所 提供之振盪信號的正極，而N型運算放大器206則用來處 理振盪信號的負極，運算放大器204和運算放大器206的 輸出端係彼此相互耦接。控制器208控制運算放大器204 和運算放大器206係如下所述，即當p型運算放大器204 處於開啟狀態時，N型運算放大器206處於關閉；反之， 當N型運算放大器206處於開啟狀態時，p型運算放大器 204處於關閉狀態。 控制器208根據控制信號CTL-Η和控制信號CTL_L 來開啟/關閉運算放大器204和206。而由控制器208產生 的控制信號CTL-H和控制信號CTL-L則是依據時序控制 器（本圖中未畫出）產生的極性信號p〇L，以做為通過輸 出緩衝器之資料的極性表示。 1258723 14734pif.doc 圖3A-3F係依據習知技術所繪示之圖2的輪出緩衝器 之時序圖。其中，圖3A中的波形係表示例如由時序控^ 器所產生的輸出致能信號；圖3B中的波形則表示極性作 號POL ;圖3C和圖3D中的波形分別表示來自於控制^ 208的CTL-H信號（見圖2)和CTL_L信號（見圖了 圖3E中的波形（VH部分，見圖2)表示p型運算放大器 204的輸出信號；圖3F中的波形（VL部份，見;2): 示N型運算放大器206的輸出信號。 乂 由圖3C和3E可以看出，VH部分波形對應ctl-h信 號；同樣，由圖3D和3F可以看出，VL部分波形對應ctl_l 信號。但是該處的對應並不是十分的好：VH部分&形（見 圖3E)的上升時間較慢，如3〇2所示；而VL部份波^ 圖3F)的下降時間較慢，如304所示。 通常設計者*希望纟輸峡衝！I而造錢慢的上升/ :降時間，因為，例如，液晶顯示器上的動態圖像的混亂 度，、上升/下降時間的延遲長短成正比。因此，對於 電路—直是所希望 【發明内容】 本發明的目的就是在提供—種高轉換速度的放大電」 (例如用於TFT-LCD系統）。此放大電路包括 祕於運算放大器輸出端的上拉電晶體、運曾放° 器輸出端的下拉電晶體，以及一控制電路係用來；擇丨 1258723 14734pif.doc 地分別開啟上拉電晶體和下拉電晶體。 根據本發明的實施例，控制電路按以下所述之一來 擇性地分別開啟上拉電晶體和下拉電晶體 =的或小於輸出致能信號的週期。另外，控= 路运可以按以下所述之-來選擇性地分別上拉電= 體：小於極性信號週期的1/20 ;或小於輸出致 =麵_⑽。再者，糾f路也可轉以下所述之 擇性地分別開啟上拉電晶體和下拉電晶體：小於極 週_麵；或小於輸出致能錢職的1/100。 根據本發明的實施例，控制電路包括了 ：第— 电路，係用於產生第一單觸於俨轳五— x 啟_ 拉電晶體的開 才間，以及第―早觸發電路，係用來產生第二單觸 ==決打拉電晶體的開啟時間。其中，第—和第^ 一 ^就係依據輸出致能信號的函數來決定。而第 「早觸發電路均分別包括至少一個延遲單元，苴 相對於輪出致能訊號轉換之對應的單觸發信號之轉換。 本發明的實施例，運算放大器包括—個高端 =和-個低端放大子電路。其中，高端放大子電路呈 個個電晶體所組成的電壓，並聽具有至少二 。而低端放大子電路同樣也具有由數個電晶體所 、-'成的電壓_器，並且也具有至少一個電容器。 子電ifΓ的實施例，上拉電晶體係減於高端放大 ^路的輪出，町拉電晶體軸接於低端放大子電路的 1258723 14734pif.doc 液晶顯示器（LCD)裝置氺白扛7 板和數個耦接於液晶顯 :：個液晶顯示面 動元件又包括-個輸出緩衝器。轉動几件，而母個源驅 每—個輸出緩衝器都包括了：— # 運算放大器之輸出的上拉+日齅 π放大、耦接於 出端的下拉電晶於運算放大器之輸 和下拉電晶體的控制電路^紐地分制敬上拉電晶體 個上器裝置的控制電路可選擇性地分別開啟每 :上拉和下拉電晶體’其開啟時間如下之—：少於極性作 ;==2;或少於輸出致能信號的週期；少於細; 二：二於輸出致能信號週期的1/10;少於極性 。號週⑽1/2GG;或少於輸出致能信號週期的1/1〇〇。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易十重，下文特舉較佳實施例，並配合所附圖式， 明如下。 【實施方式】 ^在下文中，將結合附圖具體描述本發明的實施方案。 窝要說明的是，本發明的方案可以進行不同形式的改變； 本發明的範圍並不只限於實施方案所描述的部分。此處的 實施方案只是為了對熟習此技藝者更為完全地解釋本發 明。附圖的大小只是為了清楚起見作了相應的放大。其中， 全文中相似元件均用相似數字來表示。 在本發明之實施例之部分的表示’要有以下的認識。 印，在Ρ型運算放大器和Ν形運算放大器的輪出端增加一 1258723 14734pif.doc 個或多個上拉/下拉電晶體，可以明顯改善其上升/下 間。但是如果上拉/下拉電晶體的操作週期與運算放大器柏 同或近似相同’則電流會顯著地被輸出緩衝器所減弱。但 是反過來說，如果-個或多個上拉/下拉電晶體的操作週期 比運算放大ϋ短’财崎^提高上升/下降相且不奋 導致電流被輸出緩衝器大量的減弱。 一圖4係繪示依據本發明之一較佳實施例的一種液晶顯 示器系統=00的方塊圖。請參照圖4，液晶顯示器系統*⑻ 包括一個溥膜電晶體液晶顯示器（以下簡稱TFT丄)系 統404和用來向TFT-LCD系統404提供顯示資料的圖像控 制器402。在本實施例中，圖像控制器4〇2包括一信號感 測tl件406，可以將顯示資料發送給TFT_LCD系統4〇4中 詞1應之信號接收元件416。在此信號發送元件406和信號 接收元件416可以採用多種信號技術，例如低壓差分信號 CLVDS)傳輸。 °〜 根據圖4可以看出，丁FT_LCD系統1〇4還包括··時序 控制器408 (信號接收元件416是其一部分）、閘極驅動元 = 412、源極驅動元件414*TFT_LCD面板41〇。其中， 時序控制器408包括信號發送元件418。當處理好信號接 件416所接收的顯示資料後，時序控制器4〇8會通過 信號發送元件418將處理後的資料發送至源驅動元件414 和閘驅動元件412。信號發送元件418可以採用與信號發 j和接收元件406和418相同的信號技術，例如低壓差分 仏唬傳輸（LVDS)，或者也可以採用其他類型的技術，例 10 1258723 14734pif.doc 如為熟習此技藝者所熟知的減少漂移差動信號⑽叫傳 輸技術。 S 5係、、、㈢示其中一個圖4所给示的源驅動元件々Μ之 方塊圖。請合併參照圖5，其中每個源驅動元件414都包 括：N位元移位暫存器（SR) 5〇2、資料閃鎖器5〇4、數位 類，，換(DAC) 506 *輸出緩衝器、5〇8。上述元件通 吊疋豎接(Cascade)結構來連結，以便資料從時序控制器 408流向TFT-LCD面板4!〇按照以下次序進行：5〇2 ; 5〇4°: 506 ;以及508。其中，數位類比轉換器（DAC) 506可以 由電阻器、電容器或電阻器和電容器的組合而實現。 圖6係繪不依照本發明之一實施例的輸出緩衝器6㈧ 之方塊圖。請合併參照圖6，對於丁肌⑶系統來說，輸 出緩衝器6GG可以對應於與圖5中的輸出緩衝器5〇8。 ^圖6所不輸出緩衝器600包括··多個放大器電路6〇2、 第一控制器6G8以及第二控制器616。而每個放大器電路 6〇2又包括：第-運算放大器_、第二運算放大器6〇6、 至夕一個上拉電晶體612和一個下拉電晶體61〇。在本實 施例中，—第—運算放大器6 G 4可以為由p型電晶體所組成 之^位兀（其中N為正整數）運算放大器，而第二運算放 大器606可以為由N型電晶體所組成之N位元（其中n 為正2數）運异放大器。舉例說明，每個N位運算放大器 都是=個具有圖10A和10B所示之電壓隨耦器結構的一位 元運^放大器。在較佳的情況下，上拉電晶體612可以採 用與第一運算放大器604相同類型的電晶體，例如p型電 I25872|,doc 晶體’其目的在於能與第一運算放大器604有更好的相容 性；同樣，下拉電晶體610也可以採用與第二運算放大器 606相同類型的電晶體5例如N型電晶體，其目的在於能 與第二運算放大器606有更好的相容性。 圖6所示之第一控制器608分別為第一運算放大器 604和第二運算放大器606產生控制信號CTL-H和 CTL-L。其中，第一運算放大器6〇4係用來處理振盪輸入 信號（來自數位類比轉換器如DAC 506的接收信號）的正 極，而第二運算放大器606則用來處理振盪輸入信號（來 自數位類比轉換器如DAC 506的接收信號）的負極。同 樣’第一運算放大器604和第二運算放大器606係彼此相 互耦接，以提供缓衝器600的輸出。 第一控制器608係按照以下方式來控制（或啟動）第一 運算放大器604和第二運算放大器606 :當第一運算放大 器604處於開啟狀態時，第二運算放大器6〇6就關閉；反 之亦然。同樣地，第一控制器608按照以下方式關閉或開 啟（啟動）第一運算放大器6〇4和第二運算放大器6〇6 : 經由控制化號CTL-H來控制第一運算放大器6〇4,而經由 控制信號CTL-L來控制第二運算放大器606。第一控制器 608係依據極性信號p0L (用來指示通過輸出緩衝器6〇〇 之貧料的極性，由圖4之時序控制器408所產生），而產生 控制信號CTL-H和CTL-L。 第一運算放大器604和第二運算放大器6〇6除了輸出 端相互連接在一起外，其輸出端還：透過上拉電晶體612 12 1258723 14734pif.doc 與系統源電壓如VDD相接 系統接地電壓如VSS相接。&下拉私曰曰體⑽與 上把二控制器616係分別透過控制信號HPU(半 ° 半下拉）’來控制上拉電晶體012和下拉電晶 給予具體深人的探討。由於上減晶二 一口^电日日體61㈣操作週期比第—運算放大器604和第 a二放大J 606的週期短，因此在使得輸出緩衝器刪 不會消耗大量的電流的情況下，顯著改善了上升/下_1258723 14734pif.doc IX. Description of the invention: [Technical field to which the invention pertains] and in particular related to the circuit. The present invention relates to an amplifier circuit for high slew rate in a TFT-LCD system. [Prior Art] A liquid crystal display (LCD) is currently used in flat panel displays. The liquid crystal display generally includes two substrates "Night 曰 = polarizer. Among them, 'on two substrates' is configured to generate two electrodes' and the liquid crystal layer is filled between two substrates. The other device is disposed on two substrates. The outer surface of the liquid crystal molecules can be rearranged by applying a voltage in the electric vibration to further control the truth of the liquid crystal display crying. Further, a plurality of switching element systems such as thin film transistors (TFTs) are disposed on the substrate. In order to switch the voltage applied to the electrodes, the crystal display further includes a driving unit such as a source driving circuit and a gate driving circuit, and a control circuit for controlling the driving unit to supply a voltage to the electrodes through the switching element. Usually, the controller is located outside the substrate, and the driving circuit is located in or outside the substrate. Figure 1 is a block diagram showing the structure of an output buffer for buffering the voltage supplied to the liquid crystal display. In Figure i, the output The buffer is here a N-track-to-rail amplifier 102 that has been used to process the parallel buffered N-bit data through the output buffer. The rail-to-rail amplifier 1〇2 shown in 1 has a good output slew rate, but there are still many problems, such as a large amount of current is attenuated, and a large volume is used for assembling the source. Driving element, i.e., large footprint. 1258723 14734pif.doc Figure 2 is a block diagram showing another conventional output buffer for buffering the voltage supplied to the liquid crystal display for attempting to improve the performance of the elements of Figure 1. In Fig. 2, an N-track-to-rail amplifier 102' as shown in Fig. 1 is employed instead of an output buffer composed of a plurality of amplifying circuits 202 and a controller 208. Each amplifying circuit 202 includes A one-bit operational amplifier using a p-type transistor (P-type operational amplifier) 204, and an N-type transistor (N-type operational amplifier) 206: a bit operational amplifier. It is well known that in order to better avoid the liquid crystal display The quality of the liquid crystal material is degraded, and the signal supplied from the output buffer should oscillate above and below the common voltage Vcx > m, such as Vcom = l/2VDD, and should not be fixed. Therefore, the P-type operational amplifier 20 4 is used to process the positive pole of the oscillating signal provided by the output buffer, and the N-type operational amplifier 206 is used to process the negative pole of the oscillating signal, and the outputs of the operational amplifier 204 and the operational amplifier 206 are coupled to each other. Control operational amplifier 204 and operational amplifier 206 are as follows, that is, when p-type operational amplifier 204 is in an on state, N-type operational amplifier 206 is off; conversely, when N-type operational amplifier 206 is on, p-type operational amplifier 204 is in a closed state. The controller 208 turns on/off the operational amplifiers 204 and 206 in accordance with the control signal CTL-Η and the control signal CTL_L. The control signal CTL-H and the control signal CTL-L generated by the controller 208 are based on the polarity signal p〇L generated by the timing controller (not shown in the figure) as the data passing through the output buffer. Polarity is indicated. 1258723 14734pif.doc Figures 3A-3F are timing diagrams of the wheel-out buffer of Figure 2, as depicted in the prior art. Wherein, the waveform in FIG. 3A represents an output enable signal generated by, for example, a timing controller; the waveform in FIG. 3B represents a polarity number POL; and the waveforms in FIGS. 3C and 3D respectively represent control 208 The CTL-H signal (see Figure 2) and the CTL_L signal (see the waveform in Figure 3E (VH part, see Figure 2) represent the output signal of the p-type operational amplifier 204; the waveform in Figure 3F (VL part, See 2;: shows the output signal of the N-type operational amplifier 206. As can be seen from Figures 3C and 3E, the VH partial waveform corresponds to the ctl-h signal; likewise, as can be seen from Figures 3D and 3F, the VL partial waveform corresponds to ctl_l Signal, but the correspondence is not very good: the VH part & shape (see Figure 3E) has a slower rise time, as shown by 3〇2; and the VL part of the wave ^ Figure 3F) has a slower fall time. As shown in 304. Usually the designer * hopes to lose the gorge! I make a slow increase in money / : fall time, because, for example, the degree of chaos of moving images on the liquid crystal display, and the length of delay of the rise/fall time are proportional. Therefore, it is straightforward for the circuit. [ SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed conversion power (for example, for a TFT-LCD system). The amplifying circuit comprises a pull-up transistor secreted at the output end of the operational amplifier, a pull-down transistor for outputting the output of the amplifier, and a control circuit system; respectively, the pull-up transistor and the pull-down are respectively turned on by 1258723 14734pif.doc Crystal. In accordance with an embodiment of the present invention, the control circuit selectively turns on the periods of the pull-up transistor and the pull-down transistor = or less than the output enable signal, respectively, in one of the following ways. In addition, the control = road can be selectively pulled up separately as follows - body: less than 1/20 of the polarity signal period; or less than the output = face _ (10). Furthermore, the correction circuit can also selectively open the pull-up transistor and the pull-down transistor respectively as described below: less than the pole circumference _ plane; or less than 1/100 of the output enablement position. According to an embodiment of the invention, the control circuit comprises: a first circuit for generating a first one-touch 俨轳 five-x _ pull-up crystal opening, and a first-earth trigger circuit for The second one-touch is generated == the opening time of the pull-on transistor. Among them, the first and the first ^ are determined according to the function of the output enable signal. The first "early trigger circuit" respectively includes at least one delay unit, and the conversion of the corresponding one-shot signal with respect to the turn-off enable signal conversion. In the embodiment of the present invention, the operational amplifier includes a high-end = and - low-end The amplifying sub-circuit, wherein the high-end amplifying sub-circuit has a voltage composed of a plurality of transistors, and has at least two, and the low-end amplifying sub-circuit also has a voltage _ device formed by a plurality of transistors. And also has at least one capacitor. The embodiment of the sub-electrical Γ, the pull-up electro-crystal system is reduced by the rotation of the high-end amplification circuit, and the pull-pull transistor is connected to the low-end amplifying sub-circuit 1258723 14734pif.doc liquid crystal display (LCD The device is divided into 7 plates and several are coupled to the liquid crystal display: the liquid crystal display surface moving component further includes an output buffer. Several pieces are rotated, and the parent source drives each of the output buffers include: — #的放大器的放大器的拉拉+日齅π amplification, the pull-down transistor coupled to the output terminal is connected to the op amp's input and pull-down transistor control circuit ^纽地分制敬拉电晶上器装置The control circuit can selectively turn on each of: pull-up and pull-down transistors respectively, whose turn-on time is as follows: less than polarity; ==2; or less than the period of the output enable signal; less than fine; 1/10 of the period of the output enable signal; less than the polarity. Number of weeks (10) 1/2 GG; or less than 1/1 of the period of the output enable signal. To make the above and other objects, features and advantages of the present invention The embodiments of the present invention will be specifically described below with reference to the accompanying drawings. [Embodiment] In the following, embodiments of the present invention will be specifically described with reference to the accompanying drawings. The present invention can be modified in various forms; the scope of the present invention is not limited to the embodiments described in the embodiments. The embodiments herein are only to explain the present invention more fully to those skilled in the art. For the sake of clarity, the corresponding elements are denoted by the same numerals. The representations in the parts of the embodiments of the present invention have the following recognitions: printing, in-line operational amplifiers and Ν Adding a 1258723, 14734pif.doc or more pull-up/pull-down transistors to the op amp's wheel-out can significantly improve its rise/fall, but if the pull-up/pull-down transistor operates with the op amp or approximation The same 'then current will be significantly reduced by the output buffer. But conversely, if the operating period of one or more pull-up/pull-down transistors is shorter than the operational amplification, 'Caiqi^ increases the rise/fall phase and does not The current is greatly reduced by the output buffer. Figure 4 is a block diagram of a liquid crystal display system = 00 according to a preferred embodiment of the present invention. Referring to Figure 4, the liquid crystal display system * (8) includes a A film transistor liquid crystal display (hereinafter referred to as TFT) system 404 and an image controller 402 for providing display material to the TFT-LCD system 404. In the present embodiment, the image controller 〇2 includes a signal sensing component 406 which can transmit the display data to the signal receiving component 416 of the word 1 in the TFT_LCD system 4〇4. Here, signal transmitting component 406 and signal receiving component 416 can be transmitted using a variety of signal techniques, such as low voltage differential signaling (CLVDS). °~ As can be seen from Fig. 4, the FT_LCD system 1〇4 further includes a timing controller 408 (signal receiving element 416 is a part thereof), a gate driving element = 412, a source driving element 414*TFT_LCD panel 41〇 . The timing controller 408 includes a signal transmitting component 418. When the display data received by the signal connector 416 is processed, the timing controller 4〇8 sends the processed data to the source drive element 414 and the gate drive element 412 via the signal transmitting component 418. Signaling component 418 can employ the same signal techniques as signalling j and receiving components 406 and 418, such as low voltage differential chirped transmission (LVDS), or other types of techniques can also be used, as is well known in Example 10 1258723 14734pif.doc. The drift-reducing differential signal (10), which is well known to the skilled artisan, is called transmission technology. The S 5 series, (3), and (3) show a block diagram of one of the source driving elements 图 shown in FIG. Referring to FIG. 5 in combination, each of the source driving elements 414 includes: an N-bit shift register (SR) 5〇2, a data flash locker 5〇4, a digital class, and a (DAC) 506* output. Buffer, 5〇8. The above components are connected by a cascade structure so that data flows from the timing controller 408 to the TFT-LCD panel 4! 〇 in the following order: 5〇2; 5〇4°: 506; and 508. Among them, the digital analog converter (DAC) 506 can be realized by a resistor, a capacitor or a combination of a resistor and a capacitor. Figure 6 is a block diagram of an output buffer 6 (eight) not in accordance with one embodiment of the present invention. Referring collectively to Figure 6, for a butadiene (3) system, the output buffer 6GG may correspond to the output buffer 5A8 of Figure 5. The output buffer 600 of FIG. 6 includes a plurality of amplifier circuits 〇2, a first controller 6G8, and a second controller 616. Each of the amplifier circuits 6〇2 further includes: a first operational amplifier _, a second operational amplifier 6〇6, a pull-up transistor 612 and a pull-down transistor 61〇. In this embodiment, the first operational amplifier 6 G 4 may be an operational amplifier composed of a p-type transistor (where N is a positive integer), and the second operational amplifier 606 may be an N-type transistor. The N-bits (where n is a positive 2) are transported to the amplifier. For example, each of the N-bit operational amplifiers is a one-bit amplifier with the voltage follower structure shown in Figs. 10A and 10B. In a preferred case, the pull-up transistor 612 can be of the same type as the first operational amplifier 604, such as a p-type I25872|, doc crystal, which is intended to be better than the first operational amplifier 604. Compatibility; likewise, the pull-down transistor 610 can also employ the same type of transistor 5 as the second operational amplifier 606, such as an N-type transistor, for the purpose of better compatibility with the second operational amplifier 606. The first controller 608 shown in FIG. 6 generates control signals CTL-H and CTL-L for the first operational amplifier 604 and the second operational amplifier 606, respectively. Wherein, the first operational amplifier 6〇4 is used to process the positive pole of the oscillating input signal (the received signal from the digital analog converter such as the DAC 506), and the second operational amplifier 606 is used to process the oscillating input signal (from the digital analog conversion The negative terminal of the receiving signal such as the DAC 506. Similarly, the first operational amplifier 604 and the second operational amplifier 606 are coupled to each other to provide an output of the buffer 600. The first controller 608 controls (or starts) the first operational amplifier 604 and the second operational amplifier 606 in the following manner: when the first operational amplifier 604 is in an on state, the second operational amplifier 6〇6 is turned off; Of course. Similarly, the first controller 608 turns off or turns on (starts) the first operational amplifier 6〇4 and the second operational amplifier 6〇6 in the following manner: controlling the first operational amplifier 6〇4 via the control number CTL-H, The second operational amplifier 606 is controlled via the control signal CTL-L. The first controller 608 generates control signals CTL-H and CTL-L based on the polarity signal p0L (used to indicate the polarity of the lean material through the output buffer 6, generated by the timing controller 408 of FIG. 4). . The first operational amplifier 604 and the second operational amplifier 6〇6 are connected to each other except for the output terminals, and the output terminal thereof is connected to the system source voltage such as VDD through the pull-up transistor 612 12 1258723 14734pif.doc. VSS is connected. The & pull-down private body (10) and the upper controller 616 are controlled by the control signal HPU (half-half-half pull-down) to control the pull-up transistor 012 and the pull-down transistor to give a concrete discussion. Since the upper and lower dimming circuit 61 (four) operation cycle is shorter than the period of the first operational amplifier 604 and the a second amplification J 606, it is remarkable in the case where the output buffer is not consumed by a large amount of current. Improved up/down_
間。其中’上拉電晶體612和下拉電晶體61〇分別透過第 二控制器616所產生的控制信號Hpu和HpD而運作。 圖7係、％示依照本發明之一較佳實施例的一種圖6之 第二控制器616的方塊圖。 圖6所不之第二控制器616包括單觸發高端電路7〇2 和單觸發低端電路704，係依據輸出致能信號〇E (其由圖 4所不之時序控制器408所產生），而分別產生控制信號 HPU 和 HPD。between. The pull-up transistor 612 and the pull-down transistor 61 are operated by the control signals Hpu and HpD generated by the second controller 616, respectively. Figure 7 is a block diagram of a second controller 616 of Figure 6 in accordance with a preferred embodiment of the present invention. The second controller 616 shown in FIG. 6 includes a one-shot high-side circuit 7〇2 and a one-shot low-end circuit 704 according to an output enable signal 〇E (which is generated by the timing controller 408 of FIG. 4). The control signals HPU and HPD are generated separately.
圖8A係繪示依照本發明之一較佳實施例的一種圖7 所示之單觸發而端電路702的方塊圖。請參照圖8A，單觸 發咼端電路702包括：多個非反相（或緩衝）運算放大器 802 (例如，本實施例中總共採用了四個）、一個反相器8〇4 以及一個或閘806。緩衝運算放大器8〇2係疊接在輸出致 能信號OE和轉換器804之間。反相器8〇4的輸出係耦接 在或閘806的其中一個輸入端，而或閘的另一個輸入端係 直接接收輸出致能信號OE。在實際操作中，單觸發高端 13 1258723 14734pif.doc 電路702延遲了上拉電晶體612 (圖6所示）的操作起始 時間（相對於第-運异放大器6〇4操作起始時間來說），然 後再使上拉電晶體612的操作週期比p型運曾 的週期相對較短。 °° 圖8B係!會示依照本發明之一較佳實施例的一種圖7 所不之單觸發低端電路綱的方塊圖。請參照圖8β， 發低端電路電路704包括：多個非反相（或緩衝）運算放 大器808(例如，本實施例中總共採用了四個）、反相器_ ，及及閘812 °緩衝運异放大器8〇8係疊接於輸出致能信 Ϊ二tit “Ο之間。反相器810的輸出端係耦接‘ 及，806的其中一個輸入端，而及閘812的另一個輪入端 則是直接接收輸出致能信號⑽。在實際操作巾，單觸發 7二4會延遲下拉電晶體610 (圖6所示）的猶 (相對於第二運算放大器606操作起始時間來 況）：後再使上拉電晶體610的操作週期比第二運算放大 器606的週期相對較短。 在下文中我們將提供有關上拉電晶體6 體時間/週期的具體資料。首先，假設極性信號 ^作週期，8〇微秒。其次，第—運算放大器_ 此，、軍：:二而第一運算放大器606在負極區工作。如 异大器604和606的開啟時間大約為4〇微秒，而 :晶ί 612和下拉電晶體610在當極性信號P0L從正 °:極或攸負極轉換到正極後的大約5微秒時開 ，这也就是延遲時間。另外，每個上拉電晶體M2和下 14 1258723FIG. 8A is a block diagram of a one-shot terminal circuit 702 of FIG. 7 in accordance with a preferred embodiment of the present invention. Referring to FIG. 8A, the one-shot terminal circuit 702 includes a plurality of non-inverting (or buffer) operational amplifiers 802 (for example, four are used in total in this embodiment), one inverter 8〇4, and one or a gate. 806. The buffered operational amplifier 8〇2 is cascading between the output enable signal OE and the converter 804. The output of the inverter 8〇4 is coupled to one of the inputs of the OR gate 806, and the other input of the OR gate directly receives the output enable signal OE. In actual operation, the one-shot high-end 13 1258723 14734pif.doc circuit 702 delays the operation start time of the pull-up transistor 612 (shown in Figure 6) (relative to the start-time of the first-transistor amplifier 6〇4 operation) Then, the operating period of the pull-up transistor 612 is made relatively shorter than the period of the p-type. FIG. 8B is a block diagram showing a one-shot low-end circuit diagram of FIG. 7 in accordance with a preferred embodiment of the present invention. Referring to FIG. 8β, the low-end circuit circuit 704 includes a plurality of non-inverting (or buffer) operational amplifiers 808 (for example, four are used in total in this embodiment), an inverter _, and a gate 812 ° buffer. The different amplifiers 8 〇 8 are connected to the output enable signal t two tap “Ο. The output of the inverter 810 is coupled to one of the inputs 806 and the other of the gates 812 The input terminal directly receives the output enable signal (10). In the actual operation towel, the one-shot 7 2 4 delays the pull-down transistor 610 (shown in FIG. 6) (in relation to the second operational amplifier 606 operation start time). ): The operation period of the pull-up transistor 610 is later made shorter than the period of the second operational amplifier 606. In the following, we will provide specific information on the time/period of the pull-up transistor 6. First, assume the polarity signal ^ The cycle, 8 〇 microseconds. Secondly, the first operational amplifier _ this, the military:: two and the first operational amplifier 606 operates in the negative region. If the alien 604 and 606 are turned on for about 4 microseconds, And: Crystal 612 and pull-down transistor 610 are in the polarity letter P0L from n °: Yau negative pole changeover or approximately 5 microseconds after the positive electrode, which is the delay time Further, the pull transistor M2 each of the upper and lower 141,258,723.
熟習此技藝者當知， 〇·1微秒，然後關閉直至 延遲時間和週期都可以祐且也應Those skilled in the art know that 〇·1 microsecond, then turn off until the delay time and period can be
的選擇一般從經濟效應出發， W、J硬境的變動。週期 即減少回饋。因為週期的增 加而導致迴轉率的提高能·消輸出緩衝器_所消耗之 電流的增加。 上拉電晶體612和下拉電晶體61〇在下列的週期内均 處於開啟狀態：少於極性信號roL週期的約⑽，或少於 輸出致能信號0E週期的約1/1〇 ;也可選擇性地為少於極 性信號POL週期的、約1/2〇〇，或少於輸出致能信號〇e週 期的約1/100。 圖9A-9H係繪示依照本發明之一較佳實施例的圖6所 示之輸出緩衝器600的時序圖。圖9A為例如由時序控制 器408 (如圖4所示）所產生之輸出致能信號〇E的波形 圖。圖9B為極性信號POL的波形圖。圖9C和圖9D分別 為來自於控制器608 (如圖6所示）之控制信號CTL-Η和 CTL_L的波形圖。圖9E為控制信號HPU的波形圖。圖9F 為才工制k號HPD的波形圖。圖9G為第一運算放大器604 (如上拉電晶體612根據控制信號HPU上拉而產生的信 號）輸出信號波形圖（VH部分）；圖9H為第二運算放大 器606 (如下拉電晶體610根據控制信號HPU下拉而產生 的信號）輪出信號波形圖（VL部分）。 由圖9C和圖9G可以看出，VH部分的波形圖對應於 15 1258723 14734pif.doc h號CTL_H。同樣，由圖9D和圖9H可以看出，VL部分 的波形圖對應於信號CTL-L。但是與傳統技術相比，其對 應效果更好。如數字902所指示之處，vh部分的波形圖 (見圖9G)具有一高/快的上升時間；同樣，數字904所 指不之處，VL部分的波形圖（見圖9H)具有一高/快的上 升時間。考慮到液晶顯示器平板410 (見圖4)為一大的電 阻-電容負載，與圖2所示的輸出緩衝器相比，輸出緩衝器 600高的迴轉率表示輸出緩衝器600能夠隨著電阻-電容負 載，產生對應之較快速的充電/放電。 圖10A係繪示依照本發明之一較佳實施例的一種第一 運算放大器604和上拉電晶體612 (如圖6所示）之電路 圖。同樣，圖10B係繪示依照本發明之一較佳實施例的一 種第二運算放大器006和下拉電晶體610 (如圖6所示） 之電路圖。 在圖10A中，第一運算放大器604具有電壓隨耦器的 結構’係由電晶體1002-1006所組成。另外，第，運算放 大器604也至少包括一電容器1〇18。因為電壓隨耦器對熟 習此技藝者來說是為其所知的，所以在此不作具體詳細的 描述。在圖10A的實際操作中，位於輸入端的輸入信號 INPUT係轉換為在輸出端的輸出信號〇υτρυτ，以響應控 制信號HPU。 在圖10Β中，第二運算放大器606係具有電塵隨耦器 結構，其由多個電晶體1022-1036所組成。另外，第二運 算放大器606也至少包括一個電容器1〇38。同樣地，因為 16 I258723,d〇c 電壓隨耦器對熟習此技藝者來說是為其所知的，所以在此 不作具體詳細的描述。在圖10B的實際操作中，位於輪11 端的輸入信號INPUT轉換為位於輸出端的輸出 OUTPUT，以響應控制信號HPD。 °〜 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之^講 範圍當視後附之申請專利範圍所界定者為準。 又 【圖式簡單說明】 圖1係繪示傳統輸出緩衝器之結構方塊圖。 圖2係繪示另外一傳統輸出緩衝器之結構方塊圖。 圖3A-3F係緣示圖2所示輸出緩衝器的時序圖。 圖4係繪示依據本發明之一較佳實施例的一種液晶顯 示器系統400的方塊圖。 … 圖5係繪示之一較佳實施例的一種源驅動元件414之 方塊圖。 圖6係繪示依照本發明之一實施例的一種圖丨之緩衝 器600之方塊圖。 圖7係繪示依照本發明之一較佳實施例的—種圖6所 示之第二控制器的方塊圖。 圖8A係％示依照本發明之一較佳實施例的—種圖7 所不之早觸發南端電路的方塊圖。 圖8B係繪示依照本發明之一較佳實施例的一種圖7 所示之單觸發低端電路的方塊圖。 17 1258723 14734pif.doc 一較佳實施例的圖6所 圖9A-9H係繪示依照本發明之 示之輸出緩衝器的時序圖。 圖10A係繪不依照本發明之一較佳實施例的一種圖6 所示之第-運算放大器和上拉電晶體的電路圖。 -圖1〇Β_示依照本發明之—較佳實施例的一種圖6 所7F之第一運算放大器和下拉電晶體的電路圖。 【主要元件符號說明】 102 :放大器 202、602 :放大器電路 2〇4:P型電晶體（P型運算放大器） 206 : N型電晶體（N型運算放大器） 208 :控制器 400 :液晶顯示器系統 402 :圖像控制器 406、418 :信號發送元件 408 :時序控制器 412 :閘極驅動元件 414 :源極驅動元件 416 :信號接收元件 502 · N位元移位暫存器 506 :數位類比轉換器（DAC) 508、600 :輪出緩衝器 604 :第一運算放大器 606 :第二運算放大器 18 1258723 14734pif.doc 608 :第一控制器 612 :上拉電晶體 610 :下拉電晶體 616 :第二控制器 702 :單觸發高端電路 704 ··單觸發低端電路 802、808 :緩衝運算放大器 804、810 :反相器 806 :或閘 812 :及閘 1002-1006、1022-1036 :電晶體 1018、1038 :電容器 CTL-H、CTL-L :控制信號 INPUT ·•輸入信號 OE :輸出致能信號 OUTPUT ··輸出信?虎 POL :極性信號The choices generally start from the economic effects, and the changes in W and J are hard. The cycle reduces feedback. The increase in the slew rate due to the increase in the period can eliminate the increase in the current consumed by the output buffer_. The pull-up transistor 612 and the pull-down transistor 61 are both turned on during the following periods: less than about (10) of the period of the polarity signal roL, or less than about 1/1 of the period of the output enable signal 0E; Sexually less than about 1/2 〇〇 of the polarity signal POL period, or less than about 1/100 of the output enable signal 〇e period. 9A-9H are timing diagrams of the output buffer 600 of FIG. 6 in accordance with a preferred embodiment of the present invention. Figure 9A is a waveform diagram of an output enable signal 〇E generated, for example, by timing controller 408 (shown in Figure 4). Fig. 9B is a waveform diagram of the polarity signal POL. 9C and 9D are waveform diagrams of control signals CTL-Η and CTL_L from controller 608 (shown in Figure 6), respectively. 9E is a waveform diagram of the control signal HPU. Figure 9F is a waveform diagram of the HP number HPD. 9G is a waveform diagram of the output signal of the first operational amplifier 604 (the signal generated by the pull-up transistor 612 according to the pull-up of the control signal HPU) (VH portion); FIG. 9H is the second operational amplifier 606 (the following pull transistor 610 is controlled according to the control) The signal generated by the pull-down of the signal HPU) rotates the signal waveform (VL part). As can be seen from Fig. 9C and Fig. 9G, the waveform diagram of the VH portion corresponds to 15 1258723 14734pif.doc h No. CTL_H. Similarly, as can be seen from Figures 9D and 9H, the waveform diagram of the VL portion corresponds to the signal CTL-L. However, it is more effective than traditional technology. As indicated by the numeral 902, the waveform of the vh portion (see Fig. 9G) has a high/fast rise time; likewise, the number 904 indicates that the waveform of the VL portion (see Fig. 9H) has a high / Fast rise time. Considering that the liquid crystal display panel 410 (see FIG. 4) is a large resistive-capacitive load, the high slew rate of the output buffer 600 indicates that the output buffer 600 can follow the resistance as compared with the output buffer shown in FIG. The capacitive load produces a correspondingly faster charge/discharge. Figure 10A is a circuit diagram of a first operational amplifier 604 and a pull-up transistor 612 (shown in Figure 6) in accordance with a preferred embodiment of the present invention. Similarly, Figure 10B is a circuit diagram of a second operational amplifier 006 and pull-down transistor 610 (shown in Figure 6) in accordance with a preferred embodiment of the present invention. In Fig. 10A, the structure of the first operational amplifier 604 having a voltage follower is composed of transistors 1002-1006. In addition, the operational amplifier 604 also includes at least one capacitor 1〇18. Since the voltage follower is known to those skilled in the art, it will not be described in detail herein. In the actual operation of Fig. 10A, the input signal INPUT at the input is converted to the output signal 〇υτρυτ at the output in response to the control signal HPU. In Fig. 10A, the second operational amplifier 606 has a dust follower structure composed of a plurality of transistors 1022-1036. In addition, the second operational amplifier 606 also includes at least one capacitor 1 〇 38. Similarly, since the 16 I258723, d〇c voltage follower is known to those skilled in the art, it will not be described in detail herein. In the actual operation of Fig. 10B, the input signal INPUT at the end of the wheel 11 is converted to the output OUTPUT at the output in response to the control signal HPD. The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and it is obvious to those skilled in the art that the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the structure of a conventional output buffer. 2 is a block diagram showing the structure of another conventional output buffer. 3A-3F are timing diagrams showing the output buffer shown in FIG. 4 is a block diagram of a liquid crystal display system 400 in accordance with a preferred embodiment of the present invention. Figure 5 is a block diagram of a source drive component 414 of a preferred embodiment. FIG. 6 is a block diagram of a buffer 600 of the drawing in accordance with an embodiment of the present invention. Figure 7 is a block diagram of a second controller of Figure 6 in accordance with a preferred embodiment of the present invention. Figure 8A is a block diagram showing an early-triggered south-end circuit of Figure 7 in accordance with a preferred embodiment of the present invention. 8B is a block diagram of the one-shot low-end circuit shown in FIG. 7 in accordance with a preferred embodiment of the present invention. 17 1258723 14734pif.doc Figure 6 of a preferred embodiment Figures 9A-9H are timing diagrams of output buffers in accordance with the present invention. Figure 10A is a circuit diagram showing a first operational amplifier and a pull-up transistor of Figure 6 in accordance with a preferred embodiment of the present invention. - Figure 1 is a circuit diagram of a first operational amplifier and pull-down transistor of Figure 7F of Figure 6 in accordance with a preferred embodiment of the present invention. [Main component symbol description] 102: Amplifier 202, 602: Amplifier circuit 2〇4: P-type transistor (P-type operational amplifier) 206: N-type transistor (N-type operational amplifier) 208: Controller 400: Liquid crystal display system 402: image controller 406, 418: signal transmitting component 408: timing controller 412: gate driving component 414: source driving component 416: signal receiving component 502 · N-bit shift register 506: digital analog conversion (DAC) 508, 600: turn-out buffer 604: first operational amplifier 606: second operational amplifier 18 1258723 14734pif.doc 608: first controller 612: pull-up transistor 610: pull-down transistor 616: second Controller 702: one-shot high-side circuit 704 · one-shot low-end circuit 802, 808: buffer operational amplifier 804, 810: inverter 806: or gate 812: and gates 1002-1006, 1022-1036: transistor 1018, 1038 : Capacitor CTL-H, CTL-L : Control signal INPUT ·• Input signal OE : Output enable signal OUTPUT ·· Output signal? Tiger POL: Polarity signal