CN1551225A - Built-in self-test system and method - Google Patents
Built-in self-test system and method Download PDFInfo
- Publication number
- CN1551225A CN1551225A CNA2004100435264A CN200410043526A CN1551225A CN 1551225 A CN1551225 A CN 1551225A CN A2004100435264 A CNA2004100435264 A CN A2004100435264A CN 200410043526 A CN200410043526 A CN 200410043526A CN 1551225 A CN1551225 A CN 1551225A
- Authority
- CN
- China
- Prior art keywords
- test
- bist
- failure
- data
- built
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 158
- 238000000034 method Methods 0.000 title claims description 20
- 230000015654 memory Effects 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000012544 monitoring process Methods 0.000 claims description 11
- 238000004088 simulation Methods 0.000 claims description 2
- 230000003278 mimic effect Effects 0.000 abstract 1
- 230000008901 benefit Effects 0.000 description 8
- 238000013461 design Methods 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 238000010998 test method Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56004—Pattern generation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C2029/0401—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals in embedded memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
Landscapes
- Tests Of Electronic Circuits (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
外部测试装置系被使用以仿造一内部BIST测试，因此使获取或产生详细测试结果为可能。通过在测试时间实时仿真BIST测试序列，外部测试器可能监控自BIST之一输出且决定失败发生的确实位置。外部测试器可能产生一位失败映像指示是否每一内存位置通过或未通过BIST测试。
External test equipment is used to mimic an internal BIST test, thus making it possible to obtain or generate detailed test results. By simulating the BIST test sequence in real-time at test time, it is possible for an external tester to monitor the output from one of the BISTs and determine exactly where the failure occurred. An external tester may generate a one-bit fail map indicating whether each memory location passed or failed the BIST test.
Description
Technical field
The system and method for the built-in self testing of relate generally to of the present invention (BIST) particularly relates to the system and the method for the real-time outside emulation of BIST.
Background technology
When using specific integrated circuit (ASIC) technological expansion to new market, the denser demand of imbedding internal memory usually increases.For example, be easy to carry and for example take action circuit and personal digital assistant of the market of multimedia application generally need increase the density of imbedding internal memory and be used for higher function and lower power consumption.For the demand of this increase is provided, imbeds the order of DRAM (Dynamic Random Access Memory) (eDRAM) macrodactylia and be supplied in the skill state ASIC briefcase.EDRAM is incorporated into the ASIC design and has generally strengthened the focus test high density macrodactylia order best in how, and a for example complicated DRAM macrodactylia order is in a logic testing environment.
For example, direct memory access (DMA) test often may be used to test traditional DRAM, and it has input table with direct control address, and it is can be by an external test access for data and control pin.External test may directly be operated the DRAM input and monitor its output in order to test.Imbed the direct access test of eDRAM, or the RAM that imbeds of other type for example imbeds magnetic RAM (MRAM) and imbeds quickflashing RAM, yet, usually aspect silicon area, useful I/O (I/O) pin, it is also expensive that writing complex and test duration go up.For example, to imbed RAM, only access to RAM usually be via system applies wherein RAM system be embedded in.When usually may requiring extra memory storage or extra I/O pin, tester comes external access in order to require to be applied to function.
Usually, a preferable solution of flush mounting test problem is to use built-in self testing (BIST) system, and its executive module is enough to high mistake and is covered on the DRAM.This assembly may comprise, for example, the calculating of twice superfluous position solution, pattern sequencing elasticity test in real time or on the speed, and test pattern is applied to marginal test.The foundation of BIST ability has often allowed to test big, and being stored in imbedding does not have the mold area of adding or follow implementation test inexactness on the logic tester, for example, isolates multiplexer.
Usually, BIST be a simple relatively circuit (though it may be complexity) its act on similar one little tester on semi-conductor chip or integrated circuit.BIST may be designed to have partly or access is to imbedding RAM fully, and outside automatic testing equipment often only has very limited access to chip, and dependence BIST carries out detailed memory test.BIST may test core memory subassembly only because the logical circuit of chip may be tested by a logic tester of separating.
Because BIST is on mold and can directly control and imbed RAM, a deviser may design the functional between BIST and actual device circuit of different layers, for example different test patterns.Imbed RAM in order to test, external test may be sent one and instruct BIST to begin a test.Usually, when BIST finishes test, it is got back to external test one numerical value and indicates whether that device passes through or the test of failing.For example, a logical zero may indicate DRAM to pass through test and a logical one may be indicated DRAM failure test, and perhaps vice versa.
One latent defect is that only finite information can be used for chip from the BIST test for external about existing BIST to carry out.Usually, external test only may be used and import with timing in initial BIST test procedure vector, and is used to monitor very limited BIST output, for example the flag pin of a failure and test end (EOT) pin.Usually, in case a test is come into effect, BIST inner generation address and data pattern are delivered to and are imbedded RAM on the chip, and inner comparing data is returned from imbedding RAM.If device to test failure, the then BIST failure of may fail on the outside pin of an appointment is that a logical one is indicated a failure by setting failure signal for example, perhaps keeps a logical zero and indicates one to pass through to test.
From the viewpoint of external test, only the information that receives from BIST for the whole test of whether installing by or fail.In other words, external test receives identical result no matter whether a single memory address is failed on chip, perhaps whole memory array failure, and the external test position of causing that can not differentiate between two and determine failure.
Summary of the invention
These and other problem usually solved or prevented, and technological merit system usually reaches, and by preferred embodiment of the present invention, it uses external test arrangements to come the inner BIST test of emulation, therefore makes to obtain or produce the DCO result for may.By at test period real-time simulation BIST cycle tests, external test may be monitored the failure position when they take place from one of BIST output and decision.External test may produce a failure reflection to be passed through or failure BIST test to indicate whether each core position.
According to a preferred embodiment of the present invention, being used to test the method for imbedding memory core on the semiconductor chip comprises the BIST circuit of a timer to the semi-conductor chip is provided, initialization BIST circuit uses an address sequence with the built-in self testing that memory core is imbedded in execution, begin the emulation of built-in self testing, wherein emulation copy address sequence and wherein emulation use timer with the run-in synchronism of BIST circuit test, monitoring is used for the built-in selftest failure of an indication one internal storage location from the output of BIST circuit, if and internal storage location failure arranged, related internal storage location failure and particular address by emulation produced.
The other preferred embodiment according to the present invention, on the test semiconductor chip system that imbeds memory core have the BIST correspondence comprise an emulation testing program have a control interface with initialization and timing BIST correspondence on semi-conductor chip, one address generator is in order to produce second address sequence that one first address sequence correspondence is produced during memory core is imbedded in a built-in self testing by the BIST correspondence, wherein address generator receives chronometric data in order to synchronization first address sequence and second address sequence from the emulation testing program, and data input node is in order to imbed the data-out bus signal that receives during building self testing within the memory core from the BIST correspondence, wherein the data-out bus signal indicates whether to build within indivedual internal storage locations self testing failure, and wherein test macro system is adapted to failure of a related particular memory unit and corresponding address by address generator produced.
The other preferred embodiment according to the present invention, the semiconductor chip comprises imbeds the array that memory core comprises internal storage location, one BIST circuit link memory core and comprise corresponding in order to the test memory unit in memory core, and but signal wire is attached between BIST circuit and the outside access node, wherein signal wire comprises a data-out bus, and wherein the BIST circuit is in order to provide, on data-out bus, it is tested with a built-in self testing by corresponding other internal storage location of/miss data in test.
The advantage of a preferred embodiment of the present invention is to provide about imbedding the detailed information that memory core replaces single failure or passes through for it.A failure reflection may be produced from BIST test.The indication failure of detailed information possible accuracy ground where occur in and only what device just fail.
A preferred embodiment of the present invention additional advantage is to be possible for it makes the economic memory test of imbedding, because a fabricator does not need to set up the monitoring that a memory test macrodactylia order of crossing platform is used for line.Actual product has BIST and may be used as line monitoring and imbed the internal memory defective with detecting.
The additional advantage of a preferred embodiment of the present invention allows to imbed test on the speed of internal memory for it.May be operated in high speed from the timer of tester so that the practicable test of a device to be provided.
The additional advantage of a preferred embodiment of the present invention for its can be used with check and confirm BIST itself.One defective may be manufactured on the test chip wittingly, and then BIST may be instructed to carry out a test.Video and relatively correctly to be operated with the reality failure from the position failure that test is produced with definite BIST.A preferred embodiment of the present invention may also be used to check the mixed and disorderly operation in address of BIST, as physical address and logical address conversion or transformation.
The aforementioned advantage of briefly pointing out feature of the present invention and technology is in order to describe the present invention in detail, and following explanation may be understood better.Feature and advantage that the present invention is extra will be described in down, and it forms the theme of claim of the present invention.It should may easily be used as the basis of modifying or design other structure or program to carry out the identical purpose of the present invention by the idea of disclosure that those of ordinary skill in the art is appreciated that and specific embodiment.It also should be appreciated that this structure that equates do not disagree with the scope of the invention and spirit by those of ordinary skill in the art, such as in the dependent claims proposition.
Description of drawings
For more intactly understand the present invention with and advantage, the present invention is described now in conjunction with the following drawings, in the accompanying drawing:
Fig. 1 is the calcspar of BIST system, and it is in order to test an eDRAM core;
Fig. 2 is the operation of process flow diagram displayed map 1BIST system;
Fig. 3 is the process flow diagram that the BIST data write the eRAM core; And
Fig. 4 is the process flow diagram of BIST reading of data and comparison loop.
Embodiment
Manufacturing and use preferred embodiment of the present invention system is discussed in detail as follows.Yet it should be appreciated that it can be by the widely variation of hypostazation in specific background to the invention provides many suitable inventive concepts.The specific embodiment system of discussing only illustrates specific mode with manufacturing and use the present invention, but does not limit the scope of the invention.For example, hereinafter the embodiment of Xiang Ximiaoshuing is about a BIST who imbeds the DRAM core, but the present invention may be used in and has other and imbed in the circuit, and for example other type imbeds the internal memory or the circuit of other limited access on an ASIC.
Fig. 1 is a calcspar, a test configuration is described according to a preferred embodiment of the present invention.Imbedding DRAM core 100 and BIST 102 is that the position is on the semi-conductor chip or mold that are connected to automatic testing equipment (ATE) 104.Usually, complete access is to be used on the chip to eDRAM core 100, and only wired access can be used external test arrangements.ERAM core 100 has the standard interface signal of an internal memory, comprises core data at circuit 106, timer 108, address wire 110, row address stroboscope 112, column address stroboscope 114, chip selects 116, can write 118, Timing 120, and core data output line 122.In other embodiments, eDRAM core 100 may have more, still less or different interface signals with control internal memory.
BIST 102 may use interface signal with control operation and monitoring eDRAM core 100 at a test period.BIST 102 has outside spendable signal successively with interface and ATE104.Routine vector input 124 is to use to provide a test vector to BIST 102 by ATE 104.Routine vector 124 may be used with initialization one test and operate by the fc-specific test FC of selecting BIST.ATE 104 may summon the load of routine vector 124 and BIST 102 and load signal 126 are passed through in the actual test that begins.The test system that imbeds internal memory preferably is performed as a guiding test in advance.ATE 104 also provides a differential timing to pass through timing signal timer 1 130 and timer 2 132 to BIST 102.BIST timer 128 is to derive from these timing signals.ATE 102 may also provide a reset signal 140 to BIST 102 to reset the BIST correspondence.
BIST 102 may summon the end of a test to the end 134 of ATE 104 with test signal, and may pass to a test crash by failure signal 136.BIST 102 may also provide data read bus 138 to ATE 104.Data read bus 138 may be any amount of circuit, but preferably be with core data output bus 122 from the identical size of eDRAM core 100.Data-out bus 138 may be used indicating a specific ATE104 that fails, and it may use this information to decide not pass through ad-hoc location.
External test may be for complete or automanual.Preferably, the beginning of ATE 104 controls one test, and pilot signal is used at a test period one not by taking place from BIST 104.ATE 104 comprises emulation testing program 142, its emulation by the performed test of BIST 102 when BIST 102 is just carrying out test.Based on the BIST program of emulation, address generator 144 produces positions in the BIST of identical sequence such as reality, with BIST 102 synchronizations in.One address system is produced, the data-out bus 138 of ATE 104 monitoring one failure indication.If data-out bus 138 indications one failure, this failure of ATE 104 pairings and the corresponding address that produces by address generator 144, and in the ad-hoc location of the mark failure failure reflection 146 on the throne.
Flow process Figure 200 among Fig. 2 illustrates typically operating according to a preferred embodiment of the present invention of BIST test.ATE 104 provides timing to arrive BIST 102, so ATE 104 can be synchronous in the timing of a test period and BIST 102 operations.Preferably, timing can be by the normal toggle speed of running at semi-conductor chip.Depend on test parameter, timing is selectively may be by running slow or even faster than normal toggle speed.At first, a BIST reset cycle 202 is to use reset signal 140 to be begun by ATE 104.After reset cycle was done, ATE 104 execution in step 204 were by load one routine vector or order 124 to one BIST internal memories or logger working load signal 126.Step 206 is waited for the guiding ready signal and is acted on, and after its effect, an inoperation (NOP) is to be performed to postpone a circulation.
The BIST pattern begin 210 and ATE emulation pattern begin 212 and begin to carry out in a synchronous mode.That is exactly, and outside emulation cooperates or follows the BIST pattern and circulates.Identical test procedure by BIST operate may be by external test by following identical address cycle tests by emulation.
Then, in step 214, BIST 102 writes data to all internal storage locations tested in memory core 100.It is that demonstration is more detailed in Fig. 3 that one preferred embodiment BIST writes pattern sequence 300.Write pattern and start from step 302.BIST 102 then carries out a loop and writes with data in all addresses up to tested unit.In the loop, BIST carries out following sequence: excitation 304, and NOP 306, write data 308, and NOP 310, pre-charge 312, and NOP 314.In step 316, BIST determines whether data write pattern and finishes.If also do not finish, BIST carries out the sequence of next address.Finish if write pattern, sequence continues in Fig. 2.
Get back to reference to figure 2, writing after data sequence finishes, BIST 102 beginning test memory cores 100 are written to other core position relatively by sense data and with data in step 216.It is to be shown among Fig. 4 in more detail that one preferred embodiment BIST reads pattern sequence 400.Read pattern and begin to originate in step 402.Write the data except sense data replaces, one read at the beginning of initial portion along with a similar sequence that writes: excitation 404, NOP406, sense data 408, NOP 410, charge 412 again, and NOP 414.After this sequence was finished, BIST compared the numerical value that circulation is envisioned that writes of sense data and the address in step 416.If data equal or effectively as be decided by in the step 418, read sequence and get back to one by the address in step 422.If data are unequal, read the failure that sequence is got back to the address in the step 420.
Get back to reference to figure 2, from passing through of reading that sequence returns or the system that fails is examined at the step 218.If there is not failure, step 224 is proceeded in test.If failure is arranged, the BIST citation is failed external test in step 220.In a preferred embodiment, failure system is sent to external test via data-out bus 138.The BIST engine use one group of data output node or pin to external test with the failure of citation internal storage location, node is the preferable DQ pin that is.Data-out bus system is 8 bit wides preferably, but selectively may perhaps may be less than 8 bit wides for 16 or 32 or more bit wide.Usually, each pin is represented an internal storage location.If from the output of these pin is that the unit of logical zero location is by reading loop test.Yet if the unit testing failure of a location, corresponding data pin system is set to logical one with the failure detecting by external test.
Based on test one failure, external test entry address and data pin are in conjunction with failing in the step 222.When BIST carries out the test imbed the internal storage location core, external test system carries out the emulation of test, operates identical address sequence such as BIST.External test produces absolute address information so works as data with address generator 144 and is received from BIST, and tester may be in conjunction with the corresponding address position.BIST address sequence and data are read, and external address produces the identical timing that system turns to external test synchronously and produced.Tester detecting data output pin state is in each valid data cycle period.If data are logical zero, the unit of expression location is by test.If the BIST output data is a logical one, the then unit testing failure of expression location.External test login failure position and may construction the position failure reflection of memory core use address date and from the output data of BIST reception.
Whether step 224 decision is tested and is finished, and promptly all whether tested internal storage location by decision is.If no, reading cyclic system is repeated.If test is finished, external test is finished the generation of the position failure reflection of imbedding internal memory.The end of BIST possibility use test signal indicates its test of external test for finishing.BIST may also use the failure pin to indicate whether that at that time chip has passed through or the failure integrated testability.
As one selectable, replace or except the data output of monitoring failure, external test may obtain a failure at a BIST test period by failure flag pin.If one read circulation after failure signal be a logical one, then external test may obtain miss data from the DQ pin, and from its address generator entry address information, to be used in failure reflection of construction.
After BIST test execution and position failure reflection were by construction, reflection may be stored in the database.Position failure reflection may be comply with and be stored in the test running, perhaps may be followed and be stored in after test finishes.Position failure reflection may be described the mode with original text or figure output.Usually, a failure reflection may provide about imbedding the very useful and detailed information of internal memory.For example, position failure reflection may help by chip design or make difference between the defective that operation imported of line.
Though the present invention with and advantage describe in detail, it should be appreciated that different changes, replaces and selects to be used to this and do not have and run counter to scope of the present invention and spirit defines as dependent claims.For example, many features discussed above and function can be performed in software, and hardware, or firmware are perhaps in its combination.As other example, those people that will be had the knack of this skill are appreciated that easily that sequence of steps described herein may be changed and still in scope of the present invention.Particularly, the writing all internal storage locations and may at first be performed of data then read and the data of all internal storage locations relatively.Selectable, write and sense data can be selected in some patterns.As other example, logic value may be energized height and not encourage lowly, or vice versa.As other example, timing may be provided among external test, perhaps may be produced and all be provided to external test and BIST respectively.
Moreover the scope system that the present invention uses is not inclined to the program that is confined to described in the instructions, and machine is made material composition, instrument, the special embodiment of method and step.Those of ordinary skill in the art will be easily from exposure of the present invention, program, machine, make material composition, instrument, method, or understand in the step, existing at present or later the development, it is carried out in fact identical function or reaches in fact, and identical result may be used according to the present invention as being described in this corresponding embodiment.Therefore, dependent claims is comprised in this program, machine, manufacturing, material composition, instrument, method or the step.
Claims (20)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/435842 | 2003-05-12 | ||
| US10/435,842 US7159145B2 (en) | 2003-05-12 | 2003-05-12 | Built-in self test system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1551225A true CN1551225A (en) | 2004-12-01 |
| CN100399473C CN100399473C (en) | 2008-07-02 |
Family
ID=33417019
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100435264A Expired - Lifetime CN100399473C (en) | 2003-05-12 | 2004-05-12 | Built-in self-test system and method |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7159145B2 (en) |
| CN (1) | CN100399473C (en) |
| DE (1) | DE102004023407B8 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887758B (en) * | 2009-05-12 | 2013-01-16 | 北京兆易创新科技有限公司 | Emulation verification method of nonvolatile memory |
| CN103077748A (en) * | 2011-10-25 | 2013-05-01 | 珠海扬智电子科技有限公司 | Static random access memory merged built-in self-test method |
| CN104575615A (en) * | 2013-10-16 | 2015-04-29 | 创意电子股份有限公司 | A device and method for built-in self-test memory |
| CN113393892A (en) * | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
| US11862268B2 (en) | 2020-03-11 | 2024-01-02 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100442878B1 (en) * | 2002-07-08 | 2004-08-02 | 삼성전자주식회사 | Apparatus for testing an on-chip ROM and method thereof |
| DE10323865B4 (en) * | 2003-05-26 | 2005-04-21 | Infineon Technologies Ag | Integrated circuit, in particular integrated memory, and method for operating an integrated circuit |
| US7254760B2 (en) * | 2004-10-05 | 2007-08-07 | Verigy (Singapore) Pte. Ltd. | Methods and apparatus for providing scan patterns to an electronic device |
| US7321999B2 (en) * | 2004-10-05 | 2008-01-22 | Verigy (Singapore) Pte. Ltd. | Methods and apparatus for programming and operating automated test equipment |
| US20060195744A1 (en) * | 2005-02-11 | 2006-08-31 | Broadcom Corporation | Method and apparatus to simulate automatic test equipment |
| US8595557B2 (en) * | 2005-02-23 | 2013-11-26 | International Business Machines Corporation | Method and apparatus for verifying memory testing software |
| US7543198B2 (en) * | 2005-10-21 | 2009-06-02 | International Business Machines Corporation | Test data reporting and analyzing using data array and related data analysis |
| DE102006009224B4 (en) * | 2006-02-28 | 2017-04-06 | Advanced Micro Devices, Inc. | Selection of a test algorithm in a controller for built-in memory self-test |
| US7475315B1 (en) | 2007-01-10 | 2009-01-06 | Altera Corporation | Configurable built in self test circuitry for testing memory arrays |
| WO2008117381A1 (en) * | 2007-03-23 | 2008-10-02 | Advantest Corporation | Tester and electronic device |
| US7930601B2 (en) * | 2008-02-22 | 2011-04-19 | International Business Machines Corporation | AC ABIST diagnostic method, apparatus and program product |
| US7847572B2 (en) * | 2008-06-01 | 2010-12-07 | Advantest Corporation | Test system, electronic device, and test apparatus |
| US7830737B2 (en) * | 2008-06-27 | 2010-11-09 | International Business Machines Corporation | SMI memory read data capture margin characterization circuits and methods |
| US8413036B2 (en) * | 2008-11-28 | 2013-04-02 | Agere Systems Llc | Pseudorandom binary sequence checker with control circuitry for end-of-test check |
| US8381019B2 (en) * | 2010-06-24 | 2013-02-19 | International Business Machines Corporation | EDRAM macro disablement in cache memory |
| KR20120136474A (en) * | 2011-06-09 | 2012-12-20 | 삼성전자주식회사 | Apparatus and method for testing semiconductor device |
| KR102185871B1 (en) * | 2014-01-23 | 2020-12-02 | 삼성전자주식회사 | Partial chip and system having the same |
| US9514842B2 (en) * | 2014-09-24 | 2016-12-06 | Apple Inc. | Memory testing system |
| CN106771982B (en) * | 2017-01-20 | 2019-12-10 | 珠海全志科技股份有限公司 | Automatic chip testing method and system |
| US10509074B2 (en) | 2018-02-22 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical testing apparatus for spintronics devices |
| CN110427292A (en) * | 2019-07-29 | 2019-11-08 | 深圳忆联信息系统有限公司 | The method and device that FLASH is tested using embedded ROM |
| CN113393887B (en) | 2020-03-11 | 2022-04-12 | 长鑫存储技术有限公司 | Memory test method and related equipment |
| CN111312328B (en) * | 2020-03-24 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Method and device for testing embedded flash memory and embedded flash memory chip |
| CN113032270B (en) * | 2021-03-31 | 2023-08-22 | 上海天旦网络科技发展有限公司 | White box simulation test method and system based on flow comparison |
| CN120805839A (en) * | 2025-09-11 | 2025-10-17 | 中昊芯英(杭州)科技有限公司 | Failure positioning method, device and program product in chip simulation test |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5961653A (en) * | 1997-02-19 | 1999-10-05 | International Business Machines Corporation | Processor based BIST for an embedded memory |
| US5951704A (en) * | 1997-02-19 | 1999-09-14 | Advantest Corp. | Test system emulator |
| US6519725B1 (en) * | 1997-03-04 | 2003-02-11 | International Business Machines Corporation | Diagnosis of RAMS using functional patterns |
| JP2000011692A (en) * | 1998-06-16 | 2000-01-14 | Advantest Corp | Memory testing apparatus |
| JP2000137997A (en) * | 1998-10-30 | 2000-05-16 | Ando Electric Co Ltd | Fail data memory circuit for semiconductor testing device |
| CN1353423A (en) * | 2000-11-03 | 2002-06-12 | 简篇 | Method for Memory Self-Test |
| US6829728B2 (en) * | 2000-11-13 | 2004-12-07 | Wu-Tung Cheng | Full-speed BIST controller for testing embedded synchronous memories |
| JP4115676B2 (en) * | 2001-03-16 | 2008-07-09 | 株式会社東芝 | Semiconductor memory device |
| US6445626B1 (en) | 2001-03-29 | 2002-09-03 | Ibm Corporation | Column redundancy architecture system for an embedded DRAM |
| US6400619B1 (en) | 2001-04-25 | 2002-06-04 | International Business Machines Corporation | Micro-cell redundancy scheme for high performance eDRAM |
| US6910155B2 (en) * | 2001-06-25 | 2005-06-21 | Hewlett-Packard Development Company, L.P. | System and method for chip testing |
| US6388930B1 (en) | 2001-09-05 | 2002-05-14 | International Business Machines Corporation | Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters |
| US6452848B1 (en) | 2001-09-12 | 2002-09-17 | International Business Machines Corporation | Programmable built-in self test (BIST) data generator for semiconductor memory devices |
| US7171596B2 (en) * | 2002-09-11 | 2007-01-30 | Infineon Technologies Ag | Circuit and method for testing embedded DRAM circuits through direct access mode |
-
2003
- 2003-05-12 US US10/435,842 patent/US7159145B2/en not_active Expired - Lifetime
-
2004
- 2004-05-12 CN CNB2004100435264A patent/CN100399473C/en not_active Expired - Lifetime
- 2004-05-12 DE DE102004023407.8A patent/DE102004023407B8/en not_active Expired - Fee Related
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101887758B (en) * | 2009-05-12 | 2013-01-16 | 北京兆易创新科技有限公司 | Emulation verification method of nonvolatile memory |
| CN103077748A (en) * | 2011-10-25 | 2013-05-01 | 珠海扬智电子科技有限公司 | Static random access memory merged built-in self-test method |
| CN103077748B (en) * | 2011-10-25 | 2015-09-16 | 珠海扬智电子科技有限公司 | The merging built-in self-test method of static RAM |
| CN104575615A (en) * | 2013-10-16 | 2015-04-29 | 创意电子股份有限公司 | A device and method for built-in self-test memory |
| CN113393892A (en) * | 2020-03-11 | 2021-09-14 | 长鑫存储技术有限公司 | Control chip test method and related equipment |
| US11862268B2 (en) | 2020-03-11 | 2024-01-02 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
| US11867758B2 (en) | 2020-03-11 | 2024-01-09 | Changxin Memory Technologies, Inc. | Test method for control chip and related device |
| CN115691632A (en) * | 2022-10-19 | 2023-02-03 | 中科声龙科技发展（北京）有限公司 | Test control system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| DE102004023407B4 (en) | 2013-10-10 |
| CN100399473C (en) | 2008-07-02 |
| US20040230870A1 (en) | 2004-11-18 |
| DE102004023407A1 (en) | 2004-12-09 |
| US7159145B2 (en) | 2007-01-02 |
| DE102004023407B8 (en) | 2014-01-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1551225A (en) | Built-in self-test system and method | |
| US6415403B1 (en) | Programmable built in self test for embedded DRAM | |
| US5173906A (en) | Built-in self test for integrated circuits | |
| JP3795822B2 (en) | Embedded self-test circuit and design verification method | |
| EP0805460B1 (en) | Integrated circuit having a built-in selft-test arrangement | |
| US7278078B2 (en) | Built-in self-test arrangement for integrated circuit memory devices | |
| US6829728B2 (en) | Full-speed BIST controller for testing embedded synchronous memories | |
| Jain et al. | Built-in self testing of embedded memories | |
| TW559823B (en) | System and method for identification of faulty or weak memory cells under simulated extreme operating conditions | |
| US8201037B2 (en) | Semiconductor integrated circuit and method for controlling semiconductor integrated circuit | |
| US6553527B1 (en) | Programmable array built-in self test method and controller with programmable expect generator | |
| US7729185B2 (en) | Apparatus and method for detection of address decoder open faults | |
| JPH09127206A (en) | Method and integrated self-test device for integrated circuit testing to capture fault information about selected faults | |
| JPH10162600A (en) | Semiconductor memory device with built-in test function | |
| Cheng et al. | Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories | |
| Dekker et al. | Realistic built-in self-test for static RAMs | |
| JP3367848B2 (en) | Test equipment for semiconductor devices | |
| US20050182993A1 (en) | Semiconductor integrated circuit device equipped with read sequencer and write sequencer | |
| US7240257B2 (en) | Memory test circuit and test system | |
| JP2003223798A (en) | Test facilitation circuit | |
| Hong et al. | A programmable memory BIST for embedded memory | |
| CN100516913C (en) | Method for processing vectors tested digitally | |
| JP2000090693A (en) | Memory test device | |
| Haron et al. | Modeling and simulation of microcode Memory Built In Self Test architecture for embedded memories | |
| CN100592096C (en) | Automated fault testing of logic blocks using internal real-speed logic - BIST |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| ASS | Succession or assignment of patent right |
Owner name: INFINEON TECHNOLOGIES AG Free format text: FORMER OWNER: INFINENON TECH. NORTH AMERICA CO. |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20041105 Address after: Munich, Germany Applicant after: INFINEON TECHNOLOGIES AG Co-applicant after: International Business Machines Corp. Address before: California, USA Applicant before: INFINEON TECHNOLOGIES NORTH AMERICA Corp. Co-applicant before: International Business Machines Corp. |
|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20080702 |
|
| CX01 | Expiry of patent term |