CN1542528A - Method for manufacturing thin film transistor liquid crystal display panel - Google Patents
Method for manufacturing thin film transistor liquid crystal display panel Download PDFInfo
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- CN1542528A CN1542528A CNA031250246A CN03125024A CN1542528A CN 1542528 A CN1542528 A CN 1542528A CN A031250246 A CNA031250246 A CN A031250246A CN 03125024 A CN03125024 A CN 03125024A CN 1542528 A CN1542528 A CN 1542528A
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- 238000000034 method Methods 0.000 title claims abstract description 87
- 239000010409 thin film Substances 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title abstract description 7
- 239000004973 liquid crystal related substance Substances 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 102
- 239000004065 semiconductor Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000001259 photo etching Methods 0.000 claims description 45
- 229910052751 metal Inorganic materials 0.000 claims description 30
- 239000002184 metal Substances 0.000 claims description 30
- 239000012212 insulator Substances 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 14
- 239000011521 glass Substances 0.000 claims description 13
- 230000001681 protective effect Effects 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 claims description 5
- 239000011651 chromium Substances 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- 241000206607 Porphyra umbilicalis Species 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 239000010453 quartz Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 2
- 239000002356 single layer Substances 0.000 claims description 2
- 239000010949 copper Substances 0.000 claims 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- 229910045601 alloy Inorganic materials 0.000 claims 2
- 239000000956 alloy Substances 0.000 claims 2
- 239000004411 aluminium Substances 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000004615 ingredient Substances 0.000 claims 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000000151 deposition Methods 0.000 abstract description 15
- 238000005530 etching Methods 0.000 abstract 2
- 239000011241 protective layer Substances 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
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- 229910000838 Al alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
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- RHZWSUVWRRXEJF-UHFFFAOYSA-N indium tin Chemical compound [In].[Sn] RHZWSUVWRRXEJF-UHFFFAOYSA-N 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
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- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
A method for manufacturing a thin film transistor liquid crystal display panel comprises the following steps: firstly, defining a scanning line, a data line segment which is not contacted with the scanning line and a grid electrode on a substrate, then depositing a dielectric layer, a semiconductor layer and a high-doped semiconductor layer to form an active region, then etching a contact hole, then depositing a transparent conductive layer to connect the data line segments at two sides of the scanning line, etching a pixel electrode, a source electrode and a drain electrode, and finally forming a protective layer and exposing the pixel electrode.
Description
Technical field
The present invention relates to a kind of Thin Film Transistor-LCD (Thin Film Transistor LiquidCrystal Display, TFT-LCD) method for making of panel, particularly relate to a kind of sweep trace and data line bit in same plane, avoid the TFT-LCD panel making method of sweep trace/data line interlaced area short circuit by this.
Prior art
Flourish along with electronics IT industry, the range of application of LCD (1iquid crystal display.LCD) and the market demand are also constantly enlarging, from small sized product, as electronic sphygmomanometer, to the portable information product, as personal digital assistant (PDA), notebook computer (notebook),, all can see LCD and be widely used on it to such an extent as to future very may business-like big view display.Because the structure of LCD is very during Thin Film Transistor-LCD, sweep trace and data line interlaced area or thin film transistor (TFT) be the processing procedure that can't expect of generation or human factor and make lcd products produce point defect or line defect at last easily often.
Please refer to Fig. 1, Fig. 1 is the section layout top view of existing TFT-LCD.Prior art is to utilize five road photoetching processes (PEP) to form TFT-LCD10 on a transparent glass substrate.As shown in Figure 1,36 of the sweep trace 18 of TFT-LCD and data lines are to be defined in Different Plane in the prior art, and vertical interlaced is in one staggered (cross over) district 14.Thin film transistor (TFT) source electrode 32 is to be electrically connected at data line 36, and thin film transistor (TFT) drain electrode 34 needs to see through an interlayer hole (via hole) 41 (forming) in addition in existing the 4th road PEP processing procedure and is electrically connected with pixel electrode 42.
Please refer to Fig. 2 A to 2E, Fig. 2 A to 2E is existing diagrammatic cross-section of making TFT-LCD.
Shown in Fig. 2 A, the method of the existing TFT-LCD of making panel is to deposit a first metal layer earlier on the surface of glass substrate 11, then carry out one first photoetching process, on the surface of glass substrate 11, to form a gate electrode 16 and a sweep trace 18 by ecotone 14 respectively at transistor area 12.
Shown in Fig. 2 B, then on glass substrate 11, deposit a gate insulator (gateinsulator) 22 and semi-conductor layer (semiconductor layer) 24 and one high doping semiconductor layer (heavily doped semiconductor laver) 26 successively.Then carry out one second photoetching process and etch away doping semiconductor layer and semiconductor layer outside the transistor area 12, to form the active region of thin film transistor (TFT).
Shown in Fig. 2 C, above doping semiconductor layer and gate insulator, deposit one second metal level subsequently, and carry out the pattern that one the 3rd photoetching process defines second metal level, with source electrode (source) 32, drain electrode (drain) 34 that forms thin film transistor (TFT) in transistor area 12, and definition simultaneously forms a data line 36 (data line) by ecotone 14.
Shown in Fig. 2 D; subsequently in glass substrate 11 tops deposition one by protective seam 38 that monox or silicon nitride constituted; and carry out one the 4th photoetching process; remove the protective seam 38 that part is positioned at drain electrode 34 tops of thin film transistor (TFT) 44; with the interlayer hole 41 on the one through drain electrode of formation in protective seam 38,34 surfaces, and expose drain electrode 34 partly.
Shown in Fig. 2 E, form one at last in glass substrate 11 tops by tin indium oxide (indiumtin oxide comprehensively, ITO) or indium zinc oxide (indium zinc oxide, IZO) transparency conducting layer 40 that is constituted, and carry out one the 5th photoetching process, to form a pixel electrode (pixel electrode) 42 that electrically connects with the drain electrode 34 of thin film transistor (TFT) 14.
As from the foregoing, the method for making of existing TFT-LCD panel is that to adopt data line 36 interconnected in the framework of Different Plane about in the of 18 with sweep trace.In addition, in the method for making of existing TFT-LCD panel, because need carry out five gold-tinteds and etching program, therefore Thin Film Transistor-LCD is very easy to influence the production yield because of various defectives, and work as the liquid crystal panel size of being produced when increasing, this kind problem more shape is serious.Especially near the ecotone 14 and transistor area 12 that data line 36 and sweep trace 18 pass through simultaneously; regular meeting is good inadequately because of platform (taper) shape of sweep trace 18 that is positioned at lower floor or gate electrode 16; undercutting (under cut) phenomenon of sweep trace 18 or grid lines (gate line); there is the contaminate particulate factors such as (particle) of not expecting in metal ejection (metal eruption) phenomenon and semiconductor layer 24 and the gate insulator 22; after deposition second metal level, produce short circuit (gate-signal short) phenomenon of sweep trace 18 and data line 36.From the above, no matter the manufacturing technology of traditional TFT-LCD panel is not all attained ideal on making step, process rate and product configurations, and treat further to overcome improvement especially.
Therefore, in the design of TFT-LCD panel, how to reduce the number of times of deposition or etch process,,, just become the important topic when making the TFT-LCD panel to keep certain production yield to avoid problems such as above-mentioned sweep trace and data line short circuit.
Summary of the invention
Fundamental purpose of the present invention is to provide a kind of Thin Film Transistor-LCD (Thin FilmTransistor Liquid Crystal Display, TFT-LCD) method for making, the sweep trace of this TFT-LCD panel and data line are to be defined in same plane, can avoid sweep trace/data line ecotone phenomenon that is short-circuited.In addition, the method for making of TFT-LCD panel of the present invention need not deposit one second metal level, therefore can simplify fabrication steps, obviously improves processing procedure usefulness and yield rate.
At most preferred embodiment of the present invention, one substrate is provided earlier, this substrate comprises at least one pixel region, one is used for forming the transistor area and the one scan line/data line ecotone of a thin film transistor (TFT) (TFT), at first on the surface of this substrate, deposit a metal level, carry out one first photoetching process (photo-etching-process, PEP), defining sweep trace simultaneously in this substrate surface reaches and the not contacted data line of sweep trace, and in this transistor area, form the grid (gate) of this thin film transistor (TFT), deposit a gate insulator (gate insulator) then successively, a semi-conductor layer (semiconductor layer) and a high doping semiconductor layer (heavily doped semiconductor layer), then carry out one second photoetching process, remove semiconductor layer and high doping semiconductor layer outside this transistor area, to form the active region (active region) of thin film transistor (TFT).Carry out one the 3rd photoetching process then, in gate insulator, form contact hole (contact hole), expose the data line of part of scanning line both sides, then deposit a transparency conducting layer (transparent conducting laver), and fill up the data line of this contact hole with cross-over connection sweep trace both sides.Carry out one the 4th photoetching process again; with formation pixel electrode (pixel electrode), source electrode (source), drain electrode (drain), and connect data line and source electrode, at last deposition one protective seam on substrate; and carry out photoetching process the 5th time, to expose pixel electrode.
Because LCD method for making of the present invention, be that sweep trace and data line are placed same plane, that is first time during photoetching process, promptly defining sweep trace simultaneously reaches and the not contacted data line of sweep trace, utilize transparency conducting layer cross-over connection data line in addition again, so not only can reduce by a minor metal deposition manufacture process, more can avoid the short circuit problem in the interlaced area, further promote and produce yield.
Description of drawings
Fig. 1 is the section layout top view of existing TFT-LCD.
Fig. 2 A to E is existing diagrammatic cross-section of making TFT-LCD.
Fig. 3 is the section layout top view of TFT-LCD of the present invention.
Fig. 4 A to E makes the diagrammatic cross-section of TFT-LCD for the present invention.
Fig. 5 is the flow process comparison diagram of the TFT-LCD processing procedure of the present invention and prior art.
The reference numeral explanation
10TFT-LCD system 11 glass substrates
12 transistor area, 14 ecotones
16 gate electrodes, 18 sweep traces
22 gate insulators, 24 semiconductor layers
26 high doping semiconductor layers, 32 source electrode
34 drain electrodes, 36 data lines
38 protective seams, 40 transparency conducting layers
41 interlayer holes, 42 pixel electrodes
100TFT-LCD system 101 glass substrates
102 sweep traces, 104 data lines
108 drain electrodes of 106 gate electrodes
110 source electrodes, 112 contact hole districts
114 pixel electrodes, 116 transistor area
118 ecotones, 122 metal levels
124 gate insulators, 126 semiconductor layers
128 high doping semiconductor layers, 130 transparency conducting layer
132 protective seams, 138 contact holes
501 deposition the first metal layers, 502 first road photoetching processes
503 deposit gate insulator/semiconductor layer/high doping semiconductor layer successively
504 second road photoetching processes
505 depositions, second metal level 506 the 3rd road photoetching process
507 deposition protective seams 508 the 4th road photoetching process
509 deposit transparent conductive layers 510 the 5th road photoetching process
521 deposition the first metal layers, 522 first road photoetching processes
523 deposit gate insulator/semiconductor layer/high doping semiconductor layer successively
524 second road photoetching processes
525 the 3rd road photoetching processes
526 deposit transparent conductive layers 527 the 4th road photoetching process
528 deposition protective seams 529 the 5th road photoetching process
Embodiment
Please refer to Fig. 3, Fig. 3 is the layout top view of TFT-LCD of the present invention system 100.The inventive method is to utilize First Five-Year Plan time photoetching process to go up in transparent glass substrate 101 (Fig. 3 does not show) to form TFT-LCD system 100, and substrate 101 might be a quartz base plate or a plastic substrate.As shown in Figure 3, characteristic of the present invention is that the sweep trace 102 of TFT-LCD and data line 104 are to be positioned at same plane, both arranged perpendicular but in ecotone 118, do not contact, see through in addition cross-over connection of contact hole 138 but utilize just like L type transparency conducting layer among the figure 130, L type transparency conducting layer 130 also is electrically connected to the source electrode 110 of thin film transistor (TFT).Pixel electrode 114 directly is electrically connected with the drain electrode 108 of thin film transistor (TFT), without any contact hole.Herein, pixel electrode 114 and L type transparency conducting layer 132 are by with one deck person that has come that transparent conductive material defines.
Please refer to Fig. 4 A to 4E, Fig. 4 A to 4E is the diagrammatic cross-section according to the TFT-LCD panel processing procedure of a preferred embodiment of the present invention.Shown in Fig. 4 A, at first on the surface of glass substrate 101, deposit a metal level comprehensively, then carry out one first photoetching process, define this metal level with surface in glass substrate, forming a plurality of sweep traces 102 (be positioned at zone 118), a plurality of and the not contacted discontinuous data line segment of sweep trace (data line section or data line strip) 104 (being positioned at regional 112) respectively, and a gate electrode 106 (being positioned at regional 116).Gate electrode 106 is to be connected in one scan line corresponding with it.Each data line segment 104 is between two adjacent sweep traces, with conplane sweep trace orthogonal configuration (see figure 3).Below for convenience of description, zone 116 is called transistor area, zone 112 is called contact hole district, and zone 118 is called ecotone.In successive process, the data line segment 104 that is positioned at one scan line both sides will be electrically connected mutually by a transparency conducting layer and a contact hole by ecotone 118, to form sweep trace and data line array.Wherein this metal level can be a single-layer metal layer or is a multilayer composite metal layer.If the former, the material that then constitutes this metal level is for comprising chromium, molybdenum or tungsten-molybdenum alloy.If the latter, the material ground floor that then constitutes this two-layer compound metal is an aluminum or aluminum alloy, and the second layer comprises the alloy-layer of titanium, chromium and molybdenum, or the tungsten-molybdenum alloy layer.
Shown in Fig. 4 B, then on glass substrate 101, deposit a gate insulator (gateinsulator) 124, semi-conductor layer (semiconductor layer) 126 and one high doping semiconductor layer (heavily doped semiconductor layer) 128 successively, and carry out one second photoetching process, etch away thin film transistor region 116 semiconductor layer 126 and high doping semiconductor layer 128 in addition, to be formed with source region.Wherein gate insulator 124 is for single (single) dielectric layer or one compound (cornposite) dielectric layer, by monox (SiO
x), silicon nitride (SiN
y) or silicon oxynitride (SiO
xN
y) constitute.Semiconductor layer 126 also is called as active layer (active layer), and it is to be a hydrogeneous amorphous silicon layer, and is used as the usefulness of the passage (channel) when thin film transistor (TFT) is unlocked.And highly doped semiconductor layer 128 is to be used to provide that ohm formula contact (ohmic contact) with reduction resistance between transparency conducting layer 130 and the semiconductor layer 126.
Shown in Fig. 4 C, then carry out the 3rd photoetching process, form contact hole 138 in gate insulator 124, expose the data line 104 of part of scanning line 102 both sides.
Shown in Fig. 4 D, then deposit a transparency conducting layer 130 again and should contact hole 138 and fill up, utilize the data line segment 104 of these transparency conducting layer 130 cross-over connection sweep traces 120 both sides.Carry out one the 4th photoetching process then, the pixel electrode 114, source electrode 110, drain electrode 108 and that defines direct electrical connection drain electrode 108 is by ecotone 118 and connect the L type transparency conducting layer 130 of data line 104 and source electrode.Wherein this transparency conducting layer 130 by tin indium oxide (indium tin oxide, ITO) or indium zinc oxide (indiumzinc oxide IZO) constitutes.
Shown in Fig. 4 E, again deposit one by protective seam (passivation layer) 132 that monox, silicon nitride or silicon oxynitride constituted at last, and carry out one the 5th photoetching process, pixel electrode 114 is revealed.
For further understanding the difference of the TFT-LCD method for making of the present invention and prior art, please refer to Fig. 5.Fig. 5 is the flow process comparison diagram of the TFT-LCD processing procedure of TFT-LCD of the present invention and prior art.It is as follows that existing TFT-LCD makes process description:
Step 501: deposition the first metal layer;
Step 502: with first road photoetching process definition sweep trace and the grid;
Step 503: successive sedimentation gate insulator/semiconductor layer/high doping semiconductor layer;
Step 504: with the second road photoetching process definition active region;
Step 505: deposit second metal level;
Step 506: with the 3rd road photoetching process definition of data line, source electrode, drain electrode and channel region;
Step 507: deposition protective seam;
Step 508: with photoetching process definition contact hole, the 4th road;
Step 509: deposit transparent conductive layer;
Step 510: with the 5th road photoetching process definition pixel electrode;
And TFT-LCD making process description of the present invention is as follows:
Step 521: deposition the first metal layer;
Step 522: reach the discontinuous data line segment that does not contact with sweep trace with the first road photoetching process definition sweep trace, grid;
Step 523: successive sedimentation gate insulator/semiconductor layer/high doping semiconductor layer;
Step 524: with the second road photoetching process definition active region;
Step 525: with photoetching process definition contact hole, the 3rd road;
Step 526: deposit transparent conductive layer;
Step 527:, and see through the discontinuous data line segment of contact hole cross-over connection with the 4th road photoetching process definition source electrode, drain electrode, passage area, pixel electrode;
Step 528: deposition protective seam;
Step 529: with the 5th road photoetching process definition pixel electrode;
Compared to prior art, the present invention is in first time during photoetching process, form sweep trace and discontinuous a plurality of data line segment simultaneously, be that sweep trace and data line are same planes, position, gate insulator 124 in contact hole district 112 etches contact hole 138 more afterwards, and utilize the data line segment 104 of a L type transparency conducting layer 130 cross-over connection sweep traces 102 both sides and the source electrode 110 of thin film transistor (TFT), so not only can reduce the processing procedure of a metal deposition, the more important thing is the short circuit that to avoid interlaced area, and then promote processing procedure usefulness and yield.
The above preferred embodiment only of the present invention, all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (12)
1. the method for making of a LCD panel of thin-film transistor comprises the following steps:
One substrate is provided, deposits a metal level on it, include a transistor area, an ecotone on this substrate, and a contact hole district, wherein this transistor area is to form a thin film transistor (TFT);
Carry out one first photoetching process, define this metal level, with on this substrate, define simultaneously one scan line, two lay respectively at these sweep trace both sides and with the not contacted data line segment of this sweep trace, and the grid of this thin film transistor (TFT);
Deposit one first dielectric layer (dielectric layer), a semi-conductor layer (semiconductorlayer) and a high doping semiconductor layer (heavily doped semiconductor laver) successively;
Carry out one second photoetching process, to form the active region (active region) of thin film transistor (TFT);
Carry out one the 3rd photoetching process, form the contact hole, expose this data line segment of these sweep trace both sides of part in this dielectric layer;
Deposit a transparency conducting layer (transparent conducting layer), and insert this contact hole;
Carry out one the 4th photoetching process, define pixel electrode (pixel electrode), source electrode (source), drain electrode (drain), and connect data line and source electrode;
Deposition one second dielectric layer on substrate; And
Carry out one the 5th photoetching process, expose pixel electrode to the open air.
2. method for making as claimed in claim 1, wherein this substrate is to comprise glass substrate, quartz base plate or plastic substrate.
3. method for making as claimed in claim 1, wherein this first metal layer is to be a single-layer metal structure, and the material that constitutes this first metal layer comprises chromium (Cr), molybdenum (Mo) or tungsten-molybdenum alloy (MoWalloy).
4. method for making as claimed in claim 1, wherein this metal level is a multilayer composite metal structure, and the material that constitutes this multi-layer metal structure contains aluminium (Al) or be the alloy, copper (Cu) of principal ingredient with aluminium or be the alloy of principal ingredient with copper.
5. method for making as claimed in claim 1, wherein this first dielectric layer is that (gate insulating, GI) layer comprises monox (SiO as gate insulator
x), silicon nitride (SiN
y) or silicon oxynitride (oxynitride, SiON).
6. method for making as claimed in claim 1, wherein this second dielectric layer is as protective seam (passivation layer), comprises monox, silicon nitride or silicon oxynitride.
7. method for making as claimed in claim 1, wherein this semiconductor layer is to be an amorphous silicon layer (amorphous silicon layer, α-Silayer), polysilicon layer (polycrystal silicon layer) or monocrystalline silicon layer (single crystal silicon layer).
8. method for making as claimed in claim 1, wherein this high doping semiconductor layer is the Ohmic contact (ohmic contact) in order to semiconductor layer and electrically conducting transparent interlayer to be provided.
9. method for making as claimed in claim 1, wherein this transparency conducting layer be by tin indium oxide (indium tin oxide, ITO) or indium zinc oxide (indium zinc oxide IZO) constitutes.
10. method for making as claimed in claim 1, wherein this data line segment and this sweep trace are same planes, position.
11. method for making as claimed in claim 1, wherein this data line segment and this sweep trace utilize transparency conducting layer cross-over connection in addition in this ecotone.
12. method for making as claimed in claim 1 wherein in this second photoetching process, can keep this high doping semiconductor layer of this ecotone and semiconductor layer or remove.
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| CNB031250246A CN1304896C (en) | 2003-04-29 | 2003-04-29 | Manufacturing method of thin film transistor liquid crystal display panel |
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| CNB031250246A CN1304896C (en) | 2003-04-29 | 2003-04-29 | Manufacturing method of thin film transistor liquid crystal display panel |
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| CN1304896C CN1304896C (en) | 2007-03-14 |
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| CN100570864C (en) * | 2006-11-23 | 2009-12-16 | 中华映管股份有限公司 | Pixel structure and manufacturing method thereof |
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