CN1404141A - A method for manufacturing a nitride read-only memory for preventing charge charging - Google Patents

Abstract

The present invention provides a method for fabricating a Nitride Read Only Memory (NROM) for preventing charge charging. The method comprises forming an ONO (oxide-nitride-oxide) layer composed of a bottom oxide layer, a silicon nitride layer and a top oxide layer on the surface of a substrate including a memory region and a peripheral region. Then, a plurality of bit line masks (bit line masks) arranged longitudinally are formed on the surface of the ONO layer in the memory region, and a plurality of buried bit lines (buried bit lines) are formed in the substrate uncovered by the bit line masks by utilizing a first ion implantation treatment. A plurality of word lines are formed on the ONO layer, which are arranged laterally and nearly perpendicular to the plurality of buried bit lines. Finally, forming a spacer (spacer) on the peripheral sidewall of each word line, and sequentially forming a barrier layer and a passivation layer on the substrate surface to prevent the nitride read-only memory from being charged during the semiconductor process.

Description

A method for fabricating a nitride read-only memory for preventing charge charging

Field of Invention

The invention provides a manufacturing method of a nitride read-only memory.

Background Description

Nitride read only memory (NROM) is a semiconductor device used to store data. It consists of multiple memory cells, each of which contains MOS transistors and silicon nitride layer. Due to the high density of the silicon nitride layer, the MOS transistor can be tunneled into the hot electron trap in the silicon nitride layer to achieve the purpose of storing data.

Please refer to FIG. 1 to FIG. 4 . FIG. 1 to FIG. 4 are schematic diagrams of a known method for fabricating a nitride ROM. As shown in FIG. 1 , a known nitride ROM is fabricated on the surface of a silicon substrate 12 . The silicon substrate 12 is a P-type silicon substrate and includes a memory array for storing charges and a peripheral circuit for logic circuit control. The known method is to perform conventional oxidation-nitride-oxidation (oxide-nitride-oxide, ONO) treatment on the surface of the silicon substrate 12 to form a bottom oxide layer (bottom oxide) 14, a silicon nitride layer 16 and an upper oxide layer. ONO dielectric layer 19 composed of top oxide 18. Then form a photoresist layer 20 on the surface of the ONO dielectric layer 19, and carry out a yellow light treatment and an etching process, so that the photoresist layer 20 forms a pattern, which is used to define the bit line (bit line) Location.

As shown in FIG. 2 , the photoresist layer 20 is then used as a mask to perform dry etching to remove the upper oxide layer 18 and the silicon nitride layer 16 not covered by the photoresist layer 20. , followed by ion implantation treatment 22 to form a plurality of doped regions 24 in the silicon substrate 12 to serve as bit lines of the memory, or called buried drains. The photoresist layer 20 is then completely removed.

As shown in FIG. 3 , a field oxide layer 26 is formed on the surface above the bit line 24 by using a thermal oxidation method, as an isolation between the silicon nitride layers 16 . Finally, as shown in FIG. 4 , a doped polysilicon layer 28 is deposited as a word line.

It is known that after the word line is fabricated in the known nitride read-only memory, in order to prevent the element from being damaged by ultraviolet radiation or plasma in the subsequent chemical deposition process or etching process, a protective layer 29 will be formed to cover the surface of each word line, and A spacer 27 is formed on the sidewalls around each word line, as shown in FIG. 5 . However, since the protective layer 29 is in direct contact with the ONO dielectric layer 19 of the nitride read-only memory, part of the free electrons generated by ultraviolet radiation in the subsequent chemical deposition process or etching process will pass through the protective layer 29 and enter into the ONO dielectric layer 19, thereby affecting the electrical performance of the nitride ROM.

Invention Summary

Therefore, the object of the present invention is to provide an improved method for manufacturing a nitride read-only memory (NROM), so as to prevent the nitride read-only memory from being irradiated by ultraviolet light (UV light) or generating plasma damage (plasma) in subsequent processing. damage).

In the preferred embodiment of the present invention, firstly provide the substrate that the surface includes the storage area and the peripheral area, and then form a bottom oxide (bottom oxide) layer, a silicon nitride layer and a top oxide (top oxide) layer on the surface of the substrate. ) layer composed of oxide-nitride-oxidation (oxide-nitride-oxide) (ONO) layer. Then, a plurality of bit line masks (bit line masks) arranged vertically are formed on the surface of the ONO layer in the storage area, and then the first ion implantation process is performed to form a plurality of bit line masks on the substrate not covered by the bit line masks. Form a plurality of buried bit lines (buried bit lines). After removing the bit line mask, a plurality of word lines arranged laterally and nearly perpendicular to the plurality of buried bit lines are formed on the surface of the ONO layer. Finally, a sacrificial layer is formed on the surface of the substrate, and an etch-back process is performed on the sacrificial layer to form a spacer on the sidewalls around each word line, and a barrier layer and a protection layer are sequentially formed on the surface of the substrate.

Since the surface of the nitride read-only memory manufactured by the present invention is sequentially formed with a barrier layer and a protective layer, it is possible to prevent the nitride read-only memory from being irradiated by ultraviolet light or plasma damage during subsequent processing. , while the barrier layer can effectively isolate the protective layer and the ONO dielectric layer of the nitride read-only memory, to avoid direct contact between the protective layer and the ONO dielectric layer, so it can further suppress the free in the protective layer Electrons enter the ONO dielectric layer and affect the electrical performance of the nitride ROM.

Detailed description of the invention

Please refer to FIG. 6 to FIG. 10 . FIG. 6 to FIG. 10 are schematic cross-sectional diagrams of manufacturing a nitride ROM according to the present invention. As shown in FIG. 6 , the nitride ROM of the present invention is manufactured on the surface of the substrate 32 of the semiconductor wafer 30 , and the surface of the substrate 32 defines a storage area and a peripheral area. In a preferred embodiment of the present invention, the substrate 32 is a P-type silicon substrate. However, the present invention is not limited thereto. In other embodiments of the present invention, the substrate 32 may also be a silicon-on-insulator (SOI) substrate. For the convenience of illustrating the key point of the present invention, FIG. 6 to FIG. 10 only show the cross-section of the nitride ROM storage area of the present invention. As shown in Figure 6, at first on the surface of the substrate 32, an ONO dielectric layer 39 with a thickness of about 150 to 250 angstroms (angstrom, A) is formed. layer 34, a silicon nitride layer 36 having a thickness of approximately 20 to 150 angstroms, and an upper oxide layer 38 having a thickness of approximately 50 to 150 angstroms.

Next, the step of adjusting the threshold voltage (threshold voltage) of the peripheral area elements is performed. First, a mask (not shown) is formed on the surface of the ONO dielectric layer 39 in the storage area, and ion implantation is performed to adjust the unmasked The dopant concentration in the covered substrate 32, and finally remove the mask. Subsequently, as shown in FIG. 7, a photoresist layer 40 is formed on the surface of the ONO dielectric layer 39, and a yellow light treatment and an etching process are performed, so that the photoresist layer 40 is patterned to define the position of the bit line . Then use the photoresist layer 40 as a bit line mask, and arrange them vertically on the surface of the ONO dielectric layer 39 . Next, ion implantation treatment 42 is performed to dope the substrate 32 not covered by the photoresist layer 40 with arsenic ions (arsenic, As) or other N-type doping, so as to form a plurality of N-type substrates in the substrate 32 The doped doped region 44 serves as a buried bit line of the memory. In the ion implantation process 42 , a typical dose of arsenic ions is about 1E15 to 1E16 atoms/cm ² . The implantation energy is about 20 to 80 KeV, preferably 50 KeV. Then, a rapid tempering treatment is performed at a temperature of about 800 to 1000° C. to activate the dopants implanted in the substrate 32 . The photoresist layer 40 is then completely removed.

As shown in FIG. 8 , a doped polysilicon layer 46 is deposited on the surface of the semiconductor wafer 30 as word lines. The word lines are arranged laterally on the surface of the semiconductor wafer 30 and form a nearly vertical overlapping arrangement with the doped region 44 , as shown in FIG. 9 .

Finally, as shown in FIG. 10 , FIG. 10 is a cross-sectional view along line A-A in FIG. 9 . A sacrificial layer (not shown) made of a silicon nitride compound is formed on the surface of the substrate 32, and the sacrificial layer is etched back to the surface of the substrate 32, so as to form a spacer around the sidewalls of each word line layer (spacer)47. Finally, a barrier layer 48 made of silicon oxide compound and a protective layer 50 made of silicon nitride compound are sequentially formed on the surface of the substrate 32 . The protective layer 50 is used to prevent the nitride read-only memory (NROM) from being irradiated by ultraviolet light (UV light) or plasma damage (plasma damage) in a subsequent process, and is formed on the protective layer 50 and the nitride read-only memory (NROM). The barrier layer 48 between the memories is used to prevent the protective layer 50 from being in contact with the silicon nitride layer 36, so as to avoid part of the free electrons generated by ultraviolet radiation in the subsequent chemical deposition process or etching process from passing through the protective layer. 50 into the ONO dielectric layer 39, thereby affecting the electrical properties of the nitride read-only memory (NROM).

Compared with the known manufacturing method of nitride read-only memory, the present invention uses a chemical vapor deposition method to form a barrier layer to isolate the protection layer from the ONO dielectric layer of the nitride read-only memory, because the protection layer The free electrons that may be generated by ultraviolet radiation in the subsequent chemical deposition process or etching process, so the blocking layer can prevent the free electrons in the protective layer from entering the ONO dielectric layer, so as to prevent the nitride read-only memory from being processed. The effect of being charged by the electric charge, and then improve the endurance and reliability of the nitride ROM.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

A brief description of the icon

1 to 5 are schematic diagrams of known methods for fabricating nitride ROMs.

6 to 10 are schematic diagrams of the method for fabricating the nitride ROM according to the present invention.

Explanation of symbols in the diagram

12 Silicon base 14 Bottom oxide layer

16 silicon nitride layer 18 upper oxide layer

19 ONO dielectric layer 20 photoresist layer

22 Ion implantation treatment 24 Doping area (bit line)

26 Field Oxide Layers 27 Spacer Layers

28 doped polysilicon layer (word line) 29 protective layer

30 semiconductor wafer 32 base 34 bottom oxide layer 36 silicon nitride layer 38 upper oxide layer doping 39 ONO dielectric layer 40 photoresist layer (bit line mask) 42 ion distribution process 44 doping area (bit line) Heteropolysilicon layer (word line) 47 spacer layer 48 barrier layer 50 protection layer

Claims (10)

1. A method for making a nitride read-only memory (NROM) for preventing charge charging, the method comprises the following steps: providing a substrate, and the surface of the substrate includes a storage area and a peripheral area; forming an oxidation-nitride-oxidation (ONO) layer consisting of a bottom oxide layer, a silicon nitride layer and an upper oxide layer on the surface of the substrate; forming a plurality of vertically arranged bit line masks on the surface of the ONO layer in the storage area; performing a first ion implantation process to form a plurality of buried bit lines in the substrate not covered by the bit line mask; removing the bit line mask; forming a plurality of word lines arranged laterally and nearly perpendicular to the plurality of buried bit lines on the surface of the ONO layer; forming a sacrificial layer on the surface of the base, and performing an etch-back process on the sacrificial layer until the surface of the base forms a spacer on the sidewalls around each of the word lines; and A barrier layer and a protection layer are sequentially formed on the surface of the base. 2. The method according to claim 1, wherein the method further comprises the following steps before forming the plurality of bit line masks: forming a mask on the surface of the ONO layer less than the storage area; performing a second ion implantation process to adjust the dopant concentration in the substrate not covered by the mask; and Remove the mask. 3. The method according to claim 1, wherein the thickness of the bottom oxide layer is between 50 to 150 angstroms (A), the thickness of the silicon nitride layer is between 20 to 150 angstroms, and the thickness of the upper oxide layer is between 50 to 150 Angstroms. 4. The method of claim 1, wherein the bit line mask is formed of photoresist. 5. The method of claim 1, wherein the substrate is a silicon substrate or a silicon-on-insulator (SOI) substrate. 6. The method of claim 1, wherein the sacrificial layer is composed of silicon nitride. 7. The method according to claim 1, wherein the protective layer is used to prevent the nitride read only memory (NROM) from being damaged by ultraviolet radiation or plasma during a subsequent process. 8. The method of claim 7, wherein the protective layer is composed of silicon nitride. 9. The method according to claim 1, wherein the barrier layer is used to prevent the protective layer from being in contact with the silicon nitride layer to cause the nitride read-only memory to be charged by electric charges during processing, thereby affecting the nitride read-only memory (NROM) ) electrical properties. 10. The method of claim 9, wherein the barrier layer is formed of silicon oxide.

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