CN1258218C - Method for making a system integrated chip - Google Patents

Abstract

The present invention provides a method for fabricating a System On Chip (SOC) using Nitride Read Only Memory (NROM) processing to create ROM and NROM. The method comprises forming an ONO dielectric layer on the substrate surface, and performing photolithography and ion implantation. Then, the ONO dielectric layer on the peripheral circuit region is removed, the threshold voltage (threshold voltage) of the transistor in the peripheral circuit region is adjusted, and then the ONO dielectric layer on the ROM region is removed, and a thermal oxidation method is performed. Then, forming word lines of the memory area and gate electrodes of transistors of peripheral circuit in the peripheral circuit area to form at least one nitride ROM in the nitride memory area and high and low initial voltage elements in the ROM area simultaneously, and finally injecting one ROM code.

Description

Method for making a system integrated chip

technical field

The present invention provides a memory system integrated chip (system on chip, SOC), especially a system integrated chip (SOC) that utilizes nitride read-only memory (NROM) processing to establish read-only memory (ROM) and nitride read-only memory (SOC). SOC) production method.

Background technique

A read-only memory (ROM) device is a semiconductor device used to store data. It is composed of multiple memory cells and has been widely used in computer data storage and memory. According to the data storage method, the read-only memory can be divided into mask ROM (mask ROM), programmable read-only memory (Programable ROM, PROM), erasable programmable read-only memory (Erasable programmable ROM, EPROM), electronic Erasable programmable read-only memory (Electrically erasable programmable ROM, EEPROM), nitride read-only memory (nitride read only memory, NROM) and flash memory (flash ROM), which are characterized in that once the data or data is stored After entering, the stored data or data will not disappear due to the interruption of the power supply, so it is also called non-volatile memory (non-volatile memory).

The main feature of the nitride read-only memory (NROM) is that it uses an insulating dielectric layer of silicon nitride as a charge trapping medium. Due to the high density of the silicon nitride layer, hot electrons entering the silicon nitride layer through tunneling through the MOS transistor can be trapped in it, thereby forming a non-uniform concentration distribution to Speed up reading data and avoid leakage current. As for flash memory, polysilicon or metal floating gate (floating gate) is used to store charges, so in addition to the general control gate (control gate), there will be one more gate. The former has the advantages of simple manufacturing process and low manufacturing cost. And the latter because it is necessary to make the structure of floating gate-intermediate dielectric layer-control gate, and the quality of the materials in this three-layer structure is very important, it must be matched with appropriate treatment, so the manufacturing process is more complicated and consumes a lot of money. The cost is also higher.

However, in the current electronics industry, ROMs and non-volatile memories often need to exist in various products at the same time. When placed on a chip, it not only takes up more space, but also consumes a higher cost. Therefore, in U.S. Patent No. 5,403,764, Yamamoto et al. will propose a method, in the fabrication process of the flash memory element, partly located in the flash memory element in the read-only memory area (ROM region), with ion implantation (ion implantation) to inject read-only memory code (ROM code), that is, to complete the so-called write program, and then continue to complete the flash memory processing. Therefore, in the flash memory chip, a part of the ROM can be built.

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic diagrams of a known method for fabricating a flash memory chip 10 including a read-only memory 24 . As shown in FIG. 1, the known method of making a flash memory chip 10 that includes a read-only memory 24 is to first provide a semiconductor chip 11 that includes a P-type silicon base (sillicon base) 12, and then use a temperature of about Thermal oxidation treatment at 1100°C for about 90 minutes, when not covered by an oxidation-protective film (not shown) such as a silicon nitride (Si ₃ N ₄ ) layer On the surface of the silicon substrate 12, a plurality of silicon dioxide (silicon dioxide, SiO ₂ ) layers 14 with a thickness of several thousand angstroms (angstrom, A) are formed, and this silicon dioxide layer 14 is also called a field oxide layer (field oxide layer, FOX). After completion, the remaining silicon nitride layer (not shown) is removed, and only a thin silicon oxide layer 16 remains between the silicon dioxide layer 14 and the silicon dioxide layer 14 , that is, between each FOX. In other words, local oxidation (LOCOS) is used to isolate the subsequent transistors from each other.

Then, as shown in FIG. 2, an ion implantation process (ion implantation process) is performed in the read-only memory area 18 on the flash memory chip 10. The ion implantation process uses an acceleration energy of 40 to 50 keV and a dose of 1E12 to 3E12/cm ² of boron (Boron) ions to form a first P+ type doped region 22 with an implanted ion concentration of 10 ¹⁶ -10 ¹⁷ /cm ³ . The purpose of the ion implantation process is to adjust the threshold voltage (threshold voltage, Vth) of the first ROM (not shown) in the ROM area 18 to a first specific value, so that a first ROM The initial voltage of the memory (not shown) is adjusted to about 1V to store a "1" data.

As shown in Figure 3, carry out a first yellow light processing, in the read-only memory area 18 on the flash memory chip 10, to form the initial voltage is the part outside the read-only memory 26 of the second specific value, and only Parts other than the read memory area 18 form a first mask 31 . Then an ion implantation process is performed on the flash memory chip 10 . The ion implantation process uses boron (Boron) ions with an acceleration energy of 40-50keV and a dose of 5E12-1E13/cm ² to form a second P+-type doped ion with a final implanted ion concentration of 10 ¹⁷ -10 ¹⁸ /cm ³ Miscellaneous area 32. The purpose of the ion implantation process is to adjust the threshold voltage (threshold voltage, Vth) of the second ROM (not shown) in the ROM area 18 to a first specific value, so that the second ROM The starting voltage (not shown) is adjusted to about 7V to store a "0" data.

Next, as shown in FIG. 4, a first polysilicon layer 34, an intermediate insulating layer 36 made of silicon nitride or silicon oxide, and a second polysilicon layer 38 are sequentially deposited on the flash memory chip 10. . Then a second yellow light treatment is performed to form the double gates 39 of the first and second ROMs 24 , 26 and the flash memory 40 . Although generally speaking, the gate pole structures of the first and second read-only memories 24, 26 are single-layer, and there is no need to use a three-layer double gate pole 39 structure, but in the prior art, in order to reduce processing steps, therefore All gates are done in the same processing step.

As shown in FIG. 5, a third mask (not shown) is used, and a phosphorus (phosphorous) ion implantation process is performed to form a gate on both sides of the double gate 39 of the first and second read-only memories 24, 26. An N+ type source 41 and drain 42 to complete the fabrication of the first and second ROMs 24 and 26 . Finally, a fourth mask (not shown) is used, and another phosphorus (phosphorous) ion implantation process is performed to form an N+ type source 43 and a drain 44 on both sides of the double gate 39 of the flash memory 40, respectively. To complete the fabrication of the flash memory 40 . In this way, it is only necessary to add two processing steps for adjusting the initial voltage in the general standard flash memory manufacturing process, not only the read-only memories 24 and 26 on the flash memory chip 10 are written with "1" or It is the data of "0", and the flash memory 40 is also completed at the same time.

However, the flash memory chip in the prior art only includes a part of the read-only memory, which does not achieve the purpose of the system integration chip. Moreover, the production cost of the flash memory is relatively high, which is not suitable for the production of the system integration chip. Therefore, how to develop and manufacture a kind of system integrated chip, in order to utilize the lower cost components and its processing, can make read-only memory and nitride read-only memory on the same chip at the same time, and can omit general non-volatile memory After the completion, the electrical writing step that is still required becomes a very important issue.

Contents of the invention

The main purpose of the present invention is to provide a method for making a memory system integrated chip (system onchip, SOC), especially a process using nitride read-only memory (NROM) to establish read-only memory (ROM) and nitride read-only memory (SOC). A method for manufacturing a system-on-chip (SOC) of a memory.

In the preferred embodiment of the present invention, the system integrated chip is arranged on the surface of a semiconductor chip, and utilizes the process of nitride read-only memory (NROM) to simultaneously fabricate read-only memory (ROM) and nitride-only memory (NROM). Read memory, the manufacturing method of the system integrated chip includes the following steps: on the surface of the substrate, a "bottom oxide layer-silicon nitride layer-on oxide layer" (ONO) dielectric layer is formed on the surface of the substrate, and a first Yellow light treatment and a first ion implantation treatment to form a plurality of N-type doped regions and bit lines in the substrate. The ONO dielectric layer on the peripheral circuit area is etched away, and a second ion implantation process is performed to adjust the threshold voltage of the transistor in the peripheral circuit area. A third etching process is performed to remove the ONO dielectric layer on the read-only memory area, and then a thermal oxidation is performed to form a buried drain oxide layer on the surface of each bit line , and form the gate oxide layers of the low initial voltage element, the high initial voltage element and the peripheral circuit transistor on the read only memory area and the peripheral circuit area respectively. Using a second yellow light and a fourth etching process to simultaneously form each word line in the memory area and each gate of each peripheral circuit transistor in the peripheral circuit area, and form at least one nitride only on the nitride memory area. The memory is read, and a low threshold voltage element and a high threshold voltage element are respectively formed in the low threshold voltage (lowVth) element area and the high threshold voltage (high Vth) element area of the read only memory area. A third ion implantation process is used to adjust the threshold voltage of the high threshold voltage device. The third ion implantation treatment includes performing a fourth yellow light treatment to form a patterned fourth photoresist layer covering the low starting voltage element in the read-only memory area, the non-volatile memory area And the peripheral circuit area; also include the P-type impurity settled in the high initial voltage element, so as to adjust the initial voltage of the high initial voltage element, complete the read-only memory code processing and remove the fourth photoresist layer. Because there are high threshold voltage components and low threshold voltage components in the read-only memory area, it can be used as a read-only memory. Therefore, the system integrated chip includes not only peripheral circuit transistors, but also ROMs and nitride ROMs.

Because the present invention utilizes the nitride ROM and the added ion implantation process, the ROM and the nitride ROM are fabricated on the same system integrated chip at the same time. Therefore, it can not only avoid the time and manpower required to produce the general non-volatile memory by electrical writing, which is not suitable for mass production, but also maintain the principle of simple processing. Next, make a low-cost system integration chip.

Description of drawings

1 to 5 are schematic diagrams of a known method for fabricating a flash memory chip including a read-only memory.

6 to 12 are schematic diagrams of the method of embedding the nitride ROM and the shielded ROM into the system integrated chip of the present invention.

In the accompanying drawings, 10 represents a flash memory chip, 11 represents a semiconductor chip, 12 represents a silicon substrate, 14 represents a silicon dioxide layer, 16 represents a silicon oxide layer, 18 represents a read-only memory area, and 22 represents the first P+ type doped Miscellaneous region, 24 represents the first read-only memory, 26 represents the second read-only memory, 31 represents the first shield, 32 represents the second P+ type doped region, 34 represents the first polysilicon layer, 36 represents the intermediate insulating layer, 38 represents the second polysilicon layer, 39 represents the double gate, 40 represents the flash memory, 41 represents the source, 42 represents the drain, 43 represents the source, 44 represents the drain represents the system integrated chip, 101 represents the semiconductor chip, 102 represents the P-type silicon substrate, 103 represents the peripheral circuit area, 104 represents the memory area, 105 represents the nitride read-only memory area, 106 represents the read-only memory area, 107 represents the low initial voltage element area, and 108 represents the high initial voltage element 109 represents the doped region, 110 represents the shallow trench isolation region, 112 represents the bottom oxide layer, 114 represents the silicon nitride layer, 116 represents the upper oxide layer, 118 represents the ONO dielectric structure, 121 represents the first photoresist layer, 122 Represents the bit line, 123 represents the P-type pocket doped region, 124 represents the P-type pocket doped region, 126 represents the active region, 128 represents the buried drain oxidation, 134 represents the word line, 136 represents the peripheral circuit transistor, 138 represents Gate, 142 represents a nitride read-only memory, 144 represents a low initial voltage element, 146 represents a high initial voltage element, 147 represents a lightly doped source/drain, 148 represents a spacer, 149 represents a source, and 150 represents a The drain, 152, represents the third photoresist layer.

Detailed ways

Please refer to FIG. 6 to FIG. 12 . FIG. 6 to FIG. 12 are schematic diagrams of a method for embedding a nitride ROM and a masked ROM in the system integrated chip 100 of the present invention. As shown in FIG. 6, the manufacturing method of the system integrated chip 100 of the present invention is to first provide a semiconductor chip 101 comprising a P-type silicon base (silicon base) 102. The semiconductor chip 101 includes a peripheral circuit area 103 and a memory area. 104, the peripheral circuit area 103 includes high and low voltage transistor elements (not shown), capacitance elements (not shown) and resistance elements (not shown), etc., and the memory area 104 includes a nitride read-only memory area 105 and The ROM area 106 further includes at least a low threshold voltage (low threshold, low Vt) element area 107 and a high threshold voltage (high threshold, high Vt) element area 108 in the ROM area 106 . In the present invention, since the components in the peripheral circuit area 103 are not the key points of the invention, only a general description is made, and in the illustration, only a single high-voltage peripheral circuit transistor is used as a representative.

First, part of the peripheral circuit area 103 can be processed first, using an N-type ion implantation process and a P-type ion implantation process to form N-type wells (not shown) for high-voltage transistor elements (not shown) in the peripheral circuit area 103 respectively. and a P-type well (not shown), but in the present invention, for the sake of convenience, only a doping well (well) 109 is used as a representative. Next, a plurality of insulators are formed on the surface of the substrate 102 to respectively isolate the peripheral circuit area 103 , the nitride ROM area 105 and the ROM area 106 , and define active areas of each element. Wherein, the insulator can be a shallow trench isolation region, or a field oxide layer, and the shallow trench isolation region 110 is taken as a representative in the figure for illustration.

As shown in FIG. 7, a low temperature oxidation (low temperature oxidation) treatment with a temperature range of 750° C. to 1000° C. is then used to form an oxide layer of 50 to 150 angstrom (A) on the surface of the silicon substrate 102, which is used as a bottom layer. oxide layer 112 . Then a low pressure chemical vapor deposition (LPCVD) treatment is performed to deposit a nitride on the surface of the bottom oxide layer 112 as the floating gate of the nitride read-only memory with a thickness of 100-300 angstroms (A). The silicon layer 114 serves as a charge trapping layer. Finally, in a high temperature environment of 950° C., a tempering treatment is carried out for 30 minutes to repair the structure of the silicon nitride layer 114, and water vapor is introduced to carry out wet oxidation to form a layer with a thickness of 50 ~ A silicon oxy-nitride layer of 200 Angstroms (A) is used as the upper oxide layer 116 . Wherein, during the formation process of the upper oxide layer 116, the silicon nitride layer 114 of approximately 25-100 Angstroms (A) will be consumed, and the bottom oxide layer 112 and the silicon nitride layer 114 formed on the surface of the silicon substrate 102 and the upper oxide layer 116 are collectively referred to as the ONO dielectric structure 118 .

Then as shown in FIG. 8, a first photoresist layer 121 is formed on the surface of the ONO dielectric structure 118, and a first yellow light treatment and etching process are performed to form a predetermined pattern in the first photoresist layer 121 to define The location of the bit line. Next, using the pattern of the first photoresist layer 121 as a mask, a dry etching process is performed to completely remove the upper oxide layer 116, the silicon nitride layer 114 and the bottom oxide layer 112 not covered by the first photoresist layer 121, That is, all the ONO dielectric structures 118, or only the upper oxide layer 116 and the silicon nitride layer 114 not covered by the photoresist layer 121 are removed, and part of the bottom oxide layer 112 is etched to a predetermined thickness. Then perform an arsenic (arsenic) ion implantation process with an ion concentration of 2-4E15/cm ² and an energy of about 50Kev to form a plurality of N ⁺ type doped regions in the silicon substrate 102 as bit lines 122 of the memory, or It is called a buried drain, and two adjacent doped regions define a channel, and the distance between two adjacent doped regions is the channel length.

Next, an oblique angle ion implantation process is performed to form a P ⁻ -type pocket doped region 123 on one side of each bit line 122 . Then an oblique angle ion implantation process is performed to form a P ^- type pocket doped region 124 on the other side of each bit line 122 . The two oblique-angle ion implantation processes have substantially the same ion implantation parameters except that the incident direction is different. The two-angle ion implantation process uses BF ²⁺ as dopant, the dose is about 1E13 to 1E15 ions/cm ² , the energy is about 20 to 150 KeV, and the incident angle to the silicon substrate 102 is about 20 to 45°. The two oblique angle treatments can also be performed before the ion implantation treatment for forming the bit line 122 . Within this range of conditions, the maximum concentration of BF ²⁺ dopants implanted into the silicon substrate 102 appears in the silicon substrate 102 at a depth of about 1000 angstroms below the channel, and the horizontal distance below the implanted channel is about hundreds to 1000 angstroms . The purpose of forming the P ^- type doped regions 123, 124 is to provide a high electric field region at one end of the channel, and the high electric field region can improve the hot electron (hot carrier) effect and increase the time when electrons pass through the channel when writing (program). In other words, the electrons are accelerated, so that more electrons can obtain enough kinetic energy to pass through the bottom oxide layer 112 into the silicon nitride layer 114 through collision or scattering effect, thereby improving the writing efficiency.

Then, as shown in FIG. 9 , the first photoresist layer 121 is removed. Then perform a second dry etching process on the system integrated chip 100 to remove the ONO dielectric structure 118 in the peripheral circuit region 103, and then use a photomask (not shown) as a shield to perform a first ion implantation process to Ion implantation is performed on the active region 126 of the peripheral circuit transistor (not shown) for threshold voltage adjustment. The aforementioned N-type ion implantation treatment and P-type ion implantation treatment for forming the N-type well (not shown) and P-type well (not shown) of the high-voltage transistor element (not shown) in the peripheral circuit region 103 can also be performed in An ion implantation process is performed before.

As shown in FIG. 10 , a third etching process is performed to remove the ONO dielectric structure 118 on the ROM area 106 , and a cleaning process is performed on the peripheral circuit area 103 and the surface of the ROM area 106 . The purpose of this step is to additionally form a gate oxide layer to replace the ONO dielectric structure 118 in subsequent processing. Then perform a thermal oxidation treatment to form a buried drain oxide layer 128 on the surface of each bit line 122, and use the high temperature heat energy of the thermal oxidation treatment to activate the doped drain in each bit line 122. quality. In addition, the thermal oxidation treatment will also form a gate oxide layer 132 with a thickness of 100-250 angstroms in the area not covered with the ONO dielectric structure 118 on the surface of the semiconductor chip 101, while the memory area 104 on the semiconductor chip 101 has been Where the ONO dielectric layer 118 is present, the gate oxide layer 132 is no longer formed. That is to say, the thermal oxidation treatment will form low threshold voltage elements (not shown), high threshold voltage elements (not shown) and peripheral circuit transistors (not shown) on the ROM area 106 and the peripheral circuit area 103 respectively. ) gate oxide layer 132.

It is worth mentioning that after the above treatment, several N-type wells, P-type well injection treatments, and several repeated cleaning and etching and thermal oxidation treatments can also be added to improve the peripheral circuit area on the semiconductor chip 101. Peripheral circuit transistors (not shown) with different voltages are manufactured in 103 . Next, as shown in FIG. 11 , a polysilicon layer (not shown) or a layer comprising polysilicide and polysilicon is deposited on the surfaces of the ONO dielectric structure 118, the buried drain oxide layer 128, and the gate oxide layer 132. composite layer. Then perform a second yellow light treatment to form a patterned second photoresist layer 133 on the surface of the polysilicon layer to define the connection between the word lines in the memory area 104 and the gates of the peripheral circuit transistors in the peripheral circuit area 103 Location.

Carry out a fourth etching process subsequently, remove the polysilicon layer that is not covered by this second photoresist layer 133, to simultaneously form the word line 134 in the memory area 104 and the gate electrode 138 of the peripheral circuit transistor 136 in the peripheral circuit area 103 . Finally, the second photoresist layer 133 is removed, and at least one nitride ROM 142 is formed on the nitride ROM area 105, and at least one nitride ROM 142 is formed on the low starting voltage (low Vth) element area 107 and the high voltage of the ROM area 106. The high Vth device region 108 forms a low Vth device 144 and a high Vth device 146 respectively.

As shown in FIG. 12 , several processing steps are then performed to continue to complete the unfinished processing steps of the peripheral circuit transistor 136 in the peripheral circuit region 103 of the system integrated chip 100, such as lightly doped source/drain (lightly doped drain). , LDD) 147, spacer (spacer) 148 and source/drain (S/D) 149,150 fabrication. Then utilize a third photoresist layer 152 to cover the low starting voltage (low Vth) element region 107 and the entire peripheral circuit region 103 and the nitride read-only memory region 105 in the read-only memory region 106, and then perform another starting voltage Adjusted ion implantation process, implanting P-type impurities into the high starting voltage (high Vth) element region 108 in the read-only memory region 106, this step can also be called the implantation of the read-only memory code (ROM code), used to adjust the read-only memory code (ROM code) The threshold voltage of the high threshold voltage element 146 in the memory area 106 is read. Finally, the third photoresist layer 152 is removed. Wherein, the third photoresist layer 152 can cover the buried drain 128 together, or expose the buried drain 128 .

Due to the existence of the high threshold voltage element 146 and the low threshold voltage element 144 in the read-only memory area 106, they can respectively represent 0&1 or 1&0 when the chip is running to achieve the purpose of storing data or data. After completing the injection of the read-only memory code (ROM code), the inter-metal dielectric layer (inter-metal dielectric, ILD) (not shown), the metal layer (metal layer) (not shown) are then performed on the system integrated chip 100 And contact hole (contact hole) (not shown), and contact plug (contact plug) (not shown) manufacturing steps, in order to complete the whole processing of system integrated chip 100, and on this system integrated chip 100, besides including some The peripheral circuit of the peripheral circuit transistor 136 also includes a masked ROM and a nitride ROM.

Because the manufacturing method of the system integrated chip provided by the present invention is to use the nitride read-only memory and the added ion implantation process to simultaneously manufacture the read-only memory and the nitride read-only memory on the same chip, so that not only can avoid the general abnormal After the volatile memory is completed, it still needs to be produced by electrical writing, which consumes time and manpower and is not suitable for mass production. At the same time, because the processing of the nitride read-only memory is simple, the manufacturing cost is only about the same as that of the shielded read-only memory, and the function is comparable to that of the flash memory, so the nitride read-only memory is used to establish the read-only memory and the nitride read-only memory. Compared with the prior art, the method of system integration chip of the memory significantly reduces the manufacturing cost and simplifies the manufacturing process obviously.

Compared with the known way of making flash memory chip including ROM, the present invention utilizes nitride ROM and ion implantation process to build the system integration chip of ROM and nitride ROM, which can not only avoid Generally, after the non-volatile memory is completed, it needs to be produced by electrical writing, which is not suitable for mass production because it consumes too much time and manpower. At the same time, the production cost can be greatly reduced and the production process can be obviously simplified under the premise that the function is comparable to that of the flash memory.

The above descriptions are only preferred embodiments of the present invention, and all changes and modifications made according to the claims of the present invention shall fall within the scope of the patent of the present invention.

Claims (8)

1. manufacture method of utilizing nitride ROM to set up the system combination chip of read-only memory and nonvolatile memory, this system combination chip comprises the substrate that a definition has a memory areas and a periphery circuit region, and this memory areas comprises a non-volatile memory region and a read-only memory district, and this read-only memory district includes an at least one low starting voltage element region and a high starting voltage element region, and the manufacture method of this system combination chip includes the following step:

Form impure well at periphery circuit region;

Form a plurality of insulants at this substrate surface, isolating this periphery circuit region, this non-volatile memory region and this read-only memory district respectively, and define the active region of each element;

Form a dielectric structure layer that oxide layer constituted on by a bottom oxide, a silicon nitride layer and at this substrate surface;

This bottom oxide-silicon nitride layer-on oxide layer dielectric layer surface form one first photoresist layer, and carry out that one first gold-tinted is handled and etch processes to define the position of many bit lines;

Utilize this first photoresist layer to carry out one first etch processes, to remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer that is not covered by this first photoresist layer as shielding;

Carry out one first ion and inject processing, in this substrate, to form a plurality of N type doped regions, as respectively this bit line in this memory areas;

Carry out a rake angle ion and inject processing,, carry out a rake angle ion again and inject processing, form a P type doped region with opposite side at each bit line to form a P type doped region at each bit line;

Remove this first photoresist layer;

Carry out one second etch processes, remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer on this periphery circuit region;

Carry out one second ion and inject processing, be used for adjusting the transistorized starting voltage of this periphery circuit region;

Carry out one the 3rd etch processes, remove this bottom oxide-silicon nitride layer-last oxide layer dielectric layer in this read-only memory district;

Carry out a thermal oxidation method, bury the drain electrode oxide layer to form one, and on this read-only memory district and this periphery circuit region, form the gate oxide of this low starting voltage element, this high starting voltage element and this peripheral circuit transistor respectively on this bit line surface respectively;

Form a polysilicon layer and one second photoresist layer in regular turn at this substrate surface, and utilize one second gold-tinted to handle, with the position of a plurality of gate poles of in this second photoresist layer, defining many word lines in this memory areas and respectively this peripheral circuit transistor in this periphery circuit region;

Carry out one the 4th etch processes, remove this polysilicon layer that is not covered by this second photoresist layer, respectively this gate pole with respectively this peripheral circuit transistor of forming respectively this word line in this memory areas and this periphery circuit region simultaneously, remove second photoresist layer, and on this non-volatile memory region, form mononitride read-only memory at least, and form a low starting voltage element and a high starting voltage element respectively at this low starting voltage element region and this high starting voltage element region in this read-only memory district;

Form the 3rd photoresist layer;

Carry out one the 3rd ion and inject processing, be used for adjusting the starting voltage of this high starting voltage element; And

Remove the 3rd photoresist layer.

2. the method for claim 1, wherein this substrate is a silicon base.

3. the method for claim 1, wherein this bottom oxide be utilize the low-temperature oxidation of 750 ℃～1000 ℃ of temperature ranges handle form, and the thickness of this bottom oxide is 50～150 dusts.

4. the method for claim 1, wherein this silicon nitride layer be utilize a low pressure gas phase deposition handle form, be used for being used as the unsteady gate pole of this nitride ROM, and the thickness of this silicon nitride layer is 100～300 dusts.

5. the method for claim 1, wherein should go up oxide layer is to utilize a wet oxidation to handle institute to form, and is somebody's turn to do upward that thickness of oxide layer is 50～200 dusts.

6. the step that the method for claim 1, wherein forms impure well in this periphery circuit region is injected the processing realization by one the 4th ion.

7. the method for claim 1, wherein this high starting voltage element and output signal that should low starting voltage element are to be used for representing respectively 0 or 1 or 1 or 0, to store a specific data or data.

8. the method for claim 1, wherein this read-only memory district is a shielded read-only memory district.

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