CN1492505A - Electrostatic discharge protection circuit - Google Patents

Abstract

The invention discloses an electrostatic discharge protection circuit, which comprises an NPN Darlington circuit and an N-type metal oxide semiconductor transistor. The drain of the N-type metal oxide semiconductor transistor is connected to the input end of the NPN Darlington circuit, the source of the N-type metal oxide semiconductor transistor is connected to the control end of the NPN Darlington circuit, and the grid of the N-type metal oxide semiconductor transistor is connected to the output end of the NPN Darlington circuit.

Description

Electrostatic discharge protection circuit

technical field

The invention relates to an electrostatic discharge protection circuit, in particular to an NPN Darlington (Darlington) electrostatic discharge protection circuit.

Background technique

Static electricity can be said to be ubiquitous, and any two objects of different materials rubbing against each other may generate static electricity. When an object with static electricity touches the metal pins of the IC (integrated circuit), the instantaneous high-voltage discharge will affect the internal circuit (internal circuit) through the metal pins, so it is said that it is caused by electrostatic discharge (ESD). The resulting damage is likely to cause the failure of the electronic system. The main function of the electrostatic discharge protection circuit is to start before the electrostatic discharge pulse (pulse) reaches the internal circuit when electrostatic discharge occurs, so as to quickly eliminate the excessive voltage and reduce the damage caused by electrostatic discharge. At the same time, the protection circuit must also be able to withstand the energy of the electrostatic discharge pulse without causing damage to the protection circuit itself. In addition, the electrostatic discharge protection circuit must only operate when electrostatic discharge occurs, and not operate at other times, so as not to affect the normal operation of the electronic system.

Please refer to FIG. 1 . FIG. 1 is a circuit diagram of a conventional ESD protection circuit for bipolar junction transistors. As shown in Figure 1, in the bipolar complementary metal-oxide-semiconductor transistor (BiCMOS) process, an NPN bipolar junction transistor (NPN BJT) is used as an electrostatic discharge protection circuit, and the base of the NPN bipolar junction transistor (base ) floating, the emitter (emitter) is grounded, and the collector (collector) is connected to an internal circuit input attenuator (input pad) or a voltage source attenuator (VDD pad), when the internal circuit input attenuator or When the voltage source attenuator is disturbed by an electrostatic discharge pulse, the NPN bipolar junction transistor is broken down and turned on, and the electrostatic discharge current is grounded. The advantage of using an open-base NPN bipolar junction transistor as an ESD protection circuit is that the input capacitance of the NPN bipolar junction transistor is small, so the NPN bipolar junction transistor can be turned on quickly, but the current that the NPN bipolar junction transistor can draw Limited, so the effect of electrostatic discharge protection is not good, which is the disadvantage of using a floating base NPN bipolar junction transistor as an electrostatic discharge protection circuit.

Please refer to FIG. 2 , which is a circuit diagram of a conventional ESD protection circuit for metal oxide semiconductor transistors. As shown in Figure 2, a metal oxide semiconductor transistor (MOS) is used as an electrostatic discharge protection circuit. The gate of the metal oxide semiconductor transistor is connected to its source and then grounded, and its drain is grounded. ) is connected to an input attenuator of an internal circuit or a voltage source attenuator, and when the input attenuator or voltage source attenuator of the internal circuit is disturbed by an electrostatic discharge pulse, the metal oxide semiconductor transistor will conduct the electrostatic current grounded. The advantage of using a grounded metal oxide semiconductor transistor is that the metal oxide semiconductor transistor can draw a larger current, which is better for electrostatic discharge protection. However, due to the large input capacitance of the metal oxide semiconductor transistor, the metal oxide semiconductor transistor Semiconductor transistors operate at slower speeds and may not provide complete protection for internal electronic systems, a disadvantage of using grounded-gate MOS transistors as ESD protection circuits.

It can be seen from the above that using a floating base NPN bipolar junction transistor as an ESD protection circuit has a fast operation speed but the effect of ESD protection is not good; and using a grounded metal oxide semiconductor transistor as an ESD protection circuit can Improve the disadvantages of floating base NPN bipolar junction transistors to obtain better electrostatic discharge protection effect, but the operating speed is limited due to the large input capacitance.

Other related technologies can refer to US Patent 5,530,612, US Patent 5,986,863, US Patent 6,028,758, US Patent 6,320,735, US Patent 6,400,540, US Patent Application 20020027755A1, European Patent 651,490, and European Patent 477,429.

Contents of the invention

Therefore, the main purpose of the present invention is to provide an NPN Darlington electrostatic discharge protection circuit to solve the above problems.

The invention provides an electrostatic discharge protection circuit, which includes an NPN Darlington circuit and an N-type metal oxide semiconductor transistor. The drain of the NMOS transistor is connected to the input terminal of the NPN Darlington circuit, the source of the NMOS transistor is connected to the control terminal of the NPN Darlington circuit, and the NMOS transistor is connected to the control terminal of the NPN Darlington circuit. The gate of the oxide semiconductor transistor is connected to the output terminal of the NPN Darlington circuit.

Description of drawings

Fig. 1 is the circuit diagram of the electrostatic discharge protection circuit of existing bipolar junction transistor;

2 is a circuit diagram of an electrostatic discharge protection circuit of an existing metal oxide semiconductor transistor;

Fig. 3 is the circuit diagram of electrostatic discharge protection circuit of the present invention;

4A and 4B are schematic diagrams of the element structure of the electrostatic discharge protection circuit of the present invention in a bipolar complementary transistor process;

5A and 5B are schematic diagrams of the element structure of the electrostatic discharge protection circuit of the present invention in a complementary transistor process;

Fig. 6 is the circuit diagram that the electrostatic discharge protection circuit of the present invention is connected to the voltage source attenuator; And

FIG. 7 is a circuit diagram of a complementary electrostatic discharge protection circuit of the present invention.

The reference signs in the accompanying drawings are explained as follows:

10 The electrostatic discharge protection circuit of the present invention

12 N-type metal-oxide-semiconductor transistors

14 The first NPN bipolar junction transistor

16 The second NPN bipolar junction transistor

18 1st resistor 20 2nd resistor

22 Input Attenuator 24 Voltage Source Attenuator

26 The complementary circuit of the electrostatic discharge protection circuit of the present invention

30 P-type substrate                                                                                                                                                                                                                       32  P-type epitaxial layer or N-type epitaxial layer

34 N+ buried layer 36 N well

38 P Well 40 N+ Pole

42 Insulation layer 50 P-type substrate

52 N deep well 54 P well

56 N+pole 58 Insulation layer

Detailed ways

Please refer to FIG. 3 , which is a circuit diagram of the electrostatic discharge protection circuit of the present invention. The electrostatic discharge protection circuit 10 of the present invention comprises an N-type metal oxide semiconductor transistor (NMOS) 12, a first NPN bipolar junction transistor (NPN BJT) 14, a second NPN bipolar junction transistor 16, a first resistor 18 and a second resistor 20. The collectors of the two NPN bipolar junction transistors 14 and 16 are connected together, and the emitter of the first NPN bipolar junction transistor 14 is connected to the base of the second NPN bipolar junction transistor 16. ), forming an NPN Darlington circuit (NPNDarlington circuit), the base of the first NPN bipolar junction transistor 14 is the control terminal of the NPN Darlington circuit, and its collector is the input terminal of the NPN Darlington circuit. The emitters of the two NPN bipolar junction transistors 16 are the output terminals of the NPN Darlington circuit. The drain (drain) of the NMOS transistor 12 is connected to the input end of the NPN Darlington circuit, and the gate (gate) of the NMOS transistor 12 is connected to the output of the NPN Darlington circuit terminal, and the source (source) is connected to the control terminal of the NPN Darlington circuit. The input end of this NPN Darlington circuit is connected to the input attenuator (I/P) 22 of an internal circuit, and its output end is connected to the ground point, and the first resistor 18 is connected to the base of the first NPN bipolar junction transistor 14 The second resistor 20 is connected between the base of the second NPN BJT 16 and the ground. When the input attenuator 22 of the internal circuit is disturbed by an electrostatic discharge pulse, the NMOS transistor 12 is immediately turned on, so that a part of the electrostatic current flows through the first resistor 18 to form a voltage drop at its two ends, This voltage drop drives the first NPN bipolar junction transistor 14 to conduct, and then makes a part of the electrostatic current pass through the second resistor 20 and forms another voltage drop at its two ends, and this voltage drop drives the second NPN bipolar junction transistor 16 to conduct Through this path, most of the electrostatic current is grounded through this path to achieve the effect of electrostatic discharge protection. In this embodiment, the emitter width of the second NPN bipolar junction transistor 16 is twice that of the first NPN bipolar junction transistor 14, mainly in order to achieve a better electrostatic discharge effect, while the first resistor 18 and the second The resistor 20 is only used to form a voltage drop to drive the NPN BJT to turn on, and the selected resistor value here is 500 ohms. The emitter widths of the first NPN bipolar junction transistor 14 and the second NPN bipolar junction transistor 16 and the resistance values of the first resistor 18 and the second resistor 20 can also select appropriate values according to actual needs, and all should belong to the scope of the present invention. range covered.

Please refer to FIG. 4A and FIG. 4B . FIG. 4A and FIG. 4B are schematic diagrams of the device structure of the ESD protection circuit of the present invention in a Bipolar Complementary Metal Oxide Semiconductor Transistor (BiCMOS) process. As shown in FIG. 4A, in the bipolar complementary metal-oxide-semiconductor transistor process, a P-type epitaxial layer (P-epi layer) or an N-type epitaxial layer is first formed on a P-type substrate (P-substrate) 30 layer (N-epilayer) 32, and then inject an N+ buried layer (N+buried layer) 34 on the epitaxial layer 32, form a P well (P well) 38 on the N+ buried layer 34, and the surroundings of the P well 38 Then implant an N well (NW+sink) 36 to form on the upper side of the N+ buried layer 34 in a manner surrounding the P well 38 to isolate the P well 38 from the P-type substrate 30, and finally implant the N+ pole (NW+) in the P well 38 +node)40. In the above structure, an NPN bipolar junction transistor uses the N+ electrode 40 as the emitter, the P well 38 as the base, and the N+ buried layer 34 as the collector, as shown in FIG. 4A . An NMOS transistor uses two N+ poles 40 as the drain and source, and an insulating layer 42 is formed on the channels of the two N+ poles 40 as the gate, as shown in FIG. 4B . The NMOS transistor in the P well 38 is isolated by the N well (NW+sink) 36 and the N+ buried layer 34, as shown in FIG. 3 by encircling the NMOS transistor 12 with a circle. . Because this embodiment adopts the above-mentioned special isolation structure, the NMOS transistor can be used as a trigger to drive the NPN Darlington circuit to achieve a better ESD protection effect.

Please refer to FIG. 5A and FIG. 5B . FIG. 5A and FIG. 5B are schematic diagrams of the device structure of the electrostatic discharge protection circuit of the present invention applied in a complementary metal-oxide-semiconductor transistor (CMOS) process. Likewise, in CMOS transistor technology, a deep Nwell 52 can also be used to isolate a P well 54 from a P-type substrate 50 . As shown in FIG. 5A , an N-deep well 52 is implanted on the P-type substrate 50 first, then a P-well 54 is implanted on the N-deep well 52 , and finally an N+ pole 56 is implanted in the P-well 54 . An NPN bipolar junction transistor uses the N+ pole 56 as the emitter, the P well 54 as the base, and the N deep well 52 as the collector, as shown in FIG. 5A . An NMOS transistor uses two N+ poles 56 as the drain and source, and forms an insulating layer 58 above the channels of the two N+ poles as the gate, as shown in FIG. 5B . The NMOS transistors in the P-well 54 are isolated by the N-deep well 52 , which is represented by a circle surrounding the NMOS transistor 12 as shown in FIG. 3 .

Please refer to FIG. 6 . FIG. 6 is a circuit diagram of the ESD protection circuit connected to the voltage source attenuator 24 of the present invention. To simplify the description, the same components in FIG. 6 and FIG. 3 have the same functions and use the same reference numerals. In Fig. 3, the input end of this NPN Darlington circuit is connected to the input attenuator 22 of internal circuit, when the input attenuator 22 of this internal circuit is disturbed by an electrostatic discharge pulse, the electrostatic discharge protection circuit 10 of the present invention immediately Actuation grounds electrostatic currents. Similarly, the input terminal of the NPN Darlington circuit in the electrostatic discharge protection circuit 10 of the present invention can also be connected to a voltage source attenuator 24, when the voltage source attenuator 24 is disturbed by an electrostatic discharge pulse, the electrostatic discharge protection of the present invention The circuit 10 will immediately start to direct the electrostatic current to ground. Generally, the human-body model (Human-Body Model, HBM) and the machine model (Machine Model, MM) are commonly used to simulate the situation of electrostatic discharge. An electrostatic discharge protection circuit can be known by measuring the HBM value or MM value. For the effect of electrostatic discharge protection, the larger the value of HBM or MM, the better the effect of electrostatic discharge protection. When an electrostatic discharge protection circuit is connected to an input attenuator of an internal circuit, the HBM value of the existing electrostatic discharge protection circuit is about 2.5KV, and the MM value is about 200V, while the HBM value of the electrostatic discharge protection circuit 10 of the present invention can reach 5.5KV, MM value can reach 500V. When an electrostatic discharge protection circuit is connected to a voltage source attenuator, the HBM value of the existing electrostatic discharge protection circuit is about 5KV, and the MM value is about 200V, while the HBM value of the electrostatic discharge protection circuit 10 of the present invention can reach 8KV, MM values up to 400V. It can be known from the above data that the ESD protection circuit 10 of the present invention can effectively achieve ESD protection.

Please refer to FIG. 7 , which is a circuit diagram of a complementary electrostatic discharge protection circuit of the present invention. In FIG. 3, if the ESD pulse enters from the voltage source, and the ESD current reaches the input attenuator 22 of the internal circuit through the ESD protection circuit through the ground point, the ESD protection effect may not be sufficient to meet higher requirements. As shown in Figure 7, if a circuit 26 composed of a PNP bipolar junction transistor and a P-type metal oxide semiconductor transistor is added with a complementary concept between the voltage source and the input attenuator 22 of the internal circuit, it is the same as that of Figure 3 The electrostatic discharge protection circuit 10 in the circuit is completely complementary, and when an electrostatic discharge pulse enters from the voltage source, it will directly reach the input attenuator 22 of the internal circuit through the circuit 26, thereby improving the effect of electrostatic discharge protection.

Compared with the prior art, the electrostatic discharge protection circuit 10 of the present invention uses the N well 36 and the N+ buried layer 34 to isolate the N-type metal oxide semiconductor transistor in the P well 38 in the bipolar complementary metal oxide semiconductor transistor process. In the complementary metal-oxide-semiconductor transistor process, the N-type metal-oxide-semiconductor transistor in the P-well 54 is isolated by the N-deep well 52, and the N-type metal-oxide-semiconductor transistor 12 is made by using this isolation technology as a trigger to drive the two transistors. The NPN Darlington circuit composed of two NPN bipolar junction transistors 14 and 16 enables the electrostatic current to pass quickly to achieve the effect of electrostatic discharge protection. It can be seen from the experimental results that no matter whether the ESD protection circuit 10 of the present invention is connected to the input attenuator 22 or the voltage source attenuator 24 of the internal circuit, it can achieve ESD protection more effectively than the prior art.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the spirit of the present invention shall fall within the scope of the patent of the present invention.

Claims (12)

1. ESD protection circuit, it comprises:

One NPN Darlington circuit, it has an input and an output, the output head grounding of this NPN Darlington circuit; And

One N type metal oxide semiconductor transistor, its drain electrode is connected in the input of this NPN Darlington circuit, the transistorized source electrode of this N type metal oxide semiconductor is connected in the control end of this NPN Darlington circuit, and the transistorized grid of this N type metal oxide semiconductor is connected in the output of this NPN Darlington circuit.

2. ESD protection circuit as claimed in claim 1, wherein this NPN Darlington circuit comprises two NPN bipolar junction transistors, each NPN bipolar junction transistor comprises a N+ buried layer, one P trap, be formed at the upside of this N+ buried layer, a N trap is formed at the upside of this N+ buried layer in the mode around this P trap, and a N+ utmost point, be formed at the upside of this P trap; And this N type metal oxide semiconductor transistor comprises a N+ buried layer, and a P trap is formed at the upside of this N+ buried layer, and a N trap is formed at the upside of this N+ buried layer in the mode around this P trap, and two N+ utmost points, is formed at the upside of this P trap.

3. ESD protection circuit as claimed in claim 2; wherein these two bipolar junction transistors and this N type metal oxide semiconductor transistor are formed on the P type substrate, and these two NPN bipolar junction transistors and the transistorized N trap of this N type metal oxide semiconductor are used for its P trap and this P type substrate isolation.

4. ESD protection circuit as claimed in claim 3 wherein be formed with a P type epitaxial loayer on this P type substrate, and these two bipolar junction transistors and this N type metal oxide semiconductor transistor is formed on this P type epitaxial loayer.

5. ESD protection circuit as claimed in claim 3 wherein be formed with a N type epitaxial loayer on this P type substrate, and these two bipolar junction transistors and this N type metal oxide semiconductor transistor is formed on this N type epitaxial loayer.

6. ESD protection circuit as claimed in claim 3, it forms via a bipolar CMOS transistor technology.

7. ESD protection circuit as claimed in claim 1, wherein this NPN Darlington circuit comprises two NPN bipolar junction transistors, and each NPN bipolar junction transistor comprises a N deep trap, one P trap, be formed at the upside of this N deep trap, and a N+ utmost point, be formed at the upside of this P trap; And this N type metal oxide semiconductor transistor comprises a N deep trap, and a P trap is formed at the upside of this N deep trap, and two N+ utmost points, is formed at the upside of this P trap.

8. ESD protection circuit as claimed in claim 7; wherein these two bipolar junction transistors and this N type metal oxide semiconductor transistor are formed on the P type substrate, and these two NPN bipolar junction transistors and the transistorized N deep trap of this N type metal oxide semiconductor can be with its P trap and this P type substrate isolation.

9. ESD protection circuit as claimed in claim 8, it forms via a CMOS transistor technology.

10. ESD protection circuit as claimed in claim 1, wherein the input of this NPN Darlington circuit is connected in the input of a circuit.

11. ESD protection circuit as claimed in claim 1, wherein the input of this NPN Darlington circuit is connected in a voltage source.

12. ESD protection circuit as claimed in claim 1, it also comprises:

A PNP Darlington circuit, its input is connected in the input of this NPN Darlington circuit, and the output of this PNP Darlington circuit is connected in a voltage source; And

One P-type mos transistor, its drain electrode is connected in the input of this PNP Darlington circuit, the transistorized source electrode of this P-type mos is connected in the control end of this PNP Darlington circuit, and the transistorized grid of this P-type mos is connected in the output of this PNP Darlington circuit.

Images