CN1335000A - Clock Synchronization Using System Frame Number in Telecommunication Network - Google Patents

Abstract

A telecommunications system (18) uses a System Frame Number (SFN) to synchronize a plurality of real time clocks (206) at one or more nodes in a network. Distributing system frame signals (e.g., pulses) from a signal source (210, 310) to a slave clock (206) having a clock that needs to be synchronized with a master clock_S) The processor (202). Main processor (202)_M,202_T) Sending a clock setup message (500) to the processor, the clock setup message comprising a reference master clock time (506) and a reference system frame number (504). The receiving processor receiving the clock set message resynchronizes its corresponding slave clock using the reference master clock time and the reference system frame number. In one approach, once the receiving processor obtains the reference system frame number, the clock setting message instructs the receiving processor to set its corresponding slave clock to the reference master clock time. In another mode, the clock set message informs the receiving processor of the actual master clock time at the reference system frame number, thereby allowing the receiving processor to calculate an adjusted slave clock time.

Description

Clock Synchronization Using System Frame Number in Telecommunication Network

field of invention

This invention relates to telecommunications and, in particular, to the synchronization of real-time clocks maintained by multiple processors of a telecommunications network.

Related technical and other considerations

Cellular telecommunication systems use radio links (eg air interfaces) between (mobile) user equipment units and base station (BS) nodes. A base station node has transmitters and receivers for making radio connections with a large number of user equipment units. A radio network controller node (also referred to as a base station controller [BSC] in some networks) connects (eg by landline or microwave) and manages one or more base station nodes. The radio network controller nodes are in turn connected to the core communication network via control nodes. Control nodes can take many forms, depending on the type of service or connected network. For connections of connection-oriented switched circuit networks such as PSTN and/or ISDN, the controlling node may be a Mobile Switching Center (MSC). Whereas for connections to packet-switched data services such as the Internet (for example), the control node can be a gateway data support node through which a connection to a wired data network, perhaps one or more service nodes, can be established.

Thus, a telecommunication connection between a mobile user equipment unit and another party (e.g. in the core communications network or another mobile user equipment unit) involves communication originating at the mobile unit and via a base station and a radio network controller (RNC). uplink and downlink in the opposite direction. In some types of telecommunications systems, control information and user information are transmitted in frames, both on the uplink and downlink.

In handling the transmission of frames and other activities, some nodes of the cellular telecommunications network employ multiple processors, each of which has a real-time operating system with a real-time clock. Synchronization of real time clocks is important in maintaining control over the telecommunications network and handling connections. Therefore, what is needed, and an object of the present invention, is a technique for synchronizing real time clocks in a telecommunications network.

Introduction to the invention

Telecommunications systems use system frame numbers to synchronize multiple real time clocks provided on one or more network nodes. Distribute system frame signals (eg pulses) from a signal source (eg oscillator) to devices or units with slave clocks that need to be synchronized with the master clock. The master processor sends a clock setting message to the processor, and the clock setting message includes a reference master clock time and a reference system frame number. Receiving processors receiving a clock set message resynchronize their respective slave clocks using the reference master clock time and the reference system frame number. In one approach, once the receiving processor obtains the reference system frame number, the clock set message instructs the receiving processors to set their respective slave clocks to the reference master clock time. In another manner, the clock setting message informs the receiving processor of the actual master clock time under the frame number of the reference system, thereby enabling the receiving processor to calculate and adjust the time of the slave clock.

The location of the main processor relative to the receiving processor varies according to different embodiments. For example, in one embodiment, the main processor and the receiving processor are located at the same node of the telecommunications network, such as a base station node. In such an embodiment, the main processor and the receiving processor may be located on different equipment boards in the same node of the telecommunications network. In another embodiment, the main processor and the receiving processors are located at different nodes of the telecommunication network, eg the main processor is located at a radio network controller node and one or more receiving processors are located at a base station node of the telecommunication network.

Brief introduction to the drawings

The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of a preferred embodiment thereof, which is illustrated in the accompanying drawings, in which reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

Figure 1 is a schematic diagram of an embodiment of a telecommunications system using the present invention.

FIG. 2 is a schematic diagram illustrating the use of the synchronization technique of the present invention in a base station.

Figure 3 is a schematic diagram illustrating the use of the synchronization technique of the present invention between a radio network controller (RNC) and a base station.

Fig. 4A is a flowchart illustrating a first way of using the clock setting message (CSM) of the present invention.

Fig. 4B is a flowchart illustrating a second way of using the clock setting message (CSM) of the present invention.

FIG. 5 is a diagram of an exemplary format of a clock setting message (CSM) of the present invention.

Detailed description of the invention

In the following description, for purposes of explanation and not limitation, specific details are given, such as specific structures, interfaces and techniques, in order to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the invention may be practiced in other embodiments that depart from these details. In other instances, detailed descriptions of well-known devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

FIG. 1 shows a telecommunications network 18 in which a user equipment unit 20 communicates with one or more base stations 22 over an air interface (eg, radio interface) 23 . The base stations 22 are connected by landlines (or microwave) to a radio network controller (RNC) 24 [also called a base station controller (BSC) in some networks]. A radio network controller (RNC) 24 is in turn connected to a circuit-switched telephone network (PSTN/ISDN) represented by a cloud 28 through a control node called a mobile switching center 26 . In addition, the Radio Network Controller (RNC) 24 is connected to the Serving GPRS Support Node (SGSN) 25, and is connected to the Gateway GPRS Support Node (GGSN) 30 through the backbone network 27, and is established with the cloud-shaped block 32 through the GGSN 30. Connections to packet-switched networks (eg Internet, X.25 external networks).

As will be understood by those skilled in the art, when a user equipment unit 20 participates in a mobile telephone connection, signaling information and user information from the user equipment unit 20 are sent to one or more mobile telephone connections via the air interface 23 on a designated radio channel. base station 22. A base station has a radio transceiver capable of sending and receiving radio signals participating in a connection or session. For information on the uplink from the user equipment unit 20 to the other parties involved in the connection, the base station converts the radio acquired information into a digital signal which is forwarded to a radio network controller (RNC) 24 . Since user equipment unit 20 may move geographically and may be handed off relative to base station 22, radio network controller (RNC) 24 coordinates the participation of multiple base stations 22 that may participate in a connection or session. On the uplink, a radio network controller (RNC) 24 collects user information frames from one or more base stations 22 to establish a connection between the user equipment unit 20 and other parties, whether on PSTN/ISDN 28 or on a packet switching network (such as the Internet) 32.

The exemplary embodiments presented here happen to employ Code Division Multiple Access (CDMA), where information transmitted between a base station and a particular mobile station is modulated by a mathematical code (such as a spreading code) so that the information is shared with Other mobile station information of the frequency is distinguished. In CDMA, therefore, the individual radio links are distinguished on the basis of codes. Various aspects of CDMA are described in "Applications of CDMA in Wireless/Personal Communications" by Garg, Vijay K, et al. (Prentice Hall (1997)). Considering the diversity aspects of CDMA, user equipment unit 20 in Figure 1 is depicted as being associated with a plurality of base stations 22 (eg, base station ₂₂₁ and base station ₂₂₂ ).

The invention relates in particular to the synchronization of real-time clocks in a telecommunications network 18 in which information is transmitted both on the uplink and downlink in the form of frames or packets. Each frame is numbered consecutively to include an identifying frame number (FN). The frame number (FN) is in turn based on the system frame number (SFN) maintained at both the base station 22 and the radio network controller (RNC) 24 .

The SFN is synchronized between a radio network controller (RNC) 24 and base stations 22 . In this regard, each base station 22 has a system frame number (SFN) oscillator which distributes the system frame number to all boards of the base station 22 . Thus, when a base station 22 starts up, the SFN oscillator is synchronized with a radio network controller (RNC) 24, and each base station 22 then maintains its own SFN counter with this SFN oscillator. Subsequently, when the radio network controller (RNC) 24 sends frames of user data to the base station 22 for eventual forwarding to the user equipment unit 20, each frame is tagged with a frame number (FN). This frame number (FN) is actually derived from the SFN, eg modulo 72 of the SFN. Using this frame number FN and the SFN held by the base station 22, the base station 22 can transmit a frame at a specified time.

The synchronization of real-time clocks of the present invention is applicable to multiple embodiments, a first example is given in FIG. 2 . In particular, FIG. 2 shows a representative base station 22 of the telecommunications network 18 . The example base station 22 in FIG. 2 includes a plurality of units or equipment boards 200 _M , 200 _S1 , . . . 200 _Sn . Each device board 200 has a board processor 202 running a real-time operating system (RTOS) 204 with a real-time clock 206 .

In FIG. 2, device board _200M is named "motherboard" due to the fact that its real-time clock _206M is considered to be the master real-time clock (master clock _206M ). Furthermore, in the illustrated embodiment, device board _200M includes a system frame signal source, namely SFN oscillator 210 . Processor _202M of motherboard _200M communicates with processors of other device boards 200 via interface 212 and through control bus 214 .

In the example of FIG. 2, unlike the master device board _200M , the device boards 200 are referred to herein as slave boards and are only used for their respective roles in the synchronization of the present invention. Considering synchronization, the real-time clocks 206 on the slave boards 200 _S1 to 200 _Sn are all slaved to the master clock 206 _M . In addition, the slave boards 200 _S1 to 200 _Sn receive the system frame signal from the SFN oscillator 210 through the SFN signal line 216 .

In the illustrated embodiment, the SFN oscillator 210 outputs pulses, which occur every 10 milliseconds in the illustrated embodiment. The pulses from the SFN oscillator 210 are supplied to the SFN counter 220 on each slave board _200S1 to _200Sn . SFN counter 220 maintains a count of pulses comprising the system frame signal received on SFN signal line 216 . In addition, the main processor _202M receives and counts system frame signals. When the main processor 200M determines that the SFN oscillator 210 has sent out a complete set of system frame signals, the main processor _200M sends out a reset signal on the reset line 222 .

Each of the slave boards _200S1 to _200Sn has one or more characteristic functions, generally represented by function blocks _230S1 to _230Sn located on the corresponding board. Each of the functional blocks _230S1 to _230Sn may perform one or more base station functions. For example, the functional block 230 _S1 may be a transmitter/receiver for enabling communication over the air interface 23 . The functional block _230Sn may be used as an interface to another node of the telecommunications network 18, such as eg a radio network controller (RNC) 24, in which case the device board _200Sn acts as an expansion board. Similarly, several equipment boards 200 of the base station 22 serve as transmitter/receiver boards. However, the mix of specific identities and functions provided by the base station 22 is not closely related to the present invention, and the above functions are provided for illustration only.

It should be understood that FIG. 2 does not illustrate the transmission of user data frames between the equipment boards 200 of the base station 22 and the like. This transfer of user data frames may be done in any conventional manner, such as by encapsulation in ATM frames, for example. Accordingly, in some embodiments, a switch, such as an ATM switch, may be provided to facilitate the transfer of user data frames between equipment boards of base station 22, for example.

The present invention seeks to synchronize the slave clock _206S with the master clock _206M . It is assumed that the master clock _206M has been accurately maintained or maintained (eg, by the radio network controller (RNC) 24), and that the master processor's SFN counter has been properly synchronized (eg, since it was turned on). The synchronization of the present invention utilizes a System Frame Number (SFN) maintained on a plurality of device boards 200 of the telecommunications system 18 . In this regard, SFN oscillator 210 outputs a pulse on line 216 as described above. The pulses on line 216 are counted by SFN counter 220, each device board 200 thus knows the frame number (FN) and SFN of each user data frame, so device board 200 can send the frame over the air interface at the appropriate moment. Additionally, the main processor _202M counts system frame pulses and determines when the system frame number should be reset to zero. When the main processor _202M determines that the system frame number should be reset to 0, the main processor _202M sends a reset signal on line 222 .

According to the present invention, the master processor _202M sends a clock setting message (CSM) 500 on the control bus 214 to the receiving processor _202S of each slave board _200S1 to _200Sn . FIG. 5 shows an example format of a representative clock setting message (CSM) 500 . A clock setting message (CSM) 500 includes a message type identification field 502 that distinguishes a clock setting message CSM transmitted on the control bus 214 from other types of messages. Additionally, Clock Set Message (CSM) 500 includes a reference system frame number in field 506 (referred to as reference system frame number field 504 ), and a reference master clock time in field 504 (referred to as reference master clock time field 506 ). The reference master clock time field 506 specifies the reference master clock time in hours, minutes, seconds format (hour.minute.second). An address field is also required in the clock setting message (CSM) 500 if the control bus 214 uses addressing rather than dedicated connections between the master board _200M and the respective slave boards _200S1 to _200Sn . Other fields may also be included, such as a parity field or a checksum field.

In a first mode of the invention, once a receiving processor detects that its respective SFN counter 220 has reached a certain amount equal to the value contained in the reference system frame number field 504 (eg SFN=X in the example), The clock set message (CSM) 500 then instructs the receiving slave processor _202S to set its respective slave clock _206S to the specified real time (as specified in the reference master clock time field 506).

FIG. 4A shows a first mode of the present invention, wherein in step 4A-1, main processor _202M prepares and sends (via interface _212M and through control bus 214) a clock setting message (CSM) having the format shown in FIG. 5 500. Step 4A-2 of FIG. 4A illustrates the slave processor _202S receiving and processing the clock setting message, which includes, for example, storing the received values in the reference system frame number field 504 and the reference master clock time field 506. The SFN oscillator 210 continues to provide the system frame signal (pulses) on the SFN signal line 216, eventually sending a pulse that will be counted as SFN=X (step 4A-3). Slave processors _202S monitor the count of system frame pulses maintained by their respective SFN counters 220 . As represented by step 4A-4, when the count of the SFN counter 220 reaches the value contained in the reference system frame number field 504 (e.g., SFN=X), the associated slave processor 202 resets its slave clock _206S to The time specified in the clock setting message (CSM) 500. In this way, when the count number of the system frame number signal maintained by the SFN counter 220 has a predetermined relationship with the value in the reference system frame number field 504, the slave clock _206S is reset to the time carried in the reference master clock time field 506. minutes.seconds value. In other words, the slave clock _206S is reset to the actual time specified in the reference master clock time field 506 of the clock setting message (CSM) 500 once it reaches SFN=X specified in the reference system frame number field 504 .

In a second mode of the invention, a Clock Set Message (CSM) 500 informs the receiving processors on the slave boards 200 _S1 to 200 _Sn that the actual master clock time (as specified in the reference master clock time field 506) occurs on the reference system The reference system frame number carried in the frame number field 504 . In said second mode, the receiving processor calculates the adjusted slave clock time at which its associated slave clock _206S is to be reset.

FIG. 4B shows a second mode of the present invention, wherein in step 4B-1, main processor _202M prepares and sends (via interface _212M and through control bus 214) a clock setting message (CSM) having the format shown in FIG. 5 500. Step 4B-2 of FIG. 4B shows that the slave processor _202S receives and processes the clock setting message, which includes, for example, storing the received values in the reference system frame number field 504 and the reference master clock time field 506. Step 4B-3 shows the SFN oscillator 210 providing a system frame signal (pulse) on the SFN signal line 216 that will be counted as SFN=Y. Then, in step 4B-4, when knowing the current system frame number SFN=Y, the slave processor _202S utilizes the current system frame number SFN=Y, that is, the value in the reference system frame number field 504, and the reference master clock time The actual time value in field 506 is used to calculate the adjusted slave clock time. Thus, the adjusted slave clock time calculated in step 4B-4 is not the actual time value in the reference master clock time field 506 , but another value calculated using the actual time value in the reference master clock time field 506 . In other words, knowing that the actual time of the master clock ₂₀₆₂₄ is the value stored in the reference master clock time field 506 at the particular system frame number stored in the reference system frame number field 504, the slave processor 202 can take the value stored in the current system frame No. SFN=Y to calculate the master clock time. The calculation is simplified by the fact that pulses of a system frame occur on line 216 at known intervals (eg, at intervals of every 10 milliseconds in the illustrated embodiment). Since the adjusted slave clock time was calculated in step 4B-4, in step 4B-5 the slave processor 202 sets its associated slave clock _206S to the adjusted slave clock time, thereby achieving synchronization.

Although FIG. 4B happens to depict the transmission of the system frame signal to SFN=Y (step 4B-3) following the sending of the clock setting message (CSM) 500 in step 4B-1, it should be understood that in FIG. 4B, step 4B-3 may be before step 4B-1. In other words, what is important in the second mode of the present invention is that the slave processor 202 knows the current system frame number when performing the calculation of step 4B-4. It does not matter whether the knowledge or update of the current system frame number is obtained before or after receiving the clock setting message (CSM) 500 as long as the exact current system frame number is used.

FIG. 3 provides a second representative example embodiment for illustrating real-time clock synchronization of the present invention. In particular, FIG. 3 illustrates a situation where a radio network controller ( _RNC ) 24 maintains a master clock 306 _M for synchronizing slave clocks 306 _S located at one or more base stations 22 ₁ through 22 _q .

The master clock _306M resides on a timing board _300T of the radio network controller (RNC) 24, specifically as part of a real-time operating system (RTOS) _304T of a processor _302T located on the timing board 300T. In a similar manner to the mainboard _200M in FIG. 2 , the timing board _{300T includes} an interface _312T via which the processor _302S communicates with the processor of the base station 22 via a control line 314 . The timing board _300T also has an SFN oscillator 310 that outputs a system frame signal (pulse) in a similar manner to the SFN oscillator 210 in FIG. 2 .

The timing board 300 _T is shown with a port 313 _T through which communication is established with the rest of the Radio Network Controller (RNC) 24 via a switch 315 . Various types of information are conveyed between timing board _300T and switch 315 through port _313T , including system frame signals and reset signals corresponding to those carried on lines 216 and 222 in FIG. 2 . The switch 315 is used to connect different units of the radio network controller (RNC) 24, such units include (in addition to the timing board _300T ) the diversity switching unit 340, the control node interface 342 (for example, for the interface to the MSC 26 or the SGSN 25) and Base station interfaces 344 ₁ to 344 _q (these interfaces are connected to respective base stations 22 ₁ to 22 _q , for example by land lines).

Each base station 22 is connected to a radio network controller (RNC) 24 through an expansion board 350 . As previously mentioned, expansion board 350 is just one of several equipment boards that may be placed on base station 22 . The expansion board 350 receives the system frame signal from the SFN oscillator _310T of the radio network controller (RNC) 24 and the reset signal from the processor _302T and, in one embodiment, provides such signals to the Each of the plurality of device boards 200 . In FIG. 3 , base station 22 ₁ is shown with equipment boards 200 _1-S1 to 200 _1-Sn and base station 22 _q is shown with equipment boards 200 _q-S1 to 200 _q-Sk .

_The equipment boards ₂₀₀ of the base station ₂₂ of FIG _. The equipment boards of the base station of Figure 2 are similar. Port 354 manages communication between switch 352 and the constituent elements of device board 200 , which include SFN counter 220 and processor 202 . Furthermore, for each device board 200 , the processor 202 is connected to its corresponding control line 314 through the interface 212 . Control line 314 carries a clock setting message (CSM) 500, which for the embodiment of FIG. 3 may have the same example format as shown in FIG. 5 and discussed above.

In the embodiment of FIG. 3, all equipment boards 200 of each base station 22 can be directly connected to each other in the manner described for equipment boards _2001-S1 and in any of the manners described above with respect to FIG. 4A or FIG. 4B. The slave clocks 206 are synchronized. That is, each device board 200 can receive the system frame signal of the SFN oscillator 310 _T of the radio network controller (RNC) 24 and the clock setting message (CSM) 500 of the radio network controller (RNC) 24 . In this case, the control line 314 is connected to each device board 200 of the base station which has a slave clock 106 which requires synchronization and which requires an address field in the clock setting message (CSM) 500 specifying the base station 22 to the specific device board 200 to which the clock setting message (CSM) 500 is provided.

On the other hand, the master clock 306 _T of the radio network controller (RNC) 24 may first be used to synchronize the predetermined slave clock 206 of one of the equipment boards 200 of each base station (eg, the equipment board 200 _1-S1 of the base station 22 ₁ ). , and then use the first synchronized slave clock 206 as an auxiliary master clock for synchronizing the remaining slave clocks 206 on other device boards 200 of the same base station 22 . After initial synchronization, a radio network controller (RNC) 24 monitors and performs phase corrections on the secondary master clock. In this possible operation, each device board 200 of the base station 22 receives the system frame signal directly from the SFN oscillator 310 _T , but the Clock Set Message (CSM) 500 is forwarded from the device board 200 with the first synchronized slave clock to other boards of the base station 22 for synchronization of the remaining slave clocks on other device boards 200 .

As noted above, the clock setting message (CSM) 500 of the embodiment of FIG. 3 can operate in either the manner of FIG. 4A or the manner of FIG. 4B. Such an approach is understood with reference to the previous discussion of FIG. 2 .

The embodiment of Figure 3 is illustrated with nodes employing switches for routing information through the nodes. An example of such a switch would be an ATM switch for routing ATM cells through a node. It should be understood that other types of routing techniques may be used, or that (alternatively) the signals concerned herein may be applied directly or otherwise from the radio network controller (RNC) 24 to the appropriate equipment boards 200 in the base station 22, if desired. In addition, it should be understood that intra-node switching can also be used in the embodiment of FIG. 2, although it is not specifically described here.

From the foregoing it is also possible to understand how the master processor, and thus the master clock, can be located in a control node of the telecommunications network 18, such as in the mobile switching center 26. In such a case, the master processor is used to reset the slave clocks in subordinate nodes (eg, radio network controller (RNC) 24 and/or base station 22).

The present invention advantageously facilitates accurate synchronization of real time clocks among nodes, and by exploiting another feature of the telecommunications network 18 (SFN), even among multiple nodes of the telecommunications network 18 . Accordingly, the synchronization of the present invention allows a real-time operating system (RTOS) to precisely time-stamp events occurring in the communication network 18 . These events may be, for example, alarm reports sent to other nodes, or log events recorded in log files, for example, when debugging the system.

Although the invention has been described in connection with what is presently considered to be the most practical and best embodiment, it should be understood that the invention is not limited to the disclosed embodiment, but instead the invention covers every aspect included within the spirit and scope of the appended claims. Modified and equivalent configurations.

Claims (22)

1. a telecommunications network comprises:

Primary processor with master clock;

Receiving processor with slave clock;

Impose on the System Frame Number signal source of described receiving processor;

Wherein, described primary processor tranmitting data register is provided with message and gives receiving processor, and described clock setting message comprises with reference to master clock time and frame of reference frame number; And

Wherein, described receiving processor utilizes described with reference to master clock time and the synchronous more described slave clock of described frame of reference frame number.

2. the device of claim 1 is characterized in that: in case described receiving processor obtains described frame of reference frame number, described clock setting message just indicates the described slave clock of described receiving processor to be set to specify in real time.

3. the device of claim 2 is characterized in that also being included in the counter of in the described receiving processor described System Frame Number signal being counted; Wherein when the count number of System Frame Number signal and described frame of reference frame number had predetermined relationship, described receiving processor was set to described slave clock described with reference to the master clock time.

4. the device of claim 1 is characterized in that: described clock setting message is given described receiving processor the actual master clock time announcement under the described frame of reference frame number, described receiving processor can be calculated adjust the slave clock time.

5. the device of claim 1 is characterized in that described primary processor and described receiving processor are positioned at the same node of described telecommunications network.

6. the device of claim 5 is characterized in that the same node of described telecommunications network is a base-station node.

7. the device of claim 5 is characterized in that described primary processor and described receiving processor are positioned at the distinct device plate of the same node of described telecommunications network.

8. the device of claim 1 is characterized in that described primary processor and described receiving processor are positioned at the different nodes of described telecommunications network.

9. the device of claim 8, it is characterized in that: described primary processor is positioned at the radio network controller node, and described receiving processor is positioned at the base-station node of described telecommunications network.

10. the device of claim 8, it is characterized in that: described primary processor is positioned at the radio network controller node; First receiving processor is positioned at first base-station node; Second receiving processor is positioned at second base-station node.

11. the device of claim 1 is characterized in that described System Frame Number signal source is an oscillator.

12. a method of operating the cellular telecommunication system of particular type, in the cellular telecommunication system of described particular type, primary processor keeps master clock and System Frame Number is utilized, and described method comprises:

Described primary processor tranmitting data register is provided with message and gives receiving processor, and described clock setting message comprises with reference to master clock time and frame of reference frame number;

Described receiving processor utilizes described with reference to master clock time and the synchronous more described slave clock of described frame of reference frame number.

13. the method for claim 12 is characterized in that: in case described receiving processor obtains described frame of reference frame number, described clock setting message just indicates the described slave clock of described receiving processor to be set to specify in real time.

14. the method for claim 13 is characterized in that also comprising:

To described receiving processor transmitting system frame number signal periodically;

In described receiving processor, described System Frame Number signal is counted; And, when the count number of System Frame Number signal and described frame of reference frame number have predetermined the relation,

Described slave clock is set to described with reference to the master clock time.

15. the method for claim 12 is characterized in that described clock setting message gives described receiving processor the actual master clock time announcement under the described frame of reference frame number, described receiving processor can be calculated adjust the slave clock time.

16. the method for claim 15 is characterized in that also comprising:

Prepare described clock setting message, thus when described System Frame Number is described frame of reference frame number, in the described clock setting message described with reference to the master clock time be the actual master clock time;

To described receiving processor transmitting system frame number signal periodically;

Keep the current counting of described System Frame Number signal at described receiving processor; And

Utilize the described current counting of described System Frame Number signal, described frame of reference frame number and describedly calculate the described adjustment slave clock time with reference to the master clock time.

17. the method for claim 12 is characterized in that also comprising: the same node that described primary processor and described receiving processor is placed described telecommunications network.

18. the method for claim 17 is characterized in that the same node of described telecommunications network is a base-station node.

19. the method for claim 12 is characterized in that also comprising: the distinct device plate that described primary processor and described receiving processor is placed the same node of described telecommunications network.

20. the method for claim 12 is characterized in that also comprising: the different nodes that described primary processor and described receiving processor placed described telecommunications network.

21. the method for claim 20 is characterized in that also comprising: described primary processor is placed the radio network controller node, and described receiving processor is placed the base-station node of described telecommunications network.

22. the method for claim 20 is characterized in that also comprising:

Described primary processor is placed the radio network controller node;

First receiving processor is placed first base-station node; And

Second receiving processor is placed second base-station node.

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