[go: up one dir, main page]

CN1332329C - Control chip for controlling access to external memory module and control method thereof - Google Patents

Control chip for controlling access to external memory module and control method thereof Download PDF

Info

Publication number
CN1332329C
CN1332329C CNB2004100634520A CN200410063452A CN1332329C CN 1332329 C CN1332329 C CN 1332329C CN B2004100634520 A CNB2004100634520 A CN B2004100634520A CN 200410063452 A CN200410063452 A CN 200410063452A CN 1332329 C CN1332329 C CN 1332329C
Authority
CN
China
Prior art keywords
signal
terminal module
module
dynamic selection
termination
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB2004100634520A
Other languages
Chinese (zh)
Other versions
CN1588336A (en
Inventor
叶碧云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Via Technologies Inc
Original Assignee
Via Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Technologies Inc filed Critical Via Technologies Inc
Priority to CNB2004100634520A priority Critical patent/CN1332329C/en
Publication of CN1588336A publication Critical patent/CN1588336A/en
Application granted granted Critical
Publication of CN1332329C publication Critical patent/CN1332329C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Landscapes

  • Dram (AREA)
  • Information Transfer Systems (AREA)

Abstract

A control chip for controlling access to an external storage module, which performs reading operation on a data source device during a reading period, at least comprises a terminal module and a decision unit; the terminal module is coupled with the data source device through the memory bus and used for matching the impedance of the memory bus; the decision unit decides whether to start the terminal module according to the termination signal and the dynamic selection signal; when the termination signal and the dynamic selection signal are enabled, the decision unit starts the terminal module only in the reading period.

Description

The control chip and the control method thereof of control access external storage module
Technical field
The present invention is relevant for a kind of control chip, particularly relevant for a kind of control chip with Dynamic OD T (On DieTerminator) function.
Background technology
In general computer system, its inside has many chips.Each chip utilizes bus to be connected to each other, in order to the chip chamber Data transmission.Fig. 1 represents the synoptic diagram of computer system.Computer system 10 has comprised System on Chip/SoC and data path chip, generally is called north bridge (North Bridge) 12 and south bridge (South Bridge) 13, and the origin that is referred to as " bridge " links together a plurality of different bus for it.
North bridge 12 is as the tie point of central processing unit 11, memory module 14, graphics controller 15 and south bridge 13.North bridge 12 is transferred to memory bus 124, AGP graphics bus 126 with cpu bus 122, and and south bridge 130 between exclusive interconnecting channel 128.
South bridge 13 briefly combines many outputs and goes into (being called for short I/O) controller, and the interface of different peripheral units and bus is provided, and by carrying out the transfer of data between exclusive interconnecting channel 128 and the north bridge 12.For instance, south bridge 130 provides ide interface 17, usb 18.ROM-BIOS (basicinput-output system; BIOS) 16 can directly be connected to south bridge 130.
To be example below, the data transfer mode of chip chamber will be described with north bridge and memory module.Fig. 2 represents the connection diagram of north bridge and memory module.As shown in the figure, memory bus 124 is utilized data line D 1-D nTransmit the data-signal between north bridge 22 and the memory module 24.
When memory module 24 is passed through memory bus 124 data signal to north bridge 22, because data line D 1-D nThe impedance meeting make data-signal to be received by north bridge 22 fully, and at data line D 1-D nLast formation reflex.
Reflex will cause north bridge 22 need repeatedly receive data line D 1-D nOn data-signal, the logic level of the data-signal that can judge rightly out.Thereby make that the time of data transmission is elongated, or influence the signal of back, and cause operation mistake.
For reducing reflex, conventional way connects a terminal module 28 in the terminal of memory bus 124.Wherein, terminal module 28 has terminal unit T 1-T n, connect the data line D of memory bus 124 respectively 1-D n, in order to matched data line D 1-D nImpedance.In addition, determine the logic level of data-signal at short notice in order to make north bridge 12, so with data line D 1-D nLevel be set in a datum.Therefore, also utilize terminal unit T 1-T nBleeder circuit setting data line D 1-D nLevel.
When memory module 24 data signal during, then need at data line D near north bridge 22 to north bridge 22 1-D nTerminal couple terminal unit, in order to reduce data-signal that memory module 24 exported at data line D 1-D nOn the reflex that taken place.When north bridge 22 data signal during, then need at data line D near memory module 24 to memory module 24 1-D nTerminal couple terminal unit, in order to reduce data-signal that north bridge 22 exported at data line D 1-D nOn the reflex that taken place.
Owing in the computing machine system, have various transmission lines, if the two ends of every transmission lines all need couple terminal unit, will cause the increase of computer system costs, and make the interior spendable space of computer system diminish.
Therefore, Chang Gui settling mode is incorporated into terminal module in the chip.When chip internal designs a terminal module, then be called ODT (On Die Terminator).Fig. 3 represents to have the chip internal synoptic diagram of ODT function.With the north bridge is example, and the terminal module 326 of north bridge 32 inside has terminal unit T 1-T n, in order to matched data line D 1-D nImpedance.The user can set whether start the ODT function by BIOS, and BIOS sets the deposit unit 324 of north bridge inside by south bridge then.
When the user stopped the ODT function, then the BIOS forbidden storage was in the finishing signal S of deposit unit 324 ODT, in order to end terminal unit T 1-T nInterior switch SW a 1-SWa n, SWb 1-SWb nWhen user's desire started the ODT function, then BIOS enabled the finishing signal S that is stored in deposit unit 324 ODT, in order to conducting terminal unit T 1-T nInterior switch SW a 1-SWa n, SWb 1-SWb nTherefore, terminal unit T 1-T nInterior resistance R a 1-Ra nAnd Rb 1-Rb nBut setting data line D 1-D nLevel, and matched data line D 1-D nImpedance.Receiving element 322 is by terminal unit T 1-T nReceive the data-signal that memory module 34 is exported.
After the user starts the ODT function, terminal unit T 1-T nInterior switch SW a 1-SWa n, SWb 1-SWb nCan continue conducting.Make the electric current resistance R a that continues to flow through 1-Ra nAnd Rb 1-Rb n, cause the temperature of north bridge 12 to rise.When the temperature of chip rises, will cause bad influence to the operation of chip.
Summary of the invention
The invention provides a kind of control chip, when read cycle, memory module is carried out read operation, and when write cycle, the data original device is carried out write operation.Control chip of the present invention comprises at least, terminal module and decision package.Terminal module couples the Data Source device by memory bus, in order to the impedance of coupling memory bus.Decision package is according to finishing signal and Dynamic Selection signal, and whether decision starts terminal module.When finishing signal and Dynamic Selection signal were activated, then decision package only when read cycle, started terminal module.
Specifically, provide a kind of control chip of controlling access external storage module, include: a terminal module is connected to this memory module by a rambus, in order to mate the impedance of this rambus; An and decision package, be connected to this terminal module, in order to according to a finishing signal, a Dynamic Selection signal and a data read signal, whether decision starts this terminal module, and comprise a logical block, in order to export an output signal according to this finishing signal of logical block input end reception and the logic level result of this data read signal; And a judging unit, in order to the logic level according to this output signal and this Dynamic Selection signal, whether decision starts this terminal module.
The present invention also provides a kind of control method, in order to control the terminal module in the control chip.At first, receive a finishing signal and a Dynamic Selection signal.According to finishing signal and Dynamic Selection signal, whether decision starts terminal module then.When finishing signal and Dynamic Selection signal all were activated, then control chip only started terminal module in read cycle.
Specifically, provide a kind of method of control terminal module, include: receive a finishing signal, a Dynamic Selection signal and a data read signal; According to the logic level of this finishing signal and this data read signal, export an output signal; And according to the logic level of this output signal and this Dynamic Selection signal, whether decision starts this terminal module.
The present invention also provides a kind of computer system, comprises central processing unit, Data Source device, Basic Input or Output System (BIOS) and control chip at least.The Data Source device is in order to provide central processing unit required data.Basic Input or Output System (BIOS) is in order to provide a finishing signal and a Dynamic Selection signal.Control chip is coupled between central processing unit and the Data Source device, when a read cycle, the data original device is carried out read operation.
Wherein, control chip comprises terminal module and decision package at least.Terminal module, row couples the Data Source device by the storage remittance, in order to the impedance of coupling memory bus.Decision package is according to finishing signal and Dynamic Selection signal, and whether decision starts terminal module.When finishing signal and Dynamic Selection signal were activated, then decision package only when read cycle, started terminal module.
For above and other objects of the present invention, feature and advantage can also be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.
Description of drawings
Fig. 1 represents the synoptic diagram of computer system.
Fig. 2 represents the connection diagram of north bridge and memory module.
Fig. 3 represents to have the chip internal synoptic diagram of ODT function.
Fig. 4 represents the north bridge schematic internal view with Dynamic OD T function of the present invention.
Fig. 5 represents the truth table of decision package.
Fig. 6 represents decision package one embodiment of the present invention.
Symbol description
11: central processing unit; 12,22,32,42: north bridge;
13: south bridge; 14,24,34,44: memory module;
15: graphics controller; 16: ROM-BIOS;
The 17:IDE interface; The 18:USB interface;
The 122:CPU bus; 124: memory bus;
The 126:AGP graphics bus; 128: exclusive interconnecting channel;
28,326,426: terminal module;
T 1-T n: terminal unit; D 1-D n: data line;
322,422: receiving element;
324,424,425: deposit unit;
421: processing unit; 423: decision package;
B 1-B n: snubber assembly; 72: logical block;
74: judging unit.
Embodiment
When the chip with ODT function during to a Data Source device for reading data, this chip only needs just need start the ODT function when data-signal is imported, with the impedance of data line of coupling transmission of data signals, therefore the invention is characterized in provides Dynamic OD T the chip of function.When chip during, then start the ODT function at read cycle.When chip during, then stop the ODT function not at read cycle.Utilize the present invention just can reduce to drive the power attenuation that the ODT function is caused, make the temperature of chip descend.
The present invention can be applicable to the chip of any ODT of having function, for example north bridge, south bridge or memory module.Below will principle of work of the present invention be described at the data transmission situation between chip with ODT function and Data Source device (for example memory module).Fig. 4 represents the north bridge schematic internal view with Dynamic OD T function of the present invention.North bridge 42 comprises processing unit 421, receiving element 422, decision package 423, deposit unit 424,425 and terminal module 426.
Terminal module 426 has terminal unit T 1-T n, in order to matched data line D 1-D n Impedance.Receiving element 422 has snubber assembly B 1-B n, couple data line D respectively 1-D nProcessing unit 421 receives data line D by receiving element 422 1-D nData-signal.
When north bridge 42 was desired to read the data-signal of memory module 44, then processing unit 421 was enabled data read signal S in a read cycle EN, in order to memory module 44 is carried out read operation.When north bridge 42 no longer read the data-signal of memory module 44, then forbidden data read signal S ENWherein, memory module 44 is DRAM (Dynamic Random Access Memory; DRAM (Dynamic Random Access Memory)) or DDR is DRAM (Double Data Rate DRAM; Double Date Rate DRAM).
The user can be by the setting of BIOS, and whether decision starts ODT function and Dynamic OD T function.Then, BIOS can set the deposit unit 424,425 of north bridge inside by south bridge.Deposit unit 424 is in order to storage finishing signal S ODTDeposit unit 425 is in order to storage Dynamic Selection signal S SEL
Decision package 423 is according to finishing signal S ODT, Dynamic Selection signal S SEL, and data read signal S EN, control terminal unit T dynamically 1-T nInterior switch SW a 1-SWa nAnd SWb 1-SWb nWhen the user started the ODT function, then BIOS enabled the finishing signal S that is stored in deposit unit 424 ODTOtherwise,, then forbid finishing signal S ODTWhen the user opened Dynamic OD T function, then BIOS enabled the Dynamic Selection signal S that is stored in deposit unit 425 SELOtherwise, then forbid Dynamic Selection signal S SEL
Fig. 5 represents the truth table of decision package.Wherein, " 0 " representative forbids, " 1 " representative enables, " X " representative needn't consider (don ' t care), the Fig. 4 that please arrange in pairs or groups, in first row of Fig. 5, when the user does not start the ODT function, finishing signal S then ODTBe under an embargo, no matter Dynamic Selection signal S SELOr read signal S ENState why, the control signal S that decision package 423 is exported CONTo be under an embargo, in order to switch SW a by terminal module 426 1-SWa nAnd SWb 1-SWb nAt this moment, the ODT function of north bridge 42 is stopped.
In second row of Fig. 5, when the user starts the ODT function, but when stopping Dynamic OD T function, finishing signal S then ODTBe activated, and Dynamic Selection signal S SELBe under an embargo.Therefore, control signal S CONBe activated, in order to all switch SW a of conducting 1-SWa nAnd SWb 1-SWb nThis moment, the ODT function of north bridge 42 was activated.
Suppose that the user starts the ODT function, and when opening Dynamic OD T function, then finishing signal S ODT, and Dynamic Selection signal S SELAll be activated.
In the third line of Fig. 5,, then read signal S during data if north bridge 42 is at read cycle when (for example write cycle) ENBe under an embargo, make control signal S CONBe under an embargo, in order to end all switch SW a 1-SWa nAnd SWb 1-SWb nThis, the ODT function of north bridge 42 is stopped.
In the fourth line of Fig. 5, if north bridge 42 is when read cycle, data read signal S then ENBe activated, make control signal S CONBe activated, in order to all switch SW a of conducting 1-SWa nAnd SWb 1-SWb nAt this moment, just start the ODT function of north bridge 42.
From the above, when the user opened Dynamic OD T function, then the ODT function of north bridge 42 only when read cycle, just can be activated.When north bridge 42 during, then do not start the ODT function not at read cycle.
In order to verify Dynamic OD T function of the present invention, when the present invention controls finishing signal S on the same north bridge ODT, Dynamic Selection signal S SEL, and data read signal S ENState the time, can obtain the temperature regime under the different set.When the ODT function was not activated, then the temperature of north bridge was about 49.75 ℃.When the ODT function was activated and does not open Dynamic OD T function, then the temperature of this north bridge was about 61.21 ℃.When the ODT function was activated and also opens Dynamic OD T function, then the temperature of this north bridge was about 49.94 ℃.
From the above, when the ODT function by not starting to when starting, temperature will rise to 61.21 ℃ by 49.75 ℃ on same north bridge.But during as if use Dynamic OD T function, the temperature of north bridge only rises about 0.2 ℃.
Fig. 6 represents of the present invention and decision package one may embodiment.Decision package 423 has logical block 72 and judging unit 74.As finishing signal S ODTAnd data read signal S ENWhen being activated, then logical block 72 is enabled control signal S CONAs finishing signal S ODTOr data read signal S ENWhen being under an embargo, then logical block 72 is forbidden control signal S CONIn the present embodiment, logical block 72 is an AND door.
Judging unit 74 receives finishing signal S ODT, Dynamic Selection signal S SEL, and control signal S CONAs Dynamic Selection signal S SELWhen being under an embargo, then export finishing signal S ODTGive terminal module 426.As Dynamic Selection signal S SELWhen being activated, then export control signal S CONGive terminal module 426.In the present embodiment, judging unit 74 is a multiplexer.
Compare the present invention and routine techniques, the present invention has following some advantage:
One, reduces the online signal reflection phenomenon of transmission: utilize the terminal module in the chip, but the impedance of matched transmission line reduces reflex widely.
Two, reduce chip temperature: when opening the ODT function, the chip with Dynamic OD T function, its temperature is much smaller than the chip that does not have Dynamic OD T function.
In sum; though the present invention with a preferred embodiment openly as above; right its is not in order to limit the present invention; any those skilled in the art; under the situation that does not break away from the spirit and scope of the present invention; can carry out various also moving and modifications, so protection scope of the present invention is as the criterion when looking the claim restricted portion that is proposed.

Claims (13)

1.一种控制存取外部存储模块的控制芯片，包含有：1. A control chip for controlling access to an external storage module, comprising: 一终端模块，通过一内存总线连接至该存储模块，用以匹配该内存总线的阻抗；以及a terminal module connected to the memory module through a memory bus to match the impedance of the memory bus; and 一决策单元，连接到该终端模块，用以根据一终结信号、一动态选择信号以及一数据读取信号，决定是否启动该终端模块，并且包括A decision unit, connected to the terminal module, is used to decide whether to start the terminal module according to a termination signal, a dynamic selection signal and a data reading signal, and includes 一逻辑单元，用以根据逻辑单元输入端接收的该终结信号以及该数据读取信号的逻辑电平结果输出一输出信号；以及a logic unit for outputting an output signal according to the logic level result of the termination signal and the data read signal received at the input terminal of the logic unit; and 一判断单元，用以根据该输出信号以及该动态选择信号的逻辑电平，决定是否启动该终端模块。A judging unit is used for deciding whether to activate the terminal module according to the logic level of the output signal and the dynamic selection signal. 2.如权利要求1所述的控制存取外部存储模块的控制芯片，其中当该终结信号以及该动态选择信号同时被启用时，根据该数据读取信号决定是否启动该终端模块。2. The control chip for controlling access to an external memory module as claimed in claim 1, wherein when the termination signal and the dynamic selection signal are enabled at the same time, it is determined whether to activate the termination module according to the data read signal. 3.如权利要求2所述的控制存取外部存储模块的控制芯片，其中当位于一读取周期时，该数据读取信号启用，该终端模块被启动。3. The control chip for controlling access to an external memory module as claimed in claim 2, wherein when in a read cycle, the data read signal is enabled, and the terminal module is activated. 4.如权利要求2所述的控制存取外部存储模块的控制芯片，其中当不位于一读取周期时，该数据读取信号非启用，该终端模块不被启动。4. The control chip for controlling access to an external memory module as claimed in claim 2, wherein when not in a read cycle, the data read signal is disabled, and the terminal module is disabled. 5.如权利要求1所述的控制存取外部存储模块的控制芯片，其中当该终结信号启用，该动态选择信号非启用时，启动该终端模块。5. The control chip for controlling access to an external memory module as claimed in claim 1, wherein when the termination signal is enabled and the dynamic selection signal is disabled, the termination module is enabled. 6.如权利要求1所述的控制存取外部存储模块的控制芯片，其中当该终结信号非启用时，停用该终端模块。6. The control chip for controlling access to an external memory module as claimed in claim 1, wherein when the termination signal is inactive, the termination module is disabled. 7.如权利要求1所述的控制存取外部存储模块的控制芯片，其中还包含有一第一寄存单元，用以寄存该终结信号；以及一第二寄存单元，用以寄存该动态选择信号。7. The control chip for controlling access to an external memory module as claimed in claim 1, further comprising a first register unit for registering the termination signal; and a second register unit for registering the dynamic selection signal. 8.如权利要求1所述的控制存取外部存储模块的控制芯片，其中还包含有一处理单元，连结于该终端模块与该决策单元之间，用以发出该数据读取信号。8. The control chip for controlling access to an external memory module as claimed in claim 1, further comprising a processing unit connected between the terminal module and the decision-making unit for sending out the data read signal. 9.一种控制终端模块的方法，包含有：9. A method for controlling a terminal module, comprising: 接收一终结信号、一动态选择信号以及一数据读取信号；receiving a termination signal, a dynamic selection signal and a data reading signal; 根据该终结信号以及该数据读取信号的逻辑电平，输出一输出信号；以及outputting an output signal according to the logic level of the termination signal and the data read signal; and 根据该输出信号以及该动态选择信号的逻辑电平，决定是否启动该终端模块。According to the logic level of the output signal and the dynamic selection signal, it is determined whether to start the terminal module. 10.如权利要求9所述的控制终端模块的方法，其中当该终结信号以及该动态选择信号同时启用时，根据该数据读取信号决定是否启动该终端模块。10. The method for controlling a terminal module as claimed in claim 9, wherein when the termination signal and the dynamic selection signal are enabled simultaneously, it is determined whether to activate the terminal module according to the data read signal. 11.如权利要求10所述的控制终端模块的方法，其中当位于一读取周期时，该数据读取信号启用，而该终端模块被启动。11. The method for controlling a terminal module as claimed in claim 10, wherein when in a read cycle, the data read signal is enabled and the terminal module is activated. 12.如权利要求10所述的控制终端模块的方法，其中当不位于一读取周期时，该数据读取信号非启用，而该终端模块不被启动。12. The method for controlling a terminal module as claimed in claim 10, wherein when not in a read cycle, the data read signal is inactive, and the terminal module is not activated. 13.如权利要求9所述的控制终端模块的方法，其中当该终结信号启用，该动态选择信号非启用时，启动该终端模块。13. The method for controlling a terminal module as claimed in claim 9, wherein when the termination signal is enabled and the dynamic selection signal is disabled, the terminal module is activated.
CNB2004100634520A 2004-07-06 2004-07-06 Control chip for controlling access to external memory module and control method thereof Expired - Lifetime CN1332329C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2004100634520A CN1332329C (en) 2004-07-06 2004-07-06 Control chip for controlling access to external memory module and control method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2004100634520A CN1332329C (en) 2004-07-06 2004-07-06 Control chip for controlling access to external memory module and control method thereof

Publications (2)

Publication Number Publication Date
CN1588336A CN1588336A (en) 2005-03-02
CN1332329C true CN1332329C (en) 2007-08-15

Family

ID=34603821

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100634520A Expired - Lifetime CN1332329C (en) 2004-07-06 2004-07-06 Control chip for controlling access to external memory module and control method thereof

Country Status (1)

Country Link
CN (1) CN1332329C (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338979A (en) * 1991-09-05 1994-08-16 Unitrode Corporation Controllable bus terminator
CN1143490C (en) * 1994-11-23 2004-03-24 艾利森电话股份有限公司 A coupling device in a terminating circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5338979A (en) * 1991-09-05 1994-08-16 Unitrode Corporation Controllable bus terminator
US5338979B1 (en) * 1991-09-05 1996-02-13 Unitrode Corp Controllable bus terminator
US5521528A (en) * 1991-09-05 1996-05-28 Unitrode Corporation Controllable bus terminator
US5338979B2 (en) * 1991-09-05 1996-11-26 Unitrode Corp Controllable bus terminator
CN1143490C (en) * 1994-11-23 2004-03-24 艾利森电话股份有限公司 A coupling device in a terminating circuit

Also Published As

Publication number Publication date
CN1588336A (en) 2005-03-02

Similar Documents

Publication Publication Date Title
US10651849B2 (en) Transaction-based on-die termination
US9465545B2 (en) Memory card and host device thereof
KR100468634B1 (en) Data Transfer Control Device, Semiconductor Memory Device and Electronic Information Apparatus
US20100064083A1 (en) Communications device without passive pullup components
US7436204B2 (en) Apparatus and method for determining on die termination modes in memory device
JP4773742B2 (en) 2-wire interface between chips
US7259702B2 (en) Memory device
US6886066B2 (en) Method and apparatus for sharing signal pins on an interface between a system controller and peripheral integrated circuits
TWI752838B (en) Electronic device, memory system and transmission method
US8510485B2 (en) Low power digital interface
CN1332329C (en) Control chip for controlling access to external memory module and control method thereof
CN112041830B (en) Communication interface and packaging structure
CN1992070B (en) Buffer control circuit, control method thereof, and semiconductor memory device
CN108984440B (en) Method for reducing power consumption of integrated circuit and control circuit thereof
WO2019108278A1 (en) Power reduction technique during write bursts
CN118672486A (en) Memory system
US20050223126A1 (en) Buffer controller between memories and method for the same
JP2000099449A (en) Interface circuit for cpu data bus and memory control system provided with the same
HK1178311A (en) Daisy chain cascading devices

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CX01 Expiry of patent term

Granted publication date: 20070815

CX01 Expiry of patent term