HK1178311A - Daisy chain cascading devices - Google Patents

Description

Daisy chain cascade device

The application is a divisional application of Chinese application with the application number of 200680036482.X, the name of the invention is 'daisy chain cascade equipment', and the application date is 2006, 9 and 29.

Background

Computer-based systems are currently ubiquitous and are successfully incorporated into many devices used in everyday life, such as cell phones, laptops, automobiles, medical devices, personal computers, and the like. Generally, society has relied heavily on computer-based systems in dealing with everyday tasks, such as from simple tasks of balancing bills to relatively complex tasks such as forecasting weather. As technology evolves, more and more work is being transferred to computer-based systems. This also makes society increasingly dependent on these systems.

A typical computer-based system includes a system board and optionally one or more peripheral devices, such as a display unit, a memory unit, and the like. The system motherboard may contain one or more processors, storage subsystems, and other logic, such as a serial device interface, network device controller, hard disk controller, etc.

The type of processor used on a particular system board is typically dependent on the type of work being performed on the system. For example, systems that perform a defined set of tasks, such as monitoring emissions produced by an automotive engine and adjusting the air/fuel mixture to ensure that the engine is fully combusting the fuel, may employ simple dedicated processors dedicated to performing these tasks. On the other hand, systems that perform many different tasks, such as managing many users and running many different applications, may employ one or more complex processors that are general in nature and configured to perform high-speed calculations and process data to minimize response time to service user requests.

A memory subsystem is a memory used to hold information (e.g., instructions, data values) used by a processor. The storage subsystem typically contains control logic and one or more storage devices. The control logic is typically configured as an interface between the storage device and the processor to enable the processor to store information to and retrieve information from the storage device. The storage device holds the actual information.

Similar to processors, the type of device used on a storage subsystem is typically determined by the type of task being performed by the computer system. For example, a computer system may have the task of booting up and executing a set of infrequently changing software routines without the aid of a disk drive. At this point, the storage subsystem may employ a non-volatile device, such as a flash memory device, to store the software routines. Other computer systems can perform very complex tasks requiring large amounts of high-speed data storage to hold large amounts of information. At this point, the memory subsystem may employ high speed, high density Dynamic Random Access Memory (DRAM) devices to hold large amounts of information.

Currently, hard disk drives have a high density that can store 20 to 40 gigabytes of data, but are relatively bulky. However, flash memory (also known as solid state drive) is popular because of its high density, non-volatility, and small size relative to hard disk drives. Flash technology is based on EPROM and EEPROM technologies. The term "flash" is chosen because a large number of memory cells are erased in one operation, as opposed to one byte in an EEPROM. The advent of multi-level cells (MLC) has further increased the density of flash memory relative to single-level cells. Those skilled in the art will appreciate that flash memory may be configured as NOR flash memory or NAND flash memory, which has a higher density per given area due to its tighter storage arrangement. For the purposes of the following description, reference to flash memory may be considered to be NOR or NAND or other types of flash memory.

Devices in a storage subsystem are typically interconnected using a parallel interconnection mechanism. The mechanism involves connecting to the device in such a way that: address and data information and control signals are coupled to the device in a parallel fashion. Each device may include multiple input/outputs to facilitate the parallel transfer of data and address information and control signals to the devices.

Disclosure of Invention

A drawback associated with employing parallel connections in a storage subsystem is that a large number of interconnects are often required between devices to transfer information and signals between the devices in parallel. This increases the complexity of the boards that employ these storage subsystems. In addition, undesirable effects associated with a large number of interconnects, such as cross talk (crosstalk), tend to limit the performance of these subsystems. Also, the number of devices included in these subsystems may be limited due to signal transmission delays caused by the interconnections.

The techniques described herein overcome the above-described deficiencies by providing techniques for coupling devices in a daisy chain cascade arrangement that employs fewer and shorter connections than parallel interconnect implementations. Configuring the devices in a daisy-chain cascading arrangement may allow the devices to operate at a faster speed than a parallel interconnect implementation because fewer and shorter interconnects may be used so that the overall implementation is less susceptible to adverse effects, such as transmission delays and crosstalk. In addition, fewer and shorter connections tend to reduce implementation complexity. The reduced complexity further enables the subsystem comprising the device to be implemented on a smaller area, thus allowing the subsystem to occupy a smaller area.

In accordance with some aspects of the technology described herein, devices are coupled in a daisy chain cascade arrangement such that an output of a preceding device in the daisy chain cascade is coupled to an input of a subsequent device in the daisy chain cascade to provide for the transmission of information (e.g., data, address and command information) and control signals (e.g., enable signals) from the preceding device to the subsequent device.

In one embodiment of the present technology, each device in the daisy chain cascade includes a Serial Input (SI) and a Serial Output (SO). Information is input into the device through the SI of the device. Similarly, information is output by the SO device of the device. The SO of a device in the daisy chain cascade is coupled to the SI of the next device in the daisy chain cascade. Circuitry is provided in the device such that information input to one of the preceding devices in the daisy chain cascade via the SI of the device is communicated through the device and output from the device via the SO of the device. The information is then transferred to the SI of the next device in the daisy chain cascade through the connection between the SO of the previous device and the SI of the next device. The transferred information may be input to the next device through the SI of the next device.

Further, a clock signal is coupled to the devices in the daisy chain cascade. The clock signal is used by the devices to provide for the transfer of information from one device to the next in the daisy chain cascade.

In accordance with other aspects of the techniques described herein, control signals (e.g., enable signals) used by devices (e.g., to cause data to be input to the devices via the SI and to cause data to be output from the devices via the SO) are communicated between the daisy-chained devices as previously described. Here, the circuit is arranged to enable a control signal input to a preceding device in the daisy chain cascade to propagate through that device and pass from that device to the input of the next device in the daisy chain cascade via one output. The transmitted control signal is then input to the next device through the input.

In accordance with the principles of the present invention, a flash memory system may have multiple flash memory devices connected in series. A flash memory device in the system may include a serial data link interface having a serial input data port and a serial data output port, a control input port for receiving a first input enable signal, and a control output port for sending a second input enable signal. An input enable signal is used in the circuit to control the transfer of data between the serial data link interface and the memory bank. The flash memory device is configured to receive serial input data and control signals from an external source and to provide data and control signals to an external device. The external source and external device may be other flash memory devices in the system. In embodiments of the present invention, when devices are cascaded serially in a system, the devices may further output control ports that "pass back" (echo) the received IPE and OPE signals to external devices. This allows the system to have signal ports connected point-to-point to form a daisy chain cascading mechanism (as opposed to a broadcast/multi-drop cascading mechanism).

These systems may employ unique device identifiers and target device selection address mechanisms without using limited hardware physical device selection pins, so that the overall system is easily scalable in storage density as much as possible without sacrificing the overall performance of the system. In some embodiments of the present invention, each flash memory device may contain a unique device identifier. The device may be configured to parse a destination device information field in the serial input data to associate destination address information with a unique device identification code of the device to determine whether the device is a destination device. The device may analyze the target device information field prior to processing any other input data received. If the storage device is not the target device, the serial input data may be ignored, saving additional processing time and resources.

Drawings

The foregoing will become more apparent from the following more detailed description of exemplary embodiments of the invention, as illustrated in the accompanying drawings. In the drawings, like numerals refer to like parts throughout the different views. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating embodiments of the invention.

FIG. 1 is a block diagram of an exemplary device including a plurality of single-port devices configured in a serial daisy-chain cascade arrangement;

FIG. 2 is a block diagram of an exemplary device including a plurality of single-port devices configured in a serial daisy-chain cascaded arrangement with cascaded clocks;

FIG. 3 is a block diagram of an exemplary device including a plurality of dual port devices configured in a serial daisy chain cascading arrangement;

FIG. 4 is a block diagram of an exemplary device including a plurality of single-port devices configured in a serial daisy chain cascading arrangement providing input and output for various enable signals;

FIG. 5 is a block diagram of an exemplary device including a dual port device configured in a serial daisy chain cascading arrangement providing input and output for various enable signals;

FIG. 6 is a block diagram of an exemplary device including a plurality of devices configured in a serial daisy chain cascade arrangement, the devices having a plurality of parallel inputs and a plurality of parallel outputs;

FIG. 7 is a timing diagram depicting the relative timing in performing a read operation on a single device configured in a serial daisy chain cascade arrangement and on multiple devices configured;

FIG. 8 is a timing diagram depicting the timing associated with transferring information between devices configured in a serial daisy chain cascade arrangement;

FIG. 9 is a high level block diagram of exemplary serial output control logic for a single port device;

FIG. 10 is a high-level block diagram of exemplary serial output control logic for a dual-port device;

FIG. 11 is a detailed block diagram of exemplary serial output control logic for a device;

FIG. 12 is a block diagram of an exemplary architecture of a device configured in a serial daisy chain cascade arrangement and including exemplary serial output control logic;

FIG. 13 is a timing diagram depicting the timing associated with the inputs and outputs of a device incorporating exemplary serial output control logic.

FIG. 14 is a block diagram of exemplary serial output control logic that may be used to transfer data stored by a memory in a first device in a daisy chain cascade to a second device in the daisy chain cascade;

FIG. 15 is a timing diagram depicting the relative timing of transferring data contained in a memory of a first device in a daisy chain cascade to a second device in the daisy chain cascade using exemplary serial output control logic.

Detailed Description

The following describes preferred embodiments of the present invention:

FIG. 1 is a block diagram of an exemplary device including a plurality of single port devices 110a-e configured in a serial daisy chain cascade arrangement. Devices 110a-e are exemplary memory devices, each of which includes a memory (not shown) that may include Dynamic Random Access Memory (DRAM) cells, Static Random Access Memory (SRAM) cells, flash cells, and the like. Each device 110 includes a Serial Input (SI), a Serial Output (SO), a clock (SCLK) input, and a chip select (CS #) input.

The serial input is used to transfer information (e.g., command, address and data information) to the device 110. The serial output is used to transfer information out of the device 110. The SCLK input is used to provide an external clock signal to device 110 and the CS # input is used to provide a chip select signal to device 110. One example of a device that may be used with the techniques described herein is a Multiple Independent Serial Link (MISL) memory device as in U.S. patent application No. 11/324,023.

The SI and SO between devices 110 of the daisy chain cascade arrangement are connected to each other such that the SO in the earlier device 110 in the daisy chain cascade is coupled to the SI of the next device 110 in the daisy chain cascade. For example, the SO of device 110a connects to the SI of device 110 b. The SCLK input of each device 110 is fed with a clock signal from, for example, a memory controller (not shown in the figures). The clock signal is distributed to the various devices 110 through a common connection. SCLK is used, inter alia, to latch information input to device 110 into the various registers contained therein, as described below.

Information input to device 110 may be latched at different times of a clock signal provided to the SCLK input. For example, in a Single Data Rate (SDR) implementation, information input to device 110 through the SI may be latched on the rising or falling edge of the SCLK clock signal. Alternatively, in a Double Data Rate (DDR) implementation, information input to device 110 through SI may be latched on both the rising and falling edges of the SCLK clock signal.

The CS # input of each device for selecting the device is a conventional slice select. The input is coupled to a common link so that the chip select signal is asserted (alert) to all devices 110 in parallel, thus selecting all devices 110 simultaneously.

FIG. 2 is a block diagram of an exemplary device including a plurality of single-port devices 210a-e configured in a serial daisy-chain cascading arrangement with cascading clocks. Each device 210 includes the SI, SO, SCLK inputs and the CS # inputs as described above. In addition, each device 210 contains a clock output (SCLK). The SCLKO is an output terminal that outputs the SCLK signal input to the device 210.

Referring to fig. 2, as previously described, the SI and SO of the device 210 are coupled in a serial daisy chain cascade. Additionally, the SCLK inputs and SCLKO outputs of the devices are also coupled in a serial daisy chain cascade arrangement such that the SCLKO in the earlier device 210 in the daisy chain cascade is coupled to the SCLK input of the next device 210 in the daisy chain cascade. Thus, for example, SCLK of device 210a is coupled to SCLK input of device 210 b.

Note that the clock signal may cause delays in propagating through the daisy chain cascaded devices. Internal delay compensation circuits, such as Delay Locked Loop (DLL) circuits, may be employed to eliminate this delay.

Fig. 3 is a schematic diagram of an exemplary device configuration including a plurality of dual port devices 310a-e configured in a serial daisy chain cascade arrangement. Each device 310 includes one SI and SO each at each port, and also includes the SCLK input and CS # input as previously described. Referring to FIG. 3, the SI of the first port on the device 310 is labeled "SI 0" and the SI of the second port is labeled "SI 1". Similarly, the SO of the first port is labeled "SO 0" and the SO of the second port is labeled "SO 1". The SO and SI for each port are connected between the devices 310 as previously described. Thus, for example, the SO for port 0 on device 310a feeds the SI for port 0 on device 310b, and SO on. Similarly, the SO for port 1 on device 310a feeds the SI for port 1 on device 310b, and SO on.

FIG. 4 is a block diagram of an exemplary device including a plurality of single-port devices configured in a serial daisy chain cascade arrangement having inputs and outputs for various enable signals. Each device 410 contains the SI, SO, CS # inputs, SCLK inputs as previously described. In addition, each device 410 also includes an Input Port Enable (IPE) input, an Output Port Enable (OPE) input, an input port enable output (IPEQ), and an output port enable Output (OPEQ). The IPE input is used to input IPE signals to the device. The IPE signal is used by the device to enable the SI so that when the IPE is asserted, information may be serially input to the device 410 through the SI. Similarly, the OPE input is used to input the OPE signal to the device. The OPE signal is used by the device to enable the SO SO that when OPE is asserted, information can be serially output from the device 410 via the SO. IPEQ and OPEQ are outputs from the device that output IPE and OPE signals, respectively. The IPEQ signal may be a delayed IPE signal, or a variation of the IPE signal. Similarly, the OPEQ signal may be a delayed OPE signal, or a variation of the OPE signal. The CS # input and SCLK input are coupled to different links that distribute the CS # and SCLK signals to the devices 410a-d, respectively, as previously described.

As previously described, SI and SO are coupled from one device to the next in a daisy chain cascade arrangement. Further, the IPEQ and OPEQ of a preceding device 410 in the daisy chain cascade arrangement are coupled to the IPE input and OPE input, respectively, of a next device 410 in the daisy chain cascade. This arrangement allows the IPE and OPE signals to pass from one device 410 to the next in the daisy chain cascade.

Fig. 5 is a block diagram of an exemplary device that includes dual port devices 510a-d configured in a serial daisy chain cascade arrangement that includes inputs and outputs for various enable signals. Each device 510 includes a CS # input, an SCLK input as previously described, and SI, SO, IPE, OPE, IPEQ, and OPEQ on each port. SI, SO, IPE, OPE, IPEQ, and OPEQ in ports 1 and 2 are denoted S I1, SO1, IPE1, OPE1, IPEQ1, and OPEQ1, and SI2, SO2, IPE2, OPE2, IPEQ2, and OPEQ2, respectively.

As described above, the CS # inputs of the various devices 510 are coupled to a single link to select all of the devices 510 simultaneously. Similarly, as described above, the SCLKs of the various devices 510 are coupled to a single link to be configured to distribute the clock signal to all of the devices 510 simultaneously. Also, as described above, the SI, SO, IPE, OPE, IPEQ, and OPEQ are coupled between the devices such that the SO, IPEQ, and OPEQ of a preceding device in the daisy chain cascade are coupled to the SI, IPE, and OPE of a succeeding device in the daisy chain cascade. For example, SO1, SO2, IPEQ1, IPEQ2, OPEQ1, and OPEQ2 of device 510a are coupled to SI1, SI2, IPE1, IPE2, OPE1, and OPE2, respectively, in device 510 b.

The SI, IPE, and OPE signals input to the SI, IPE, and OPE inputs, respectively, of device 510a are provided to device 510a under control of, for example, a memory controller (not shown). The device 510d returns data and control signals to the memory controller through the SO, IPEQ, and OPEQ outputs in the device 510 d.

FIG. 6 is a block diagram of an exemplary device comprising a plurality of devices 610a-d configured in a serial daisy chain cascade arrangement having a plurality of serial inputs (SI0 through SIn) and a plurality of serial outputs (SO0 through SOn). In addition, each device 610 has an SCLK input and a CS # input as described above.

The serial inputs (SI0 to SIn) and serial outputs (SO0 to SOn) used by the various devices 610 enable information to be input and output, respectively, to the devices 610 in a serial manner. Each input is assigned a specific role to input certain types of data (e.g., address, command, data) and/or signals (e.g., enable signals) to the device 610. Similarly, each output is assigned a specific role to output certain types of data and signals from the device 610. For example, one or more inputs may be assigned a role that can input address information to the device 610. Similarly, for example, one or more outputs may be assigned a role of outputting address information from the device 610.

The number of serial inputs and serial outputs on each device 610 typically depends on certain factors, such as the number of address lines, command size, and data width size. These factors can be influenced by how the device is used in a particular system application. For example, system applications requiring data storage of small amounts of information may employ devices having fewer address and data lines, and thus fewer input/output terminals, than system applications requiring data storage of large amounts of information.

FIG. 7 is a timing diagram depicting the timing associated when performing read operations on individual devices configured in a serial daisy chain cascade arrangement and on multiple devices configured. Referring to fig. 7, CS # is asserted to select all devices. The read operation is initiated by establishing an IPE and clocking information associated with the read operation into the device in a clock tick via the SI. Illustratively, such information includes a Command (CMD) indicating that a read operation is performed, and a column address (Col ADD) and a Row address (Row ADD) indicating a memory start address of where to read data.

At time "tR", the requested data is read from memory and stored in a specific internal data buffer contained in the device. the length of tR is generally determined by the characteristics of the cell containing the memory. After time tR, OPE is asserted to enable serial transfer of data from the internal data buffer over the SO to the next device in the daisy chain cascade. Illustratively, on the rising edge of SLCK, data is serially output from an internal buffer at the SO output. Data output from devices in the daisy chain cascade is delayed as long as one clock cycle to control, for example, the delay time (latency) associated with propagating control signals such as IPE and OPE. As will be described, the delay time control is performed using clock synchronized latches.

Some examples of the operation of cascaded memory devices in a flash core architecture implementation are shown in table 1 below. Table 1 lists the Target Device Address (TDA), possible Operation (OP) codes and corresponding states of column addresses, row/bank addresses, and input data.

TABLE 3 Command set

In some embodiments of the present invention, each device of the system shown in FIGS. 1-6 may possess a unique device identifier to use as the target device address (tda) in the serial input data. Upon receiving the serial input data, the flash memory device analyzes a target device address in the serial input data and determines whether the device is the target device by associating the target device address with a device identification number unique to the device.

Table 2 shows a preferred input order for an input data stream according to an embodiment of the invention, including the systems described in connection with fig. 1-6. Commands, addresses, and data are serially shifted into and out of each memory device, starting with the most significant bit.

Referring to fig. 4, the devices 410a-d may operate with a serial input Signal (SIP) sampled on a rising edge of a Serial Clock (SCLK) when Input Port Enable (IPE) is high. The command sequence begins with a single byte of the target device address ("tda") and a single byte of the operation code, also referred to interchangeably as the command code ("cmd" in table 1). By starting with a single-byte target device address in the most significant bits of the serial input signal, the device may analyze the target address field before processing any additional input data received. If the storage device is not the target device, the serial input data may be transferred to another device prior to processing, thereby saving additional processing time and resources.

Table 2 input sequence in byte mode

After a single byte of cmd code, the single byte TDA is shifted into the device. The Most Significant Bit (MSB) starts from SIP and latches each bit on the rising edge of the Serial Clock (SCLK). Depending on the command, a single-byte command code may be followed by a column address byte, a row address byte, a bank address byte, a data byte, and/or a combination or blank.

FIG. 8 is a timing diagram depicting the timing associated with transferring data between devices configured in a serial daisy chain cascade arrangement. As described above, CS # is established to select a device. Information is input to the first device in the serial daisy chain cascade arrangement by asserting IPE and clocking clock data into the devices on the rising edge of successive SCLKs. The IPE propagates through the first device to the second device in less than one cycle. This clocks information from the SO of the first device into the SI of the second device within one cycle after clocking into the first device. This process is repeated in successive devices in a serial daisy chain cascade. Thus, for example, information is input to a third device in the serial daisy chain cascade at the third rising edge of SCLK from the latch point of the data at the first device.

Fig. 9 is a block diagram of exemplary serial output control logic 900 in a single port device. Logic 900 includes an input buffer 902 for IPE, an input buffer 904 for SI (SIP), an input buffer 906 for OPE, an input latch controller 908, a serial-to-parallel register 910, an output latch controller 912, a data register 914, an address register 916, a command interpreter 918, a selector 920, a page buffer 924, a logical OR gate 926, an output buffer 928, a selector 930, and a memory 950.

The input buffer 902 is a conventional low voltage transistor-to-transistor logic (LVTTL) buffer configured to buffer the state of an IPE signal fed to the device at the input of the buffer 902. The output of buffer 902 is provided to input latch control 908, which latches the state of the IPE signal and provides the latched state of the IPE signal to input buffer 904 and selector 920. The input buffer 904 is a LVTTL buffer configured to buffer information provided to the device through the SI input. Input buffer 904 is enabled by input latch controller 908. When enabled, information provided to the SI input is transferred by buffer 908 to serial-to-parallel register 910 and to one input of selector 930. Input buffer 904 is enabled when the latched state of the IPE signal provided by input latch controller 908 indicates that the IPE signal is asserted. Information provided to the serial-to-parallel register 910 is converted from a serial form to a parallel form by the register 910. The output of the serial-to-parallel register 910 is provided to a data register 914, an address register 916, and a command interpreter 918.

The data register 914 and the address register 916 hold data and address information, respectively, provided to the device through the SI. The command interpreter 918 is configured to interpret commands input to the device through the SI. These commands are used to further control the operation of the device. For example, a "write memory" command may be used to cause the device to write data contained in the data register 914 to the memory 950 located at an address specified in the device via the address register 916.

The input buffer 906 is a LVTTL buffer configured to buffer an OPE signal provided to the OPE input of the device. The output of the buffer 906 is passed to an output latch controller 912 which latches the state of the OPE signal. The output latch controller outputs the latched OPE signal state to or gate 926. Or gate 926 is a conventional logical or gate whose output is used to enable/disable the output of output buffer 928.

Selector 920 is a conventional 1-out-of-2 multiplexer that selects one of two inputs as an output via signal DAISY _ CHAIN. As previously described, one of these inputs is the latched state of the IPE signal obtained from input latch controller 908. The other input is set to a logic low state. The signal DAISY _ CHAIN indicates whether the device is connected to one or more other devices in a serial DAISY CHAIN cascade arrangement. Illustratively, the signal is asserted if the device is connected to one or more other devices in a serial daisy chain cascade arrangement. Asserting the DAISY _ CHAIN signal causes the latched state of the IPE signal provided to selector 920 to be output from selector 920. When the DAISY _ CHAIN signal is not asserted, a logic low state input to the selector 920 is output from the selector 920.

The page buffer 924 is a conventional data buffer configured to hold information read from the memory 950. Selector 930 is a conventional 1-out-of-2 multiplexer that selects one of two inputs as an output via signal ID _ MATCH. One input of selector 930 is provided by the output of page buffer 924, and the other input is provided by the output of SI input buffer 904. The output of selector 930 is provided to output buffer 928. The signal ID MATCH indicates whether a particular command transmitted to the device via the SI is addressed to the device. If the command is addressed to a device, ID _ MATCH is asserted so that the output of page buffer 924 is output from selector 930. If ID _ MATCH is not asserted, the output from the SI buffer 904 (i.e., the state of the SI signal input to the device) is output from the selector 930.

The memory 950 is a conventional register configured to hold data. The memory 950 may be a Random Access Memory (RAM) comprising a plurality of cells, such as static RAM (sram), dynamic RAM (dram), or flash memory cells, which may be addressed using addresses input to the device via SI.

In operation, an asserted IPE signal is buffered by input buffer 902 and passed to input latch controller 908, which latches the state of the asserted IPE. This latched state is provided to selector 920 and input buffer 904 to enable the buffer 904. The command, address and data information input to the input buffer 904 is then transferred to the serial-to-parallel register 910, which converts the information from serial to parallel form, and provides the command, address and data information to the command interpreter 918, address register 916 and data register 914, respectively. The output of buffer 904 is also provided to selector 930. If ID _ MATCH is not asserted, the output of register 904 will appear at the output of selector 930, which is provided to the input of output register 928. If DAISY _ CHAIN is asserted, the latched state of IPE will appear at the output of selector 920 and is provided to a first input of OR gate 926. Or gate 926 passes the state of the IPE to output buffer 928 to enable output buffer 928. This in turn will allow information input to the SI input to be output from the SO of the device.

Data from the page register 924 is output from the device by asserting OPE and ID _ MATCH. In detail, the asserted state of the OPE is provided to the input buffer 906, which in turn provides the state to the output latch controller 912, which latches the state. The latched asserted state is provided to a second input of OR gate 926, OR gate 926 outputting a signal to enable output buffer 928. Asserting the output of the ID _ MATCH enable page register 924 appears at the output of the selector 930. The output of selector 930 is provided to an enabled output buffer 928, which outputs data from the SO output of the device.

Note that output buffer 928 is only OPE enabled if DAISY _ CHAIN is not asserted. This would allow the device to be used in a non-daisy chain serial cascade configuration.

Fig. 10 is a block diagram of exemplary serial output control logic 1000 in a dual port device. For each port, the input and control path logic 1000 includes an IPE input buffer 1002, a SI input buffer 1004, an OPE input buffer 1006, an input latch controller 1008, a serial-to-parallel register 1010, an output latch controller 1012, a data register 1014, an address register 1016, a command interpreter 1018, a selector 1020, a page buffer 1024, a logical OR gate 1026, an output buffer 1028, and a selector 1030, which are identical to the IPE input buffer 902, the SIP input buffer 904, the OPE input buffer 906, the input latch controller 908, the serial-to-parallel register 910, the output latch controller 912, the data register 914, the address register 916, the command interpreter 918, the selector 920, the page buffer 924, the logical OR gate 926, the output buffer 928, and the selector 930, respectively, described above.

FIG. 11 is a detailed block diagram of another embodiment of serial output control logic 1100 for use with the techniques described herein. Logic 1100 includes an SI input buffer 1104, an IPE input buffer 1106, an OPE input buffer 1108, an SCLK input buffer 1110, logical AND (AND) gates 1112 AND 1114, latches 1116, 1118, 1120, AND 1122, selectors 1124 AND 1130, a logical OR gate 1126, AND an SO output buffer 1128. Buffers 1104, 1106, 1108 and 1110 are conventional LVTTL buffers configured to buffer SI, IPE, OPE and SCLK signals, respectively, that are input into the device.

And gate 1112 is configured to output information input to SI to latch 1116 when IPE is asserted. The latch 1116 is configured to latch this information when the buffer 1110 provides a clock Signal (SCLK). DATA _ OUT represents the state of DATA read from a memory (not shown) contained in the device. And gate 1114 is configured to output the state of DATA _ OUT when OPE is asserted. The output of AND gate 1114 is provided to a latch 1118, which latch 1118 is configured to latch the state of DATA _ OUT when buffer 1110 provides a clock signal. The buffer 1106 is configured to buffer IPE signals provided to the device. The output of the buffer 1106 is latched by a latch 1120. Similarly, buffer 1108 is configured to buffer OPE signals provided to the device. Latch 1122 is configured to latch the state of OPE output by buffer 1108. Selectors 1124 and 1130 are conventional 1-out-of-2 multiplexers each having two inputs. The input of the selector 1124 is selected as output from the selector 1124 via the ID _ MATCH signal described above. One input is provided the latched state of DATA _ OUT maintained by latch 1118. This input is selected to be output from the selector 1124 when ID _ MATCH is asserted. The other input is provided with the latching state of the SI maintained by latch 1116. When ID _ MATCH is not asserted, this input is selected to be output from the selector 1124.

The input of the selector 1130 is selected by the above-mentioned DAISY _ CHAIN signal to be output from the selector 1130. One input of selector 1130 is provided with the latched state of the IPE maintained by latch 1120, while the other input is connected to a logic 0. When DAISY _ CHAIN is asserted, the latched state of IPE is selected as the output of selector 1130. Similarly, when DAISY _ CHAIN is not asserted, a logic 0 is selected from the output of selector 1130.

Or gate 1126 is a conventional logical or gate configured to provide an enable/disable signal to output buffer 1128. Or gate 1126 is provided the output of selector 1130, as well as the latched state of OPE maintained by latch 1122. Either of these two outputs may be used to provide a time enable signal to the buffer 1128 to enable the output of the buffer. The buffer 1128 is a conventional buffer for buffering the output signal SO. As described above, the output of the buffer 1128 through the or gate 1126 is enabled/disabled.

In operation, when IPE is asserted, information input to the device through SI is provided to latch 1116. Illustratively, latch 1116 latches this information at the first upward transition of SCLK after IPE is asserted. Similarly, latch 1120 latches the state of IPE at this SCLK transition. Assuming that ID _ MATCH is not asserted, the output of latch 1116 is provided to register 1128 via selector 1124. Similarly, an asserted IPE is transferred from buffer 1106 to latch 1120, also illustratively latching in latch 1120 at the first upward transition of SCLK. Assuming that DAISY _ CHAIN is asserted, the latched state of IPE is provided to the output of selector 1130 and passed to OR gate 1126 to provide an enable signal to register 1128. The latched state of the SI is then passed out of the device as output SO via buffer 1128.

When the data _ CHAIN is not asserted, a logic 0 input to the selector 1130 is selected, and the selector 1130 outputs a logic 0. This effectively disables the IPE enable buffer 1128.

Illustratively, on the next upward transition of SCLK after OPE is asserted, the asserted state of OPE is latched 1122 and the state of DATA _ OUT is latched 1118. Assuming that ID _ MATCH is asserted, the latched state of DATA _ OUT is selected by the selector 1124 and applied to the input of the register 1128. At the same time, the latched asserted state of OPE resulting from latch 1122 is transferred through OR gate 1126 to enable buffer 1128, which causes the latched state of DATA _ OUT to be output from the device as output SO.

FIG. 12 is a block diagram of an exemplary architecture of a device configured in a serial daisy chain cascade arrangement and including exemplary serial output control logic. The arrangement includes three devices 1210 configured as previously described with the output of a previous device in the daisy chain cascade coupled to the input of the next device in the daisy chain cascade. The transfer of information and data from one device to the next is described with reference to fig. 13 below.

Fig. 13 is an exemplary timing diagram for illustrating input and output related timing for the device depicted in fig. 12. Specifically, the figure describes the operation of serial output control logic 1100 in each device with respect to transferring information input at the SI input of each device 1210 to the SO output of the device 1210.

Referring to fig. 11, 12 and 13, assume that DAISY _ CHAIN is asserted. When an IPE is established at device 1210a, data at the device SI input is transferred to the SO output of device 1210a through the serial output control logic 1100 of the device as previously described. In detail, at each rising edge of SCLK after IPE is established, data is illustratively clocked into device 1210 a. The information and status of the IPE propagates through logic 1100 as previously described and exits device 1210a at the device's SO and IPEQ outputs, respectively. These outputs are represented in the figure by S1 and P1, respectively. As previously described, these outputs are provided to the SI and IPE inputs of device 1210b, through the serial output control logic 1100 of device 1210b, and output from the SO and IPEQ outputs of device 1210b one clock cycle later. These outputs are represented in the figure by S2 and P2, respectively. Similarly, the SO and IPEQ outputs of device 1210b are provided to the SI and IPE inputs, respectively, of device 1210c, through serial output control logic 1100 of device 1210c, and output from device 1210c after one clock cycle from the SO and IPEQ outputs of the device, respectively. These outputs are represented in the figure by S3 and P3, respectively.

In the daisy chain cascade arrangement as described above, the signal output delay time (latency) in the daisy chain cascade for SDR operation can be determined using the following equation:

output_latency＝N*clock_cycle_time

wherein:

"output _ latency" is an output delay time of data,

"N" is the number of devices in the daisy chain cascade arrangement, and

"clock _ cycle _ time" is the clock cycle time of the clock operation.

For example, assume that the clock _ cycle _ time of the daisy chain cascade depicted in fig. 12 is 10 nanoseconds. For SO data in device 1210c, the total output delay time is 3 x 10 nanoseconds or 30 nanoseconds.

In the example of DDR operation, the output delay time can be determined as follows:

output_latency＝N*(clock_cycle_time/2)

in DDR operation, both edges of the clock can serve as a latch point for input data and a change point for output data. Thus, the total delay time is half of the delay time in SDR operation.

Note that in the above description, information input into the device 1210 is output after one clock cycle for the SDR operation and after half a cycle for the DDR operation. Such delays are introduced to provide the time required to activate the output buffer 1128.

Fig. 14 is a block diagram of logic 1400 for transferring data stored by a memory of a first device 1450a in a daisy chain cascade to a second device 1450b in the daisy chain cascade. Logic 1400 includes data output register 1402, OPE input buffer 1404, SCLK input buffer 1406, and gate 1408, data output latch 1410, OPE state latch 1412, selector 1414, SO output buffer 1416, and OPEQ output buffer 1418.

Data output register 1402 is a conventional register configured to store data read from memory contained in device 1450. Register 1402 is illustratively a parallel-to-serial data register that loads data from memory in a parallel fashion and transfers the data serially to the input of gate 1408. SCLK provides the clock signal used by register 1402 to transfer data to gate 1408. As shown, the data register 1402 is configured to hold byte data including bits D0 through D7, where D0 is the Least Significant Bit (LSB) of the byte and bit D7 is the Most Significant Bit (MSB) of the byte. Register 1402 loads one byte wide of data from memory in parallel. The data is shifted out of the register starting with the most significant bit and provided to the input of gate 1408 bit by bit in a serial fashion.

Buffers 1404 and 1406 are conventional LVTTL buffers for buffering the input signals OPE and SCLK, respectively. The OPE signal is passed from the Output (OPEI) of buffer 1404 to gate 1408. The SCLK signal is transferred from the output of buffer 1406 to data output register 1402, and latches 1410 and 1412 to clock these components.

Gate 1408 is a conventional logical and gate configured to transfer the output of DATA output register 1402 (DATA _ OUT) to latch 1410 when OPE is asserted. The output of gate 1408 is denoted "DBIT". Latches 1410 and 1412 are conventional latches configured to latch the state of the DBIT and OPE signals, respectively. Selector 1414 is a conventional 1-out-of-2 multiplexer controlled by signal ID _ MATCH. One of the data inputs is the latched state of DBIT. When ID _ MATCH is asserted, this status is output from selector 1414. The other input is serial data (SI0) transmitted to the device through the SI of the device 1450 a. When ID _ MATCH is not asserted, this information is output from selector 1414.

Buffers 1416 and 1418 are conventional buffers configured to buffer the outputs of selector 1414 and latch 1406, respectively. The output of buffer 1416 exits device 1450a as SO (SO0) and the output of buffer 1418 exits device 1450a as OPEQ (OPEQ 0).

FIG. 15 is a timing diagram associated with an exemplary timing for transferring a one byte wide data from memory contained in device 1450a to device 1450b using logic 1400. Referring to fig. 14 and 15, the OPEI is asserted shortly after the OPE is provided to device 1450a in input buffer 1404. The OPEI is provided to gate 1408 to enable the data currently at D7 of data output register 1402 to be latched in latch 1410 at the next rising edge of SCLK. In addition, the next rising edge of SCLK causes data to shift right into the data output register, so that data of D6 is shifted to D7, data of D5 is shifted to D6, and so on. The output of the latch 1410 appears at the selector 1414, and assuming that ID _ MATCH is asserted, the selector 1414 outputs the latched state of the data to the register 1416. The buffer 1416 outputs this latched state as SO0 from device 1450a, SO0 being provided to the SI input of the next device in the daisy chain cascade (SI 1). At the same time, the state of OPE is latched in latch 1412 also on the rising edge of the first clock after OPE is asserted. The output of the latch 1412 is transferred to a buffer 1418, which outputs the latched state of the OPE from device 1450a as the OPEQ (OPEQ0) which is provided to the OPE input (OPE1) of the next device 1450b in the daisy chain cascade. The above process is repeated for bits D6 through D0.

While the present invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims.

Claims (56)

1. A semiconductor device, comprising:

a memory;

a first circuit for receiving input data at a data input port and transmitting output data to an output port;

a second circuit for receiving an input clock signal, the first circuit receiving input data in synchronization with the input clock signal;

a third circuit for receiving the first enable signal and outputting the second enable signal.

2. The semiconductor device of claim 1, wherein the first circuit is configured to receive:

a first enable signal for indicating the presence of input data; or

A first enable signal having first and second logic levels, the first logic level indicating the presence of valid input data at the data input port, the second logic level indicating the absence of valid input data at the data input port.

3. The semiconductor device of claim 1 or 2, wherein the third circuit is configured to receive a first enable signal for data transfer between the data input port and the memory.

4. The semiconductor device of claim 1, wherein the second enable signal is derived from the first enable signal.

5. The semiconductor device of claim 1, wherein the input data comprises serial data, the first circuitry configured to:

converting the serial data into parallel data and transmitting the converted data to a memory; or

The parallel data obtained from the memory is converted into serial data.

6. The semiconductor device of claim 1, wherein the third circuit is configured to receive executable instructions at an input port to control transfer of input data and output data to and from a memory.

7. The semiconductor device of claim 6, further comprising a device identification number.

8. The semiconductor device of claim 7, wherein the third circuit is further configured to control:

accessing the memory in response to a target device address corresponding to a device identification number associated with the device, the target device address contained in a target device address field of the input data; or

Data is transferred to a location in the memory identified by the address field of the input data.

9. The semiconductor device of claim 1, wherein the memory, the first circuit, and the third circuit are located within a single package having a single-sided pad architecture.

10. The semiconductor device of claim 1, wherein the memory comprises a non-volatile memory bank.

11. The semiconductor device of claim 10, wherein the non-volatile memory bank comprises a flash memory bank.

12. The semiconductor device of claim 1, further comprising:

an output port enable input for receiving an output port enable input signal, the output port enable input signal being used to enable the memory device to send serial output data to an external device; and

an output port enable output for outputting the output port enable output signal.

13. A method of controlling data transfer between a link interface and a memory having a bank in a semiconductor device, the method comprising:

receiving an input data stream;

receiving a first enable input signal;

receiving a clock input signal;

enabling processing of the received input data in response to a first enable signal to store data in or access data from a memory;

transmitting a second enable signal derived from the first input enable signal; and

the output data stream is transmitted.

14. The method of claim 13, further comprising:

the input data stream is parsed to extract the device address, the command, and the bank address of the bank.

15. The method of claim 13, wherein the command comprises a memory access command, and the processing further comprises:

converting serial input data into parallel data; and

parallel data is transferred to the memory banks.

16. A semiconductor device, comprising:

a memory;

a first input circuit for receiving input data at a data input port;

control circuitry responsive to a target device address contained in the input data and associated with a device identification number to control access to the memory, the device identification number associated with the device.

17. The semiconductor device of claim 16, further comprising:

a second input circuit for receiving a first control signal indicating the presence of input data at a data input port; or

A third input circuit for receiving a second control signal indicating the presence of output data at the data output port.

18. The semiconductor device of claim 17, wherein:

each time interval of input and output data is based on a clock; and

each of the first and second control signals has a first logic level and a second logic level, the first logic level and the second logic store indicating the presence and absence of data, respectively.

19. The semiconductor device of claim 17, wherein:

the first input circuit is configured to transmit output data to a data output port, the input data and the output data containing target device address information; and

the control circuit is configured to control transfer of data between the first input circuit and the memory and between the first input circuit and the data output port.

20. The semiconductor device of claim 19, wherein the control circuit is configured to control:

transmission of data from the first input circuit to a data output port; or

Transfer of data accessed from the memory to the data output port in response to the destination device address information.

21. The semiconductor device of claim 20, wherein:

the data transmission occurs at any one of a single and double data rate based on rising and falling edges of a clock signal;

each of the input data and the output data is serial data; and

the first input circuit is further configured to convert serial input data into parallel data and to transmit the converted data to a memory.

22. The semiconductor device defined in claim 21, further comprising:

a second input circuit for converting the parallel data from the memory into serial output data.

23. The semiconductor device of claim 16, wherein:

the control circuitry is configured to receive executable instructions to control the transfer of input data and output data to and from the memory; and

the control circuitry is programmed with executable instructions to parse a target device address field in the input data and control transfer of the data to the memory.

24. The semiconductor device of claim 16, wherein:

the memory, the first input circuit, and the control circuit are located within a single package having a single-sided pad architecture; or

The memory includes a plurality of memory banks.

25. The semiconductor device of claim 16, wherein the memory comprises a non-volatile memory.

26. The semiconductor device according to claim 25, wherein the nonvolatile memory is a flash memory.

27. A method of controlling transfer of data between a link interface and a memory bank in a semiconductor device, the method comprising:

receiving an input data stream at a link interface, the input data stream including a target device address, a command, and bank address information;

receiving a first enable signal indicating the presence of input data at the link interface;

parsing the received input data to extract a target device address, a command, and a bank address of a bank; and

the received input data is processed when the target device address is associated with the device identifier.

28. The method of claim 27, further comprising: an output data stream from the link interface is transmitted.

29. The method of claim 28, wherein the input and output data streams comprise serial data, the method further comprising:

converting serial input data into parallel data to transmit the converted parallel data to a memory; and

parallel data is transferred between the memory and the link interface to convert the parallel data into serial output data.

30. The method of claim 27, further comprising:

the presence and absence of input data and output data is indicated by two logic level signals.

31. A system comprising at least one semiconductor device, the device being as defined in any one of claims 16-30.

32. The system of claim 31, comprising a plurality of semiconductor devices, each of the plurality of semiconductor devices being defined by any one of claims 16-30, and a controller comprising:

an output for transmitting data to a first one of the plurality of semiconductor devices; and

an input for receiving data from a last device of the plurality of semiconductor devices.

33. A semiconductor device, comprising:

a memory;

a clock input circuit for receiving a clock signal;

a data circuit for receiving input data in synchronization with a clock signal and transmitting output data in synchronization with the clock signal.

34. The semiconductor device of claim 33, wherein the data circuit comprises:

a data input circuit for receiving input data; and

and the data output circuit is used for transmitting output data.

35. The semiconductor device defined in claim 34 wherein:

the data input circuit includes a data capture circuit for capturing input data in synchronization with a clock signal; and

the data output circuit includes a data transmission circuit for transmitting output data in synchronization with a clock signal.

36. The semiconductor device defined in claim 35 wherein:

the data capture circuitry is configured to store the captured data in a memory; and

the synchronization of the data is achieved with a clock signal.

37. The semiconductor device defined in claim 34 wherein:

the data input circuit is configured to receive input data having input bits and the data output circuit is configured to transmit output data having output bits; or

The data input circuit is configured to receive input data having one bit, and the data output circuit is configured to transmit output data having one bit.

38. The semiconductor device defined in claim 37 wherein:

each of the input and output data contains a single bit at a time.

39. The semiconductor device of claim 35 or 36, wherein:

the data capture circuit is configured to capture input data once during each cycle of a clock signal; and

the data transmission circuit is configured to transmit the output data once during each period of the clock signal.

40. The semiconductor device defined in claim 35 wherein:

the data capture circuit is configured to capture input data twice during each cycle of a clock signal; and

the data transfer circuit is configured to transfer the output data twice during each cycle of the clock signal.

41. The semiconductor device defined in claim 34, further comprising:

and a clock output circuit for outputting an output clock signal responsive to the input clock signal, the output data being transmitted in synchronization with the output clock signal.

42. The semiconductor device defined in claim 41, further comprising a delay adjustment circuit to adjust a delay of the input clock.

43. The semiconductor device of claim 42, wherein the delay adjustment circuit comprises a delay locked loop.

44. The semiconductor device of claim 33, wherein the memory comprises a non-volatile memory.

45. The semiconductor device according to claim 44, wherein the nonvolatile memory comprises a flash memory.

46. A system, comprising:

a controller for transmitting data and a clock; and

an apparatus comprising a plurality of semiconductor devices, each semiconductor device being as defined in one of claims 33 to 39,

the output data and the output clock of one semiconductor device are transmitted to the next semiconductor device as its input data and input clock.

47. The system of claim 46, wherein each of the plurality of semiconductor devices is further defined by one of claims 41-45.

48. The system of claim 46, wherein each of a plurality of semiconductor devices in the apparatus receives a clock signal from a controller.

49. The system of any one of claims 46 to 48, wherein:

the plurality of semiconductor devices includes at least a first semiconductor device and a second semiconductor device; and

the data circuit of the first semiconductor device is configured to receive input data and an input clock from a controller.

50. The system of claim 49, wherein

The data circuit of the second semiconductor device is configured to receive, directly or indirectly, the output data and the output clock as the input data and the input clock from the first semiconductor device.

51. The system of any of claims 46-50, wherein the data circuit of the second semiconductor device is configured to transmit the output data to the controller.

52. The system of claim 51, wherein the data circuit of the second semiconductor device is further configured to transmit the output clock to the controller.

53. A method for accessing memory, comprising:

receiving a clock signal;

receiving input data in synchronization with a clock signal; and

the output data is transmitted in synchronization with the clock signal.

54. The method of claim 53, wherein:

the step of receiving input includes capturing input data; and

the step of transmitting comprises transmitting the output data,

each of the data reception and the data transmission is performed once or twice during each cycle of the clock signal.

55. The method of claim 53 or 54, further comprising:

an output clock signal responsive to the received clock signal is output, and output data is transmitted in synchronization with the output clock signal.

56. The method of claim 55, wherein the outputting step comprises:

the delay of the received clock signal is adjusted to output an output clock signal.