CN1328790C - A dummy solder bump structure and manufacturing method for avoiding generation of parasitic capacitance - Google Patents

Abstract

A parasitic capacitance-preventing dummy solder bump structure includes at least one conductive layer formed on a substrate surface, a dielectric layer covering the conductive layer, an under bump metallurgy layer (UBM layer) formed on the surface of the dielectric layer, and a solder bump formed on the under bump metallurgy layer.

Description

A dummy solder bump structure and manufacturing method for avoiding generation of parasitic capacitance

technical field

The invention relates to a solder bump and a manufacturing method thereof, in particular to a parasitic capacitance-preventing dummy solder bump structure and a manufacturing method thereof.

Background technique

In today's packaging technology, high-efficiency electronic components usually use solder balls or solder bumps to achieve the purpose of electrical and mechanical connection with each other. For example, very large scale integration (VLSI) uses solder balls or solder bumps to electrically connect to a circuit board or other secondary packaging substrate. This connection technology is called flip-chip bonding (Flip-chip, FC), also known as C4 bonding (Controlled Collapse Chip Connection). Flip-chip bonding is a planar array (Area Array) type of bonding, so it can be applied to extremely high-density electronic assembly. To put it simply, the concept of flip chip bonding is to grow solder bumps on the pads of the IC chip first, then place the IC chip on the assembly substrate and complete the alignment of the pads, and reflow soldering (Reflow) ) Cooperate with the surface tension effect when the solder melts to make the solder into a ball, and then complete the bonding of the IC chip and the assembly substrate.

Please refer to FIG. 1 to FIG. 4 , which are schematic diagrams of a manufacturing method of a conventional solder bump structure. As shown in FIG. 1 , the surface of the substrate 10 includes a first region 12 , a second region 14 and at least one conductive layer 16 . The base 10 is a semiconductor chip, and an integrated circuit is formed in the semiconductor chip; the first area 12 is the central area of the surface of the base 10 , and the second area 14 is the peripheral area of the surface of the base 10 .

As shown in FIG. 2 , a chemical vapor deposition (chemical vapor deposition, CVD) process is first performed to form a dielectric layer 18 covering the conductive layer 16 on the surface of the substrate 10 . Then an etching process is performed to form at least one via hole (via hole) 20 penetrating through the dielectric layer 18 in the first region 12 until reaching the surface of the conductive layer 16 . A deposition (deposition) process is then carried out to form an electrically connected conductive layer 16 in each via hole 20, and a via plug (viaplug) 22 made of tungsten (tungsten), and then a chemical mechanical polishing ( chemical mechanical polishing (CMP) process, so that the surface of the via plug 22 is approximately tangent to the surface of the dielectric layer 18 .

As shown in FIG. 3 , a metal pad 24 made of copper or aluminum is then formed in a plurality of predetermined regions of the first region 12 and the second region 14, and then a chemical vapor deposition process and an etching process are performed to A protection layer 26 is formed on the surface of the dielectric layer 18 not covered by the metal pad 24 . As shown in FIG. 4 , a sputtering process and an etching process are then performed to form an under bump metallurgy layer (UBM layer) 28 on the surface of each metal pad 24 . Finally, a solder bump 30 is formed on each flip-chip UBM layer 28 to complete the manufacturing method of the conventional solder bump structure. Wherein, the solder bump 30 formed in the second region 14 is used as a dummy solder bump, so that the solder bump layout of the substrate 10 presents a symmetrical shape for subsequent packaging (packaging) process In this process, the flow stability of the under fill liquid compound of the substrate 10 is improved.

However, as products become more sophisticated and complex, the process line width is also gradually reduced. Therefore, when the thickness of the dielectric layer 18 is reduced due to product specifications, the metal pad 24 made of copper or aluminum in the conventional solder bump structure is often too close to the conductive layer 16, resulting in the metal pad 24 A parasitic capacitance is generated between the conductive layer 16 and the conductive layer 16, thereby affecting product performance and even causing circuit failure.

Contents of the invention

Therefore, the main purpose of the present invention is to provide a method for manufacturing a parasitic capacitance-preventing dummy solder bump structure, so as to solve the above-mentioned problems of the conventional manufacturing method.

The above object of the present invention is achieved by the following technical solutions.

A dummy solder bump structure avoiding generation of parasitic capacitance, the dummy solder bump structure is formed on a substrate, the dummy solder bump structure includes:

at least one conductive layer formed on the surface of the substrate;

a dielectric layer formed on the surface of the substrate and covering the conductive layer;

a flip chip under ball metallization layer formed on the surface of the dielectric layer; and

A solder bump is formed on the flip-chip UBM layer.

The dummy solder bump structure for avoiding parasitic capacitance is characterized in that: the substrate is a semiconductor chip, and an integrated circuit is formed in the semiconductor chip, and the dielectric layer includes at least one chemical vapor deposition process. The deposited layer formed is used as a protective layer.

The feature of the dummy solder bump structure avoiding generation of parasitic capacitance is that the deposition layer contains silicon nitride or silicon oxide.

The feature of the dummy solder bump structure for avoiding generation of parasitic capacitance is that the metal layer under the flip chip ball is formed by a metal layer formed by a sputtering process.

The feature of the dummy solder bump structure for avoiding generation of parasitic capacitance is that a plurality of solder bump structures are additionally formed on the surface of the dielectric layer.

The described virtual solder bump structure for avoiding generation of parasitic capacitance is characterized in that: each of the solder bump structures includes:

a metal pad formed on the surface of the dielectric layer;

a flip-chip under-ball metal layer formed on the surface of the metal pad; and

A solder bump is formed on the flip-chip UBM layer.

The dummy solder bump structure for avoiding parasitic capacitance is characterized in that: each solder bump structure additionally includes at least one interlayer plug for electrically connecting each solder bump structure with the corresponding conductive layer below it. layer.

The feature of the dummy solder bump structure for avoiding generation of parasitic capacitance is that: the solder bump structure is arranged in the central region of the substrate surface, and the dummy solder bump structure is arranged in the peripheral region of the substrate surface And surrounded by at least one of the aforementioned solder bump structures.

The feature of the dummy solder bump structure for avoiding generation of parasitic capacitance is that the dummy solder bump structure is used to improve the stability of fluidity of the liquid bottom sealant in the subsequent packaging process of the substrate.

The present invention also provides a method for forming solder bumps on a substrate surface, the substrate surface includes at least one conductive layer, and the substrate surface is divided into a first region and a second region, the method includes the following step:

forming a dielectric layer on the surface of the base and covering the conductive layer;

forming at least one via plug penetrating through the dielectric layer in the first region and electrically connecting the conductive layer;

forming at least one metal pad electrically connected to the via plug;

performing a flip-chip UBM process to form at least one flip-chip UBM layer on the surface of the metal pad in the first region and the surface of the dielectric layer in the second region; and

A solder bump is formed on each of the flip-chip UBM layers.

The method for forming solder bumps on a substrate surface is characterized in that: after the step of forming a dielectric layer on the substrate surface and covering the conductive layer, at least one dielectric layer penetrating through the first region is formed. Before the step of electrically connecting the electrical layer and the via layer plug electrically connected to the conductive layer, further including a protection layer on the dielectric layer.

The method for forming solder bumps on a substrate surface is characterized in that: the dielectric layer and the protective layer are made of materials including silicon nitride or silicon oxide.

The method for forming solder bumps on the surface of a substrate is characterized in that: the material forming the via plug includes titanium, titanium nitride, tungsten, aluminum, copper or copper-aluminum alloy.

The method for forming solder bumps on a substrate surface is characterized in that: the flip-chip underball metal layer is formed by a sputtering process.

The method for forming solder bumps on the surface of a substrate is characterized in that: the solder bumps formed in the second region are used as a dummy solder bump to improve the subsequent packaging process of the substrate. The fluidity of the liquid bottom seal is stable.

The method for forming solder bumps on the surface of a substrate is characterized in that: the substrate is a semiconductor chip, and an integrated circuit is additionally formed in the semiconductor chip.

The method for forming solder bumps on a substrate surface is characterized in that: the first region is a central region of the substrate surface, and the second region is a peripheral region of the substrate surface. In a preferred embodiment of the present invention, a substrate surface includes a first region, a second region and at least one conductive layer. Firstly, a chemical vapor deposition (CVD) process is performed to form a dielectric layer covering the conductive layer on the surface of the substrate. Then at least one via plug is formed through the dielectric layer in the first region and electrically connected to the conductive layer. Then at least one metal pad electrically connected to the via plug is formed, and a flip-chip UBM process is performed to cover the surface of the metal pad in the first region and the dielectric layer in the second region. At least one flip chip under bump metallurgy layer (UBM layer) is formed on each surface. Finally, a solder bump is formed on each of the metal layers under the ball of the flip-chip. Wherein the solder bump formed in the second region is used as a dummy solder bump to improve the flow stability of the under fill liquid compound in the subsequent packaging (packaging) process of the substrate .

The advantages of the present invention are:

Since the dummy solder bumps of the present invention are formed on the flip-chip under-ball metal layer, and the flip-chip under-ball metal layer is directly formed on the surface of the dielectric layer, there is no need to form a solder bump as in the conventional manufacturing method. A metal pad is formed on the surface of the dielectric layer prior to the flip-chip UBM layer, so the problem of parasitic capacitance around the wires caused by the conventional manufacturing method can be avoided. Therefore, the manufacturing method of the present invention can greatly improve the fluidity stability of the liquid bottom seal on the substrate in the subsequent packaging process without affecting the product performance, thereby improving the product yield.

In order to have a further understanding of the structure, manufacturing method and effects of the present invention, specific embodiments are listed hereby and detailed descriptions are as follows in conjunction with the accompanying drawings:

Description of drawings

1 to 4 are schematic diagrams of a conventional manufacturing method of a solder bump structure.

FIG. 5 to FIG. 9 are schematic diagrams of the manufacturing method of the solder bump structure avoiding the generation of parasitic capacitance according to the present invention.

Detailed ways

Please refer to FIG. 5 to FIG. 9 . FIG. 5 to FIG. 9 are schematic diagrams of a manufacturing method of a parasitic capacitance-preventing dummy solder bump structure according to the present invention. As shown in FIG. 5 , the surface of the substrate 40 includes a first region 42 , a second region 44 and at least one patterned conductive layer 46 . Wherein, the base 40 is a semiconductor chip, and an integrated circuit is formed in the semiconductor chip; the first area 42 is the central area of the surface of the base 40 , and the second area 44 is the peripheral area of the surface of the base 40 .

As shown in FIG. 6 , a chemical vapor deposition (chemical vapor deposition, CVD) process is first performed to form a dielectric layer 48 covering the conductive layer 46 on the surface of the substrate 40 and made of silicon nitride or silicon oxide, and A protective layer 50 also formed of silicon nitride or silicon oxide is then formed on the dielectric layer 48 . In addition, in other embodiments of the present invention, a dielectric layer 48 made of silicon nitride or silicon oxide may also be formed on the surface of the substrate 40 to cover the conductive layer 46 .

As shown in FIG. 7 , an etching process is then performed to form at least one via hole (via hole) 52 penetrating through the dielectric layer 48 in the first region 42 until reaching the surface of the conductive layer 46 . A deposition process or a sputtering process is then performed to form a via plug (via plug) 54 electrically connected to the conductive layer 46 in each via hole 52, and then a chemical mechanical polishing (chemical mechanical polishing) is performed. , CMP) process, so that the surface of the via plug 54 is approximately tangent to the surface of the passivation layer 50 . Usually, the via plug 54 is made of titanium, titanium nitride and tungsten, and may also be made of titanium, titanium nitride, aluminum, copper or copper-aluminum alloy depending on the needs of the product or process.

As shown in FIG. 8, at least one metal pad 56 electrically connected to the via plug 54 is then formed, and a sputtering (sputtering) process and an etching process are performed to form the metal pad 56 surface in the first region 42 and the second metal pad 56. At least one underbump metallurgy layer (UBM layer) 58 is formed on the surface of the protection layer 50 in the region 44 .

Finally, as shown in FIG. 9 , a solder bump 60 is formed on each flip chip UBM layer 58 to complete the manufacturing method of the present invention. The solder bump 60 formed in the second region 44 is used as a dummy solder bump, so that the solder bump layout of the substrate 40 presents a symmetrical shape, so that in the subsequent packaging (packaging) process, The flow stability of the under fill liquid compound of the substrate 40 is enhanced.

It is worth noting that the metal pad 56 formed above the via plug 54 is used to increase the good bonding between the flip-chip under-ball metal layer (UBM layer) 58 and the via plug 54, so the second region There are no metal pads 56 formed within 44. Even in other embodiments of the present invention, no metal pad 56 may be formed at all, either under the solder bump 60 in the first region 42 or under the dummy solder bump 60 in the second region 44 .

Compared with the manufacturing method of forming the metal pad 24 on the surface of the dielectric layer 18 in the prior art, and then forming the flip-chip under-ball metal layer 28 on the surface of the metal pad 24, the method for manufacturing the dummy solder bump of the present invention is based on After performing a sputtering process to form a metal layer 58 under each flip-chip ball on the surface of the metal pad 56 in the first region 42 and the surface of the protective layer 50 in the second region 44, then under each flip-chip ball A solder bump 60 is respectively formed on the metal layer 58, and the solder bump 60 formed in the second region 44 is used as a dummy solder bump, so that the layout of the solder bump on the substrate 40 presents a symmetric shape for subsequent During the encapsulation process, the flow stability of the liquid bottom sealant of the substrate 40 is improved. Therefore, when the process line width gradually shrinks and the thickness of the dielectric layer 48 is reduced synchronously due to product specifications, the manufacturing method of the present invention can effectively avoid the metal pads and surrounding wires under the dummy solder bumps caused by the conventional manufacturing method The problem of parasitic capacitance (parasitic capacitance) is generated, and then without affecting the performance of the product, the fluidity stability of the liquid bottom seal of the substrate 40 in the subsequent packaging process is greatly improved, and the product yield rate is improved.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the patent of the present invention.

Claims (17)

1. A dummy solder bump structure that avoids generation of parasitic capacitance, the dummy solder bump structure is formed on a substrate, the dummy solder bump structure includes: at least one conductive layer formed on the surface of the substrate; a dielectric layer formed on the surface of the substrate and covering the conductive layer; a flip chip under ball metallization layer formed on the surface of the dielectric layer; and A solder bump is formed on the flip-chip UBM layer. 2. The dummy solder bump structure for avoiding parasitic capacitance according to claim 1, wherein the substrate is a semiconductor chip, and an integrated circuit is further formed in the semiconductor chip, and the dielectric layer includes at least one A deposited layer formed by a chemical vapor deposition process is used as a protective layer. 3. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 2, characterized in that: the deposited layer contains silicon nitride or silicon oxide. 4. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 1, wherein the flip chip under-ball metal layer is formed by a metal layer formed by a sputtering process. 5. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 1, characterized in that: a plurality of solder bump structures are additionally formed on the surface of the dielectric layer. 6. The virtual solder bump structure for avoiding parasitic capacitance according to claim 5, characterized in that: each of the solder bump structures includes: a metal pad formed on the surface of the dielectric layer; a flip-chip under-ball metal layer formed on the surface of the metal pad; and A solder bump is formed on the flip-chip UBM layer. 7. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 6, characterized in that: each of the solder bump structures further comprises at least one via layer plug for electrically connecting each of the solder bump structures with each other. The corresponding conductive layer below. 8. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 5, characterized in that: the solder bump structure is disposed on the central area of the substrate surface, and the dummy solder bump structure is disposed on The peripheral area of the surface of the base is surrounded by at least one solder bump structure mentioned above. 9. The dummy solder bump structure for avoiding generation of parasitic capacitance according to claim 1, characterized in that: the dummy solder bump structure is used to improve the flow stability of the liquid bottom sealant in the subsequent packaging process of the substrate . 10. A method for forming solder bumps on a substrate surface as claimed in claim 1, the substrate surface comprising at least one conductive layer, and the substrate surface is divided into a first region and a second region, the The method includes the following steps: forming a dielectric layer on the surface of the base and covering the conductive layer; forming at least one via plug penetrating through the dielectric layer in the first region and electrically connecting the conductive layer; forming at least one metal pad electrically connected to the via plug; performing a flip-chip UBM process to form at least one flip-chip UBM layer on the surface of the metal pad in the first region and the surface of the dielectric layer in the second region; and A solder bump is formed on each of the flip-chip UBM layers. 11. The method for forming solder bumps on a substrate surface according to claim 10, characterized in that: after the step of forming a dielectric layer on the substrate surface and covering the conductive layer and forming at least one through the first Before the step of connecting the dielectric layer in a region and electrically connecting the conductive layer via layer plug, it also includes forming a protection layer on the dielectric layer. 12. The method for forming solder bumps on the surface of a substrate as claimed in claim 11, wherein the dielectric layer and the passivation layer are composed of silicon nitride or silicon oxide. 13. The method for forming solder bumps on a substrate as claimed in claim 10, wherein the via plug is made of titanium, titanium nitride, tungsten, aluminum, copper or copper-aluminum alloy. 14. The method of forming solder bumps on a substrate as claimed in claim 10, wherein the flip chip UBM layer is formed by a sputtering process. 15. The method for forming solder bumps on the surface of a substrate according to claim 10, wherein the solder bumps formed in the second region are used as a dummy solder bumps to enhance the substrate surface. The fluidity of the liquid bottom sealant in the subsequent encapsulation process is stable. 16. The method for forming solder bumps on a surface of a substrate as claimed in claim 10, wherein the substrate is a semiconductor chip, and an integrated circuit is further formed in the semiconductor chip. 17. The method of forming solder bumps on a substrate surface as claimed in claim 10, wherein the first region is a central region of the substrate surface, and the second region is a peripheral region of the substrate surface.

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