CN1306824C - Image boundarg pixel extending system and its realizing method - Google Patents

Abstract

The present invention relates to an image boundary pixel extension system and an extension method in a video decoding chip. The system includes a reconstruction frame storage circuit, a variable length decoder sends a control command signal to the reconstruction frame storage circuit, and an intra-frame prediction circuit sends a reconstruction frame storage circuit The data is transmitted, and the memory controller stores and processes the output data of the reconstructed frame storage circuit. The reconstructed frame storage circuit includes a control command memory, an image data memory and an image boundary pixel expansion module circuit, and the control command memory stores the control command input by the variable-length decoder. signal, the image data memory stores the image data input by the intra-frame predictor with variable length of digits, the image boundary pixel expansion module circuit analyzes the image control signal, and repeatedly expands the edge and corner pixels outward, and the expanded pixel data is stored in dynamic memory. The invention can obtain great coding gain, expand the range of the motion vector, and greatly improve the efficiency of the digital video decoding chip.

Description

Image Boundary Pixel Extension System and Its Realization Method

technical field

The present invention relates to the technical field of digital video encoding and decoding in digital television image processing, in particular to an image boundary pixel expansion system in a video decoding chip and its implementation method. When it is outside, the image pixel value of its edge is used to replace the non-existing macroblock (macroblock), so as to realize the decoding technology of unlimited motion vector.

Background technique

In the entire video decoding system, motion compensation is an important link. The motion vector is the basis for motion compensation. In the prior art, the range of the general motion vector is limited within the coded reference frame. This limitation makes it impossible to obtain optimal results when performing motion estimation on the macroblocks at the boundary of the current frame image because the reference macroblocks may already be outside the reference frame. Compression standards before the Motion Picture Experts Group standard MPEG-2 And this is the case in the International Telecommunication Union video codec standard H.261. This restriction is removed in H.263, MPEG-4, and China's audio and video codec national standard AVS1.0, allowing motion vectors to point to areas outside the image. However, the technology allowed by the standard has never been implemented

Contents of the invention

In order to solve the deficiencies of the prior art, the purpose of the present invention is to provide an image boundary pixel expansion system and its implementation method, so as to improve the coding gain when motion vectors are allowed to point to areas outside the image.

Another object of the present invention is to provide an image boundary pixel expansion system and its implementation method, which allow the use of larger motion vectors and expand the range of motion vectors, so as to improve the efficiency of digital video decoding.

In order to accomplish the above-mentioned purpose, the overall technical solution adopted by the present invention is: an image boundary pixel extension system, including a variable-length decoder, an intra-frame prediction circuit, a memory controller, an inverse quantization circuit, an inverse transformation circuit, a dynamic memory and a motion compensation circuit, The variable-length decoder is connected with other devices through the command bus and the control bus. There is a motion compensation circuit between the variable-length decoder and the intra-frame prediction circuit. The system also includes a reconstructed frame storage circuit. The variable-length decoder stores The circuit sends a control command signal, the intra-frame prediction circuit transmits data to the reconstructed frame storage circuit, and the memory controller stores and processes the output data of the reconstructed frame storage circuit, and the reconstructed frame storage circuit includes image control information storage, image data storage and image boundary pixels The expansion module circuit, the image control information memory stores the control command signal input by the variable length decoder, the image data memory stores the image data input by the intra-frame predictor, the image boundary pixel expansion module circuit analyzes the image control signal, and converts the edge and corner pixels The expansion is repeated outward, and the expanded pixel data is stored in the dynamic memory.

The image control information memory is a register array with a bit width of 32 bits and a depth of 8.

The image data memory is two RAMs with a width of 64 bits and a depth of 48 bits, which converts 64-bit input data into 128-bit data for output.

The image control signal input by the variable length decoder at least includes clock synchronization signal, write command and data command, command data and image information data.

The format of the image control information input by the variable length decoder includes initialization information, image sequence level information, frame level information, and macroblock level information; the initialization information includes initialization signals, and 0-15 of the 32 bits of the initialization information Bits provide image logical storage width; 2-13 bits of the image sequence level information indicate the width of each frame in the image sequence, and 14-29 bits of the image sequence level information indicate the height of each frame in the image sequence ; 6-25 bits of frame-level information mark the base address of each frame of image; 0-6 bits of macroblock-level information mark the vertical relative address of macroblock in each frame of image, and 7-13 bits of said macroblock-level information Mark the relative address of the macroblock in the horizontal direction in each frame of image.

The output information of the image control information memory at least includes: a memory command fed back to the variable length decoder, and a read data command stored in the image boundary pixel expansion module circuit.

The image data information input by the intra predictor to the image data storage at least includes a clock synchronization signal, a write data command, and input data.

The information output from the image data memory to the image boundary pixel expansion module circuit at least includes: a memory command fed back to the intra-frame predictor, and a read data command stored in the main module.

An extension method of an image boundary pixel extension system, the system includes a variable length decoder, an intra-frame prediction circuit, a memory controller, an inverse quantization circuit, an inverse transformation circuit, a dynamic memory, a motion compensation circuit and a reconstruction frame storage circuit, and the method at least includes The following steps:

Step 1, the variable length decoder sends control information to the image control information storage of the reconstructed frame storage module;

Step 2, the image control information storage device sends image information data to the image boundary pixel expansion module circuit;

Step 3, the image boundary pixel expansion module circuit judges whether to expand the image to the boundary pixel, and then receives the image data stream transmitted by the intra-frame predictor into the image data stream memory, and executes step 4; otherwise, it ends;

Step 4, the image boundary pixel expansion module circuit combines the data in the two memories to establish an image model, and repeatedly expands the edge and corner pixels outward;

Step 5. Store the expanded data in the dynamic memory.

The image data sent by the image control information memory in the step 2 to the image boundary pixel expansion module circuit is 128-bit data converted from the input 64-bit data.

The described conversion of the input 64-bit data into 128-bit data specifically includes the following conversion steps:

Step 21, the intra-frame prediction circuit module IP takes 64 bits as the unit, writes 8 numbers at a time, writes the image data stream into the image data stream memory, and writes every 8 numbers into the random access memory where the row is selected as 0 and 1 middle;

Step 22, the image data stream memory judges whether the data has been stored, and if so, reads out the 128-bit data in the two RAMs of 0 and 1 as a whole, and executes step 23; otherwise, it ends;

Step 23, sending the read data into the image boundary pixel expansion module circuit.

Repeated expansion of the edge and corner pixels outward in the step 4 refers to: in the horizontal direction, respectively expand 16 pixel pixels from left to right; in the vertical direction, expand 8 pixel pixels for UV; Y expands each pixel by 16pixel.

Said step 4 further comprises:

Step 41. Determine the mode and type of the decoded code stream. If the decoded code stream is in the frame-in mode, perform the following expansions: For brightness Y, the expansion of the MB unit at the periphery is directly expanded 16 times in units of edge pixels, and the corner The expansion at the corner is based on the corner pixel of the MB at the corner, and the expansion is repeated 16×16 times. For the chroma UV, the border pixel units of U and V are synthesized in the left and right directions respectively, and a U pixel unit and a U pixel unit are combined. V pixel unit as a whole, expand 8 times to the left or right respectively, expand 8 times after crossing U and V in the up and down direction, and at the corner, the corner point pixel unit of U and the corner point pixel of V The unit is integrated into one, expanding 16×8 times;

Step 42. If the decoded code stream is in the field-in mode, then further judge whether it is the top field or the bottom field. If the incoming code stream is the top field, then use the first line to calculate the address as the standard, and perform address calculations in alternate lines based on the jump address Store data to the dynamic memory, and expand pixels to the top left and top right, to the left and right and the top edge of the image according to the method in step 41;

Step 43, if the input code stream is the bottom field, take the first line to calculate the address as the criterion, and perform address calculation on an interlaced basis, store data in the dynamic memory with the jump address, and transfer the data to the bottom left, bottom right, and bottom of the image according to the method in step 41. The left and right and bottom edges are expanded by pixels.

The storage in the step 5 specifically includes the following steps:

Step 51. Determine the mode and type of the decoded code stream. If the decoded code stream is frame-in mode, for brightness Y, if it is the main part of the image, the address is directly calculated and written to the dynamic memory. If it is an extension part, the address is calculated. Under the premise, write it into the dynamic memory in the order of expansion. For the chroma UV, if it is the main part, calculate the address, and store U and V in the dynamic memory after crossing. If it is the extension part, after calculating the address Under the premise, write to the dynamic memory in the order of expansion;

Step 52. If the decoded code stream is input in the field-forward mode, for the brightness y, if it is the main part, directly calculate the address and write it into the dynamic memory; The storage addresses of the top right, left, and right data are then stored. For the bottom field, it is necessary to calculate the storage addresses of the data extended to the bottom left, bottom, bottom right, left, and right, and then write them into the dynamic memory in the order of expansion. , for chroma UV, if it is the main part, calculate the address, store U and V in the dynamic memory after crossing, if it is the extension part, for the top field, you need to calculate and expand to the top left, top edge, top right, and left , the storage address of the data on the right side, and then store it. For the bottom field, it is necessary to calculate the storage address of the data extended to the bottom left, bottom side, bottom right, left side, and right side, and then write them into the dynamic memory in the order of expansion.

The present invention has obvious advantages and positive effects. The image boundary pixel extension system and its implementation method of the present invention realize the hardware extension system and extension method of boundary pixel extension, allowing the motion vector to point to the area outside the image, when the reference macroblock pointed by a certain motion vector is located outside the coded image , replace the non-existing macroblock with the image pixel value of its edge. The present invention expands the range of motion vectors and allows the use of larger motion vectors. When there are motion vectors crossing boundaries, a large coding gain can be obtained, and the improvement of coding gain can be realized, especially for small images, the effect is better good. At the same time, the method of the present invention also saves hardware storage space and improves data processing efficiency, and the application of two-dimensional storage increases the speed of hardware processing. It is especially suitable for decoding chips of digital video equipment such as digital cameras.

Description of drawings

Fig. 1 is a system configuration diagram of the present invention;

Fig. 2 is a structural schematic diagram of the reconstructed frame memory of the present invention;

Fig. 3 is a schematic diagram of the image control command information memory command input and output of the present invention;

Fig. 4 is a schematic diagram of data input and output of the image data memory of the present invention;

Fig. 5 is a schematic diagram of the working principle of the data storage of the image data memory of the present invention;

6 is a schematic diagram of the circuit data input and output architecture of the image boundary pixel expansion module of the present invention;

Fig. 7 is a schematic diagram of the overall layout of boundary pixels expanding to the boundary in the present invention;

Fig. 8 is a schematic diagram of the expansion process of boundary pixels to the top left and top right in the frame forward mode of the present invention;

Fig. 9 is a schematic diagram of the expansion process of border pixels to the bottom left and bottom right in the frame forward mode of the present invention;

Fig. 10 is a schematic diagram of the expansion process of the border pixel image top, left, bottom, and right in the frame-forward mode of the present invention;

Fig. 11 is a schematic diagram of the storage process of the main part under the frame forward mode of the present invention;

FIG. 12 is a schematic diagram of the boundary pixel expansion process for chroma in the frame-forward mode of the present invention;

FIG. 13 is a schematic layout diagram of the border pixel expansion process in the field-in mode of the present invention;

Fig. 14 is a schematic diagram of the interface between the output interface and the dynamic memory of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

Please refer to Figure 1, image boundary pixel expansion system, including variable length decoder VLD, intra prediction circuit (IP, Intra prediction), memory controller (SRAM Controller), inverse quantization circuit, inverse transformation circuit, dynamic memory (DRAM) And the motion compensation circuit, the variable length decoder is connected with other devices through the command bus and the control bus, there is a motion compensation circuit between the variable length decoder and the intra-frame prediction circuit, and the reconstructed frame storage circuit (REFERENCE STORE) and the intra-frame prediction circuit connected, and connected to the variable-length decoder through the command bus, the variable-length decoder sends a control command signal to the reconstructed frame storage circuit, the intra-frame prediction circuit transmits data to the reconstructed frame storage circuit, and the memory controller outputs to the reconstructed frame storage circuit The data is stored and processed, and the frame reconstruction circuit includes two first-in-first-out memories and an image boundary pixel expansion module circuit. The front and rear two memories store the input control command signal and image data stream, and the image boundary pixel expansion module circuit analyzes the image control signal. , repeatedly expand the edge and corner pixels outward, and store the expanded pixel data into the dynamic memory.

Please refer to Figure 2, the reconstructed frame storage circuit mainly includes three parts, two first-in-first-out memories (FIFO) and the main module image boundary pixel expansion module circuit (ref_store), the two memories refer to storing the image control input by the variable-length decoder The information memory CMDFIFO and the memory DATAFIFO store the decoded image data input by the intra prediction circuit.

The expansion method of the image boundary pixel expansion system of the present invention mainly has the following steps:

First, the variable length decoder VLD sends control information to the image control information memory CMDFIFO of the reconstruction frame storage module (REFRENCE STORE);

Afterwards, the image control information memory CMDFIFO sends image information data to the image boundary pixel expansion module circuit ref_store;

Next, the image boundary pixel expansion module circuit ref_store judges whether to expand the image to the boundary pixel, and if so, receives the image data stream transmitted by the intra-frame predictor IP to the DATAFIFO in the image data stream memory; otherwise, it ends;

Then, the image boundary pixel expansion module circuit ref_store combines the data in the two memory FIFOs to establish an image model, and repeatedly expands the edge and corner pixels outward;

Finally, the expanded data is stored in the dynamic memory DRAM.

Please refer to Figure 3, the image control information memory is a register array with a bit width of 32 bits and a depth of 8, and the image control information CMD input by the variable length decoder to the image control information memory includes a clock synchronization signal, a reset command, a write command and data Command, command data and image data, and memory correct response and end signal. Its input and output information are as follows:

Input: I_CLK I_DATA_WR

I_CLK_INV I_DATA

I_RESET I_SRAM_ACK

I_CMD_WR I_SRAM_END

I_CMD_DATA

output:

O_CMD_FIFO_FULL O_SRAM_SIZE

O_DATA_FIFO_FULL O_SRAM_LINES

O_SRAM_REQ O_SRAM_PITCH

O_SRAM_ADDR O_SRAM_WDATA

The image control information memory output information includes: memory commands and data overflow information fed back to the variable length decoder, read data commands stored in the image boundary pixel expansion module circuit, and main memory module requests, addresses and their sizes, lines, positioning and Write data command.

The CMD image control signal sent by VLD to the image boundary pixel expansion module circuit REFERENCE STORE contains the following information:

1, 4 commands

0initial (initialization level)

1seq (sequence level)

2frm (frame level)

3mb (macroblock level)

The specific format allocation of cmd data information is shown in Table 1: LEVEL0 contains the initialization signal, and the DRAM width is provided by bits 0-15 of the 32bit, thereby determining the image width of the logical storage. LEVEL1 contains information at the image sequence level, its 2-13 bits mark the width of each frame in this image sequence (img-width), and 14-29 bits mark the height of each frame in this image sequence (img-height) . LEVEL2 contains frame-level information, and its 6-25 bits mark the base address of each frame of image. LEVEL3 contains macroblock-level information, its 0-6 bits indicate the vertical relative address (mb-y) of the macroblock in each frame of image, and its 7-13 bits indicate the horizontal relative address of the macroblock in each frame of image (mb-x). The 30-31 bits of the cmd data are used as the flag bits of the image information level.

Table 1 level=0 (Initialization level); DRAM width 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRAM width level=1(seq Level); 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level Img width 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Img height level=2(Ftame Level) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level DRAM Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 for the pic to be stored top_field_first Frm/Fld Note: 1.frame/field type 1->frame 0->field1.top field_first 1->top field first 0->bottom field first level=3(mb level) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mb_x Mb_y

1. CMD number: 1/app 1/sequence 1/frm 1/mb

2. Parameters:

1) img height and img width

2) DRAM Address

3) mbx and mby

2. CMD data stream format

The initial image control information data flow is shown in Table 2.

Table 2 Level0 lnitializatio Level seq Level2 pic Level3 MB Level3 MB no 1

Each frame of image control information data flow is shown in Table 3.

table 3 Level2 pic Level3 MB Level3 MB Level3 MB 5

Referring to Fig. 4, the image data memory stores the decoded image data DATA transmitted by the frame prediction circuit (IP, Intra-Prediction), and provides image expansion (padding) data for the image boundary pixel expansion module circuit ref_store At the same time, it also provides a bridge function for the direct output of image data that does not need to be expanded.

The information that the intra-frame prediction circuit inputs the decoded image data memory to the reconstructed frame memory includes a clock synchronization signal, a reset command, a write data command, a data transmission ready command, and a data input command. The information output from the image data memory to the main module includes: memory commands and data overflow information fed back to the intra-frame predictor, and read data commands stored in the main module.

Please refer to Figure 5, the image data memory is two RAMs with a width of 64bit and a depth of 48, which can convert 64bit input data into 128bit data output. Converting 64bit input data to 128bit data output is achieved by changing the way of storage. The specific way is:

1. Write data: The image data stream written by IP is based on 64bit, 8 numbers are written each time, and the 8 numbers written for the first time are put into the 64bit RAM whose row is selected as 0, as shown in Figure 5 In the RAM on the left, the 8 numbers written for the second time are put into the 64bit RAM whose row is selected as 1, as shown in the right RAM in Figure 5, and the 8 numbers written for the third time are put into the RAM whose row is selected as 0 , the 8 numbers written for the fourth time are put into the RAM whose row is selected as 1, and so on, storing all the input image data streams.

2. Read data: the two RAMs are read out as a whole, that is, Y0Y1 starts writing a 128-bit number to the DRAM as a whole.

Please refer to Figure 6, the image boundary pixel expansion module circuit ref_store is used as the main module of the reconstruction frame memory REFERENCE STORE, it needs to analyze the cmd image control signal sent by the variable length encoder to the image control command information memory of the reconstruction frame memory, and at the same time it needs to be combined The cmd image control signal identifies the current image data type: frame advance mode, top field advance mode, and bottom field advance mode, and calculates the storage head address sent to the dynamic memory accordingly, and at the same time performs the image data stream data sent by the intra-frame prediction circuit Extended processing padding, and the need to process the cross output of pixels in U and V.

Please refer to Figure 7, the image to be processed is divided into nine cases, and the extended PADDING involves the boundary part of the image. The character strings and Arabic numerals in the figure are used as the identification of the nine cases of the image in the code. The range of extension is: in the horizontal direction, expand 16 pixels from the left to the right; in the vertical direction, for the chroma UV, only need to expand 8pixel1, and for the brightness Y, expand 16pixel. It is formed by repeated expansion of the edge pixel unit of the boundary macroblock (mb). The expansion method is:

The expansion in the left and right directions to the top and bottom is shown in Figure 8 and Figure 9, and the order of expansion is: start from the main part MAIN, and expand according to abcdefghijkl.

1.TOP_LEFT; 3.BOT_LEFT;

2. TOP_RIGHT; 4. BOT_RTGHT.

The expansion in the direction of the top, bottom, left, and right is shown in Figure 10. The order of expansion is: starting from the main part MAIN, and expanding according to abcdef.

5. TOP_EDGE; 6. BOT_EDGE;

7. LEFT_EDGE; 8. RIGHT_EDGE

The sequence of the main part MAIN is shown in Figure 11: proceed according to abc.

The general trend of the order of expansion is clockwise, which has higher data processing efficiency and saves storage space. For example, first take out the data that needs to be expanded, which is the luminance component (y0y1) of the top left MB, and start to expand related to the block (y0y1) after obtaining the data: expand to the left to form the luminance component (y0y1) of the left extended part, Store in the dynamic memory at the same time; Then expand to the luminance component (y0y1) of the upper left corner extension part, store in the dynamic memory at the same time; Then expand to the luminance component (y2y3) of the upper left corner extension part, store in the dynamic memory at the same time; Then The luminance component (y0y1) extended to the upper extended part is stored in the dynamic memory at the same time; the luminance component (y2y3) extended to the upper extended part is stored in the dynamic memory at the same time; like this and the luminance component of the top left macroblock MB (y0y1) related expansion processing is done, and all the data are stored at the same time, then start to consider (y2y3) of the luminance component of the top left macroblock (MB), after the same method is completed, start the top left macroblock MB The (uv) pixel extension of the chroma component. The pixel expansion of other boundary parts also follows this principle for boundary pixel expansion. This has two advantages: first, the process of processing is also a process of storing data in the dynamic memory, so that the data required for pixel expansion can be saved without first storing the data required for pixel expansion, which saves storage space; second, the main Only the data to be used is obtained for processing, instead of obtaining the data of the entire macroblock and then expanding the boundary pixels, which reduces data redundancy and improves the efficiency of data processing. The storage method is to provide a line number signal lines each time, and only calculate the first address of the lines×16pixel block, and then, the controller of the memory only needs one request signal to the memory controller according to the first address and the number of lines. The lines row data can be sequentially written to the dynamic memory, thereby realizing two-dimensional storage.

Please refer to Figure 11, the method of expansion is: in the frame-forward mode, for the brightness Y, the expansion of the macroblock MB unit at the periphery is directly expanded 16 times in units of edge pixels, and the expansion at the corner is performed at the corner The corner pixel of the MB is repeatedly expanded outward 16×16 times.

As shown in Figure 12, for the chromaticity UV, the extension method is: in the left and right directions, the boundary pixel units of U and V are synthesized into a whole with a U pixel unit and a V pixel unit as a unit, respectively. Extend left or right 8 times, cross U and V in the up and down direction and expand 8 times respectively, at the corner, combine the corner pixel unit of U and the corner pixel unit of V into one, expand 16×8 times .

As shown in Figure 13, if the decoded code stream is in the field entry mode, it is further judged whether it is the top field or the bottom field. If the incoming code stream is the top field, the address stored in the DRAM needs to jump: the address calculated in the first line shall prevail , interlace and then address calculation, such as 1357.... It is necessary to expand the top-left TOPLEFT, top-right TOPRIGHT, bottom-left BOTLEFT, bottom-right BOTRIGHT, left-left LEFTEDGE, right-right RIGHTEDGE, top-side TOPEDGE, and bottom-side BOTEDGE.

If the entering code stream is the bottom field, the address stored in the dynamic memory DRAM needs to jump: the address calculation is based on the first line, and the address calculation is performed on every other line, such as 2468.... It is necessary to expand the top-left TOPLEFT, top-right TOPRIGHT, bottom-left BOTLEFT, bottom-right BOTRIGHT, left-left LEFTEDGE, right-right RIGHTEDGE, top-side TOPEDGE, and bottom-side BOTEDGE.

Please refer to Figure 14, the expanded data will be stored in the dynamic memory. If the decoding code stream is in the frame-in mode, then for the brightness Y, if it is the main part of the image, the address is directly calculated and written to the DRAM. If it is the extended PADDING part, the address is calculated in the order of expansion. Write to DRAM. For chroma UV, if it is the MAIN part, calculate the address and store it in DRAM after interleaving. If it is the PADDING part, on the premise of calculating the address, write it into DRAM in the order of expansion after crossing;

As shown in Figure 13, if the decoded code stream is input in the field advance mode, then for the brightness Y, if it is the MAIN part, directly calculate the address and write it to DRAM; if it is the PADDING part, for the top field, the calculation needs to be extended to the top left TOPLEFT, top right TOPRIGHT, bottom left BOTLEFT, bottom right BOTRIGHT, left LEFTEDGE, right RIGHTEDGE, top edge TOPEDGE, bottom edge BOTEDGE data storage addresses, and then store them. For the bottom field, the calculation needs to be extended to top left TOPLEFT, top right The storage address of the data of TOPRIGHT, bottom left BOTLEFT, bottom right BOTRIGHT, left LEFTEDGE, right RIGHTEDGE, top edge TOPEDGE, bottom edge BOTEDGE, and then write to DRAM in order of expansion. For chroma UV, if it is the MAIN part, Calculate the address intersection and store it in DRAM. If it is the PADDING part, for the top field, the calculation needs to be extended to the top left TOPLEFT, top right TOPRIGHT, bottom left BOTLEFT, bottom right BOTRIGHT, left LEFTEDGE, right RIGHTEDGE, top TOPEDGE, bottom BOTEDGE The storage address of the data, and then store it. For the bottom field, it is necessary to calculate the storage of the data extended to the top left TOPLEFT, top right TOPRIGHT, bottom left BOTLEFT, bottom right BOTRIGHT, left LEFTEDGE, right RIGHTEDGE, top edge TOPEDGE, and bottom edge BOTEDGE address, and then written to DRAM in expansion order.

Finally, it should be noted that the above embodiments are only used to illustrate and not limit the technical solutions of the present invention, although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: the present invention can still be modified Or an equivalent replacement, any modification or partial replacement without departing from the spirit and scope of the present invention shall fall within the scope of the claims of the present invention.

Claims (14)

1. Image boundary pixel expansion system, including variable length decoder, intra-frame prediction circuit, memory controller, inverse quantization circuit, inverse transformation circuit, dynamic memory and motion compensation circuit. The variable length decoder communicates with other The device is connected, and there is a motion compensation circuit between the variable-length decoder and the intra-frame prediction circuit. It is characterized in that the system also includes a reconstruction frame storage circuit, and the variable-length decoder sends a control command signal to the reconstruction frame storage circuit. The prediction circuit transmits data to the reconstructed frame storage circuit, and the memory controller stores and processes the output data of the reconstructed frame storage circuit. The reconstructed frame storage circuit includes an image control information memory, an image data memory and an image boundary pixel expansion module circuit, and an image control information memory Store the control command signal input by the variable-length decoder, the image data memory stores the image data input by the intra-frame predictor, the image boundary pixel expansion module circuit analyzes the image control signal, and repeatedly expands the edge and corner pixels outward, and the expanded Pixel data is stored in dynamic memory. 2. The image boundary pixel expansion system according to claim 1, wherein the image control information memory is a register array with a bit width of 32 bits and a depth of 8. 3. The image boundary pixel expansion system according to claim 1, characterized in that, the image data memory is two RAMs with a width of 64 bits and a depth of 48 bits, and converts 64-bit input data into 128-bit data output. 4. The image boundary pixel expansion system according to claim 1, wherein the image control signal input by the variable length decoder at least includes clock synchronization signal, write command and data command, command data and image data. 5. The image boundary pixel expansion system according to claim 2, wherein the format of the image control information input by the variable length decoder includes initialization information, image sequence level information, frame level information, and macroblock level information ; The initialization information includes an initialization signal, and bits 0 to 15 of the 32 bits of the initialization information provide the image logic storage width; bits 2 to 13 of the information at the image sequence level mark the width of each frame of the image in the image sequence, and the image sequence The 14-29 bits of the level information mark the height of each frame image in this image sequence; the 6-25 bits of the frame-level information mark the base address of each frame image; the 0-6 bits of the macroblock level information mark the macroblock in each frame The vertical relative address in the image, the 7-13 bits of the macroblock level information indicate the horizontal relative address of the macroblock in each frame of image. 6. The image boundary pixel extension system according to claim 1, wherein the output information of the image control information memory at least includes: a memory command fed back to the variable length decoder, a memory command stored in the image boundary pixel extension module circuit Read data command. 7. The image boundary pixel expansion system according to claim 1, wherein the image data information input by the intra predictor to the image data storage at least includes a clock synchronization signal, a write data command, and input data. 8. The image boundary pixel expansion system according to claim 2, characterized in that the information output from the image data memory to the image boundary pixel expansion module circuit at least includes: a memory command fed back to the intra predictor, a storage direction The read data command of the main module. 9. An expansion method of an image boundary pixel expansion system, the system comprising a variable length decoder, an intra-frame prediction circuit, a memory controller, an inverse quantization circuit, an inverse transformation circuit, a dynamic memory, a motion compensation circuit and a reconstruction frame storage circuit, its characteristics In that, the method at least includes the following steps: Step 1, the variable length decoder sends control information to the image control information memory of the reconstructed frame storage module; Step 2, the image control information storage device sends image information data to the image boundary pixel expansion module circuit; Step 3, the image boundary pixel expansion module circuit judges whether to carry out image boundary pixel expansion, and then receives the image data stream transmitted by the intra-frame predictor into the image data stream memory, and executes step 4; otherwise, it ends; Step 4, the image boundary pixel expansion module circuit combines the data in the two memories to establish an image model, and repeatedly expands the edge and corner pixels outward; Step 5. Store the expanded data in the dynamic memory. 10. The expansion method of the image boundary pixel expansion system according to claim 9, characterized in that the image data sent by the image control information memory in the step 2 to the image boundary pixel expansion module circuit is the input 64-bit data Converted into 128-bit data. 11. The extension method of the image boundary pixel extension system according to claim 10, characterized in that said converting the input 64-bit data into 128-bit data specifically includes the following conversion steps: Step 21, the intra-frame prediction circuit module IP takes 64 bits as the unit, writes 8 numbers at a time, writes the image data stream into the image data stream memory, and writes every 8 numbers into the random access memory where the row is selected as 0 and 1 middle; Step 22, the image data stream memory judges whether the data has been stored, and if so, reads out the 128-bit data in the two RAMs of 0 and 1 as a whole, and executes step 23; otherwise, it ends; Step 23, sending the read data into the image boundary pixel expansion module circuit. 12. The extension method of the image boundary pixel extension system according to claim 9, characterized in that, in the step 4, repeatedly expanding the edge and corner pixels outward refers to: in the horizontal direction, from left to right 16 pixels are respectively expanded, and in the vertical direction, 8 pixels are expanded for the chrominance component UV, and 16 pixels are expanded for the luminance component Y. 13. The extension method of the image boundary pixel extension system according to claim 9, characterized in that the step 4 further comprises: Step 41. Determine the mode and type of the decoded code stream. If the decoded code stream is in the frame-in mode, perform the following expansions: For brightness Y, the expansion of the MB unit at the periphery is directly expanded 16 times in units of edge pixels, and the corner The expansion at the corner is based on the corner pixel of the MB at the corner, and the expansion is repeated 16×16 times. For the chroma UV, the border pixel units of U and V are synthesized in the left and right directions respectively, and a U pixel unit and a U pixel unit are combined. V pixel unit as a whole, expand 8 times to the left or right respectively, expand 8 times after crossing U and V in the up and down direction, and at the corner, the corner point pixel unit of U and the corner point pixel of V The unit is integrated into one, expanding 16×8 times; Step 42. If the decoded code stream is in the field-in mode, then further judge whether it is the top field or the bottom field. If the incoming code stream is the top field, then the first row is used as the basis for calculating the address, and the address calculation is performed alternately. The address stores data to the dynamic memory, and expands pixels to the top left and top right of the image, to the left and right and to the top edge according to the method in step 41; Step 43, if the input code stream is the bottom field, take the first line calculation address as the criterion, perform address calculation in an alternate line, store data in the dynamic memory with the jump address, and transfer the image to the bottom left, bottom right, Expand pixels to the left and right and bottom. 14. The extension method of the image boundary pixel extension system according to claim 9, characterized in that the storage in step 5 specifically includes the following steps: Step 51. Determine the mode and type of the decoded code stream. If the decoded code stream is frame-in mode, for brightness Y, if it is the main part of the image, the address is directly calculated and written to the dynamic memory. If it is an extension part, the address is calculated. Under the premise, write it into the dynamic memory in the order of expansion. For the chroma UV, if it is the main part, calculate the address, and store U and V in the dynamic memory after crossing. If it is the extension part, after calculating the address Under the premise, write to the dynamic memory in the order of expansion; Step 52. If the decoded code stream is input in the field-forward mode, for the brightness Y, if it is the main part, directly calculate the address and write it into the dynamic memory; The storage addresses of the top right, left, and right data are then stored. For the bottom field, it is necessary to calculate the storage addresses of the data extended to the bottom left, bottom, bottom right, left, and right, and then write them into the dynamic memory in the order of expansion. , for chroma UV, if it is the main part, calculate the address, store U and V in the dynamic memory after crossing, if it is the extension part, for the top field, you need to calculate and expand to the top left, top edge, top right, and left , the storage address of the data on the right side, and then store it. For the bottom field, it is necessary to calculate the storage address of the data extended to the bottom left, bottom side, bottom right, left side, and right side, and then write them into the dynamic memory in the order of expansion.

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