CN1118470A - Image processing apparatus - Google Patents

Abstract

In an apparatus provided with a frame memory for sequentially reading image data written in the frame memory for image display data, an image processing apparatus includes: a recognizing section for recognizing whether the image data written in the frame memory are image data in which each pixel is written with a first bit number or image data in which each pixel is written with a second bit number that is different from the first bit number; a second image data reading section for reading the image data from the frame memory, regarding each pixel as being expressed by the second bit number; and a switching section for switching the first image data reading section and the second image data reading section on the basis of the recognition information from the recognizing section.

Description

image processing device

The present invention relates to an image processing device with a frame memory for display, especially suitable for use in such occasions, that is, an image is formed from compressed or converted image data or image data of computer graphics For video game consoles or graphics computers that require high "display" performance.

Usually, in computer graphics such as so-called 3D (three-dimensional) graphics, when an "object" is actually displayed, the surface of the object is first decomposed into a plurality of polygons, and each polygon represents the object represented by an image device. The smallest unit of graphics to be processed (such as a triangle or a rectangle); each polygon is sequentially imaged in the frame memory corresponding to the monitor display image field; these imaged image data are stored in the frame memory; and, these data are read out and displayed on a monitor to reconstruct an image which can be displayed stereoscopically.

In some cases, a digital moving picture playback system such as an image playback system in which a secondary storage device such as a CD-ROM for recording image data in a data compression and image expansion device is used in combination with a The 3D image system is installed and used side by side. Such a digital motion picture playback system is inferior to a 3D graphics system in transformation characteristics, but has an advantage in that it can reproduce images that are difficult for a 3D graphics system to express. Therefore, the data motion picture playback system is used as a subsystem to assist the operation of the 3D graphics system when the 3D graphics system is used as a background image field.

In this way, a conventional image processing apparatus is equipped with a frame memory (buffer memory) for display, and the number of bits of image data written in the frame memory is generally kept constant. For example, in a device such as a game machine, since the picture image does not require high quality through the 3D image processing, each element constituting the three primary color data R (red), G (green) and B (blue) The number of bits for one pixel is maintained at 15 bits/pixel, 5 bits for each of R, G, and B, and the resolution is fixed at about 32,000 colors.

Each of the patent applications listed below related to the present invention is owned by the applicant and is incorporated herein by reference.

Japanese patent application, Heisei 05-190764 (application date is July 2, 1993)

Japanese patent application, Heisei 05-258625 (filing date is October 15, 1993) and

A Japanese patent application, Heisei 06-027405 (filing date 1/31/94) and a corresponding US patent application to these Japanese applications are currently pending.

As described above, conventionally, the number of bits of a frame memory used for one pixel is fixed. Therefore, when the moving picture is reproduced and played back in a combined system belonging to a 3D graphics system and a digital moving picture playback system, even if there is an extra space in the frame memory capacity, the bit The number is also determined to be 15 bits/pixel, and as a result only a resolution of 32,000 colors can be obtained.

Considering the display of moving images, it is possible to fix the number of bits per pixel of the frame memory to be 8 bits for R, G, B and 24 bits for each pixel (24 bits/pixel), so that Makes 16,700,000 colors displayed. In this case, however, the memory area of the frame memory used for display increases dramatically, and this number of bits is unnecessary for images of 3D graphics. This kind of program is not beneficial.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image processing apparatus which optimizes the number of bits per pixel of a frame memory in accordance with the quality of an image to be displayed.

In order to solve the above-mentioned problems, in the image processing apparatus according to the present invention, there is a display device for sequentially reading image data written in the frame memory to realize image display data, the image processing system is characterized in that include:

Identification means for identifying whether the image data written in the frame memory is image data written in a first number of bits per pixel or a second number of bits different from the first number of bits for each pixel the image data written;

The first image data reading device is used to read the image data about the first pixel represented by the first bit number from the frame memory;

A second image data reading means for reading image data about each pixel represented by the second bit number from the frame memory; and

switching means for switching the first image data reading means and the second image data reading means based on the identification information from the identification means.

According to the structure of the present invention, the identifying means identifies whether the image data on the frame memory is image data written in the first number of bits or image data written in the second number of bits.

When the image data to be read out from the frame memory according to the identification information of the identification means is the first bit number/pixel data, the switching means is switched to select the first image data reading means, so that the image data is output from the frame memory. like data. Also, when the image data read out from the frame memory is the second number of bits/pixel data, the switching means is switched to select the second image reading means to output the image data from the frame memory 63.

It is possible to optimize the image data read from and written into the frame memory while satisfying the image quality.

As described above, according to the present invention, it is possible to optimize the number of bits per pixel of the frame memory in response to the quality of an image to be displayed, and to utilize the frame memory efficiently.

Furthermore, according to the present invention, since the circuit for reading image data from the frame memory is switched in response to the number of bits/pixel corresponding to the image quality, the frame memory itself has no adverse effect on the change of the number of bits. Therefore, there is no need to use a special memory as a frame memory.

Moreover, if the present invention is applied to a game machine, since the moving image or still image is properly displayed with high quality except for the image according to the image forming command, it is possible to display it in a more realistic manner. Enjoy the game graphics.

Fig. 1 is a block diagram of an embodiment of an image processing apparatus according to the present invention.

Fig. 2 is a schematic diagram illustrating a storage area in this embodiment.

Fig. 3 is a schematic diagram illustrating an embodiment of polygonal imaging in this embodiment.

Fig. 4 is a schematic diagram illustrating the formation of polygons in this embodiment.

Fig. 5 is a diagram illustrating structural transformation.

Fig. 6 is a schematic diagram illustrating an example of the data structure in conversion to image data in this embodiment.

Fig. 7 is a diagram showing an example of an image of one frame.

Fig. 8 is a diagram illustrating a conversion unit of image data in this embodiment.

Fig. 9 is a diagram illustrating an example of the data structure in the conversion of image data in this embodiment.

Fig. 10 is a diagram illustrating examples of the number of bits per pixel in this embodiment.

An embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 shows a schematic structural diagram of an embodiment of an image processing device according to the present invention. This example is an example of a game machine having a 3D graphics function and a digital motion picture playback function.

In FIG. 1, reference numeral 41 denotes a system bus (host bus), to which a CPU 42, a main memory 43, and a sorting controller 45 are connected.

Furthermore, the image extension device section 51 is also connected to the system bus 41 via an input FIFO buffer memory (hereinafter simply referred to as a FIFO buffer) 54 and an output FIFO buffer memory 55 . Also, a CD-ROM decoder 52 is connected to the system bus 41 via a FIFO buffer 56, and an imaging device section 61 is also connected to the system bus 41 via a buffer 62.

The frame memory 63 is connected to the imaging device section 61 . As will be described later, the image data formed according to an imaging command and the image data decoded by the image extension device section 51 are written in the frame memory 63 so that the reproduced image is displayed on the image monitor. device 67.

The control keyboard 71 is connected to the system bus 41 via the interface 72 as an operation input device. Furthermore, the boot ROM 73 is a memory for programs for starting the game machine, and is also connected to the system bus 41 .

The CPU 42 executes control over the entire device. In the device of the present embodiment, there are two modes to choose from, i.e. the first mode (hereinafter referred to as normal mode), wherein the image display data from the frame memory 63 is used as the image data of 15 bits/pixel, for R , each of G and B is 5 bits (hereinafter referred to as image data of the first bit number); The bit/pixel image data is 8 bits for each of R, G, and B (hereinafter referred to as image data of the second number of bits). The CPU 42 performs a mode switching operation accordingly.

Also, where the object is imaged as a large number of polygons, the CPU 42 is used as part of performing these operations. That is, as described later, the CPU 42 forms an example of an image forming command to form a drawing image corresponding to an image field on the main memory 43 .

Furthermore, the CPU 42 has a cache memory 46 and can execute a part of CPU instructions without fetching information from the system bus 41 . The coordinate calculation means section 44 which performs coordinate transformation calculation with respect to these polygons when forming an imaging command is provided as an internal coprocessor of the CPU 44 . The coordinate calculation means 44 performs three-dimensional coordinate transformation on the display image field and conversion from three-dimensional to two-dimensional coordinates.

Therefore, since the CPU 42 includes the built-in instruction cache 46 and the coordinate calculating device section 44, the CPU can perform its processing without using the system bus 41 to some extent. Therefore, the system bus 41 seems to be idle.

A CD-ROM decoder 52 is connected to a CD-ROM drive 53 to decode data recorded on a CD-ROM disc mounted on the CD-ROM drive 53 . Image data of application programs such as a game program, moving and still images subjected to image compression such as discrete cosine transform (DCT) processing, and image data of structural images for decorating these polygons are recorded in the the CD-ROM. The CD-ROM disc application includes multi-edge imaging instructions. The FIFO buffer 56 has a capacity corresponding to one sector of CD-ROM disc recording data.

Image expansion means 51 performs expansion processing for compressed image data reproduced from a CD-ROM, and it has a decoder hardware for Huffman (Huffman) code decoding, an inverse quantization circuit, inverse discrete cosine sum conversion circuit. The processing of the decoder portion of the Huffman code can be processed as software in the CPU.

In this example, the image expansion section 51 can perform decoding processing for two modes, i.e., a decoding processing mode for expanding compressed image data into image data of the first bit number of 15 bits/pixel, And another decoding processing mode for expanding the compressed image data into image data of the second bit number of 24 bits/pixel.

The CPU 42 sends the mode switching command to the image expansion device 51 for execution. According to this mode switching command, the image expansion means section 51 decodes the compressed image data into image data of the first bit number in the normal mode and into image data of the second bit number in the high definition mode.

In the case of this example, as will be discussed with respect to Fig. 7, the image stretcher section 51 divides a single (one frame) image into several small areas, for example roughly 16 x 16 pixels ( Each area is hereinafter referred to as a macroblock), and image stretch decoding is performed in units of macroblocks. Therefore, both FIFO buffers 54 and 55 have capacities corresponding to such macroblocks.

The frame memory 63 is connected to the imaging section 61 via the local bus 11. The imaging device 61 executes the imaging command transmitted from the main memory 43 via the buffer FIFO 62 , and writes the result into the frame memory 63 . Imaging performed according to the imaging command is performed only in the normal mode. However, the graphic image data is image data having a first bit number of 15 bits/pixel. Also, the FIFO buffer 62 has a storage capacity corresponding to one imaging command.

The frame memory 63 has an image storage area for storing imaging images and moving images used for display, a structure area for storing structure images, and a table memory for storing a color lookup table (color conversion table CLUT). district. The color look-up table can be used in two types of modes, namely normal mode and high-definition mode. In some cases, part of the high-definition mode can be used in normal mode.

FIG. 2 shows a memory space of the frame memory 63 . The frame memory 63 is addressed with two-dimensional addresses, row addresses and column addresses. In this two-dimensional address space, area AT is used as a structure area. Various types of structural patterns can be arranged in the structural area AT. AC represents the table memory area of the color conversion table CLUT.

As will be discussed later, the data of the color conversion table CLUT is transferred from the CD-ROM disc to the frame memory 63 by the memory controller 45 via the CD-ROM decoder 52 . The structured image data of the CD-ROM disc is extended by the image extending means section 51, and transferred to the memory 63 via the main memory 43.

Also, AD in FIG. 2 denotes an image memory area having frame buffer memories corresponding to two surfaces of one area for imaging and the other area for display. In this example, the frame buffer currently used for display is called the display buffer, and the frame buffer used for imaging is called the imaging buffer. In this example, while one is used as an image buffer for imaging, the other is used as a display buffer. If imaging is complete, both buffers are switched. Switching between the imaging buffer and the display buffer is performed synchronously with the vertical sync pulse when the imaging operation is complete.

In this example, two readout circuits (unpack circuits) for reading out data from the display buffer of the frame memory 63 are provided. That is, the division circuit 64 is a readout circuit for the normal mode, and it reads out image data from the display buffer of the frame memory 63, every 15 bits as 15 bits/pixel (may be regarded as 2 bytes/one image) white). Moreover, the dividing circuit 65 is a readout circuit for high-definition mode, and it reads out image data from the display buffer of the frame memory 63, and every 24 bits is regarded as 24 bits/pixel (3 bytes/one pixel) .

The division circuits 64 and 65 are switched by the changeover switches SW1 and SW2. SW1 and SW2 are provided in an explanatory manner, and the on-off of the dividing circuits 64 and 65 is actually realized by a switching control signal

Switching of the dividing circuits 64 and 65 is effected by a switching control signal from the imaging device section 61 . Since the mode switching instruction is given from the CPU 42 to the image forming apparatus portion, the image forming apparatus 61 forms switching control signals for SW1 and SW2 in accordance with this instruction. The mode switching command from the CPU 42 is given in accordance with switching between the display buffer area and the imaging buffer area of the image memory area AD of the frame memory 63 . According to the operation of writing the image data into the frame memory 63, the CPU 42 recognizes whether the data currently being processed is the image data of the first bit number or the image data of the second bit number. The converted image data is sequentially written into the imaging buffer of the memory 63 .

As described above, the image data that has been read out by the dividing circuit 64 or 65 is converted into an analog image signal by the D/A converter 66, and is sent to the image monitor device 67 and displayed on its image field. Also, the bit numbers of the D/A converter 66, input image data R, G, and B are changed corresponding to switching of the mode, and this switching operation is carried out accordingly.

The selection controller 45 has a function similar to that of a so-called DMA controller, and forms a converter device part for performing conversion of image data between the main memory 43 and the imaging expansion device part 51 and from the main memory 43 to The imaging of the imaging device section 61 instructs conversion of lines. The selection controller 45 performs the switching process without the intervention of the CPU 42, finding time slots when other devices, such as the CPU 42 or the control board 71, make the system bus 41 free. In this case, it is possible for the CPU 42 to monitor the free state of the system bus 41 to the selection controller 45 , that is, it is possible for the selection controller 45 to forcibly request the bus to resist the free state of the CPU 42 .

The main memory has a storage area for compressed image data and a storage area for expanded image data which has been subjected to expansion decoding processing as image data of moving or still images. Also, the main memory 43 has a storage area (hereinafter referred to as a packet buffer storage area) for graphic data such as an imaging command line.

The packet buffer memory is used to set the imaging command line and to switch the imaging command to the imaging device section 61 by means of the CPU 42 so that it is shared by the CPU 42 and the imaging device section 61.

In this example, in order to make this processing run in parallel by the CPU 42 and the imaging device section 61, two packet buffers are provided, that is, a packet buffer for setting the imaging instruction line (hereinafter referred to as the setting packet buffer memory) and the packet buffer memory used for transformation (hereinafter referred to as the execution packet buffer memory). While one is used as a setup buffer, the other is used as an execution packet buffer. When the execution is done with the execution packet buffers, the functions of the two packet buffers are changed, and the working process of the device will now be described.

[Read data from CD-ROM]

When the power supply of the device (game machine) shown in Fig. 1 is switched on and the CD-ROM disc is loaded, the program for starting the initial step is executed by the CPU 42, that is, the gate circuit of the toot ROM73 is started. The recorded data of the CD-ROM disc is loaded. At this time, a decoding process for each user data is performed based on the identification information ID in each sector of the user data of the CD-ROM disc, and the data is detected. According to the result of the detection, the CPU 42 executes the process in response to the playback data with the content indicated by each ID.

That is to say, compressed image data, imaging command and the program that will be carried out by CPU 24 are read from this CD-ROM disk through CD-ROM drive 53 and CD-ROM decoder 52 and input to by selection controller 45 in the main memory 43. In addition to this data, the information of the color conversion table is also sent to the area CLUT of the frame memory 63 .

[Involves processing and transmission of imaging commands]

An image of a plurality of polygons constituting the target surface can be stereoscopically imaged by sequentially imaging the polygons starting with a polygon located at a deep position in the depth of the Z data of the three-dimensional information data. Display the surface in a 2D image. Therefore, the CPU 42 constitutes the imaging instruction line on the main memory 43 so as to sequentially execute the imaging operation in the imaging device section 61 in accordance with a polygon positioned from the depth direction.

Also, a so-called Z-buffering method is adopted in this computer graphics, wherein Z data for each pixel is stored in a memory, and its display priority is determined for each polygon (Z-buffering method in Japanese Patent It is described in application Heisei-05-190763, which was filed by the present applicant on Jul. 2, 93, the Japanese patent application with US application pending). However, since Z data is stored in this Z-buffering method, a long-capacity memory must be used. Thus, the process for determining the display priority order of polygons in this example is executed by the CPU 42 in the following manner.

For this reason, the polygon imaging instruction IP in this example has a structure as shown in Fig. 3A. That is, the polygon imaging command ID has a header at the leading edge of the polygon imaging data PD. The header part carries a tag TG and a command identification code CODE.

The address with respect to the main memory 43 in which the next imaging command is stored is written in the tag TG. The command identification code CODE includes identification data indicating the contents of an imaging command and necessary data for imaging. The polygon imaging data PD includes data such as coordinates of polygons. For example, when the imaging order IP is a rectangular polygon and the interior of the polygon is transformed in a color, the identification data IPD will indicate this fact. Color data used for conversion is described as other necessary information.

Fig. 3B shows a case of an imaging command of a rectangular polygon. Four coordinates (X0, Y0), (X1, Y1), (X2, Y2) and (X3, Y3) are described in the polygonal imaging data PD. Color data (RGB) for transforming the interior of a polygon with a single color is also included.

The CPU 42 calculates the movement of the object and the eye point based on the operation input by the user from the control keyboard 11, and forms a polygonal image instruction line on the main memory 43. Subsequently, the tags of the polygon imaging instruction line are rewritten in the order shown by the Z data. At this time, the address of each imaging command on the main memory 43 is not rewritten but only the flag.

When the imaging instruction line is completed, the selection controller 45 sequentially follows the tag TG of each imaging command, and transfers the data from the main memory 43 to the imaging device section 61 for each imaging command. For this reason, it is sufficient that the FIFO buffer 62 has a capacity corresponding to one imaging command.

In the imaging device part 61, since the data that has been fed has been stored, as shown in FIG. The sequence is executed and the result is stored in the image memory area AD of the frame memory.

According to the imaged polygons, the data is sent to the gradient calculation unit of the imaging device 61 to perform gradient calculations. This gradient calculation is a calculation to find the plane of the transformed data when the interior of the polygon is filled with transformed data in polygon imaging. In the case of this structure, the polygon is filled with structure image data, and in the case of gray scale, the polygon is filled with data of brightness values.

In the case of structures associated with polygons forming the surface of an object, the structure data of the structure area AT is subject to a two-dimensional transform transformation.

For example, the structure figures T1, T2, T3 shown in FIG. 5A are converted into coordinates on a two-dimensional screen so that they are connected to the polygons of the target surface shown in FIG. 5B. The structure patterns T1, T2 and T3 that have been thus transformed and converted are associated with the surface OB1 shown in Fig. 5C. This is arranged in the image memory area A01, and is displayed on the display image field of the image display monitor 65 thereupon.

In the case of a still image structure, the structure pattern on the main memory 43 is transferred to the structure area AT on the frame memory 63 via the imaging device section 61 . In the imaging device part 61, it is attached to the polygon. Therefore, the structure of the still image is realized on target. Such data of structural patterns of still pictures can be stored in a CD-ROM disc.

Furthermore, it is possible to provide the structure of moving pictures. In the case of the motion picture structure, the motion picture data which has been decoded in the picture expander section 51 to effect expansion is sent to the structure area AT on the frame memory 63 as described below. Since the texture area AT is provided in the frame memory 63, the texture pattern itself can be rewritten for each frame. Therefore, when a moving picture is sent to the texture area AT, the texture is automatically rewritten and changed for each frame. The motion structure can be realized if the transformation of the structure into polygons is performed by the motion graphics of the structure area AT.

[Expansion and Transformation of Compressed Image Data]

In addition to the input data of the main memory 43, compressed data is written (by the CPU 42) in the main memory 43 again after the CPU 42 has performed the decoding process of the Huffman code. Subsequently, the selection controller sends the image data that has been processed by Huffman from the main memory 43 to the image expander section 51 via the FIFO buffer 54 . Prior to this, the CPU 42 sends an instruction to the image expansion device 51 whether to perform decoding in the normal mode or in the high-definition mode. The inverse quantization process and the inverse DCT process are performed in the image expansion means 51, and the expansion decoding process for the image data is performed in accordance with the mode of the instruction from the CPU 42.

The selection controller 45 sends the expanded image data to the memory 43 via the FIFO buffer 55 . In this case, as described above, the image expansion means section 51 performs expansion processing in units of macroblocks. For this reason, the selection controller 45 transfers the compressed data in units of macroblocks from the main memory 43 into the input FIFO buffer 54 . Thereupon, when this expansion decoding process is finished, this image expansion means 51 inputs the expanded image data as a result to the output FIFO buffer 55, and simultaneously obtains the next macro data from the input FIFO buffer 54 block of compressed data in order to thereby perform an expansion decoding process.

If the system bus 41 is in a free state and the FIFO buffer 55 of the image expander part 51 is not empty, the selection controller 45 will switch the expanded image data of one macroblock to the main memory 43, and transfer the next The compressed image data of one macroblock is transferred to the input FIFO buffer 54 of the image expander section 51 .

When a predetermined set of macroblocks of expanded image data is loaded in the main memory 43, the CPU 42 converts the expanded data into the frame memory 63 via the imaging set section 61. At this time, if the expanded image data is transferred to the image memory area AD of the frame memory 63, the data will be displayed on the image monitor 65 as a background moving image without any modification. Also, these data are sometimes sent to the structure area AT of the frame memory 63 . The image data of the structure area AT is used for the correction of the polygon as the structure image.

In this case, the graphic image is synthesized with the background moving image, and the image data of the background moving image is expanded-decoded or image data of the first bit number in the normal mode, and converted to the frame memory 63 . Also, the expanded image data is converted to the texture area AT, and in the same manner, the data is expanded-decoded as the image data of the first bit number of the normal mode. The reason for this is that the graphic image data is constituted with the first number of bits. However, in the case where the background image is not synthesized with the graphic image, the data is expansion-decoded into image data of the second bit number with high definition.

Incidentally, the image data expanded and decoded in the image expander section 51 is transferred from the main memory 43 to the frame memory 63 . In this example, its conversion instruction is used in the following manner. Such an exchange of the expanded image data into the conversion instruction type is carried out in the CPU 42 .

That is, FIG. 6 is a schematic diagram of a structure of such a conversion instruction. The conversion command is of almost the same type as the imaging command, with a tag TG at its leading edge, followed by identification data IDP. In the same manner as the imaging instruction, the tag TG includes the address value of the main memory 43 in which the next imaging instruction or conversion instruction is stored, indicating the data representation of the fact that the conversion instruction for expanding the image data is described in the identification data in the IDP.

In FIG. 6, next data "H" and "W" indicate the height and width of the extended data area to be converted. The height and width correspond to the area of the video field of one frame. Also, the data "X" and "Y" indicate the coordinates of the position to which the data can be converted. Since its transformation area is a rectangle, each coordinate indicates the coordinate of the upper right area of the rectangle. Each coordinate is a coordinate in the area AD if the converted position is in the image memory area AD of the frame memory, and each coordinate is a coordinate in the area AT if the converted position is in the area AT.

In the case of the conversion command of the expanded image data, the conversion from the tag TG area to the coordinates X, Y and the size of the title are indicated by the identification data IDP. The conversion from the identification data IDP to the coordinates X, Y corresponds to the command identification code CODE of the imaging command shown in FIG.

The conversion command includes pixels PIX0, PIX1, PIX2, . . . , PIYn of expanded image data following the header. As mentioned above, each pixel has 15 bits in normal mode and 24 bits in high definition mode. Via the imaging device section 61, the expanded image data is switched from the main memory 43 to the frame memory 63 in units of switching instructions from the selection controller 45.

In addition, as described above, the image expansion means section 51 divides one frame of image into macroblocks including length x width = 16 x 16 to perform expansion decoding in units of blocks. For example, assuming that the picture includes a frame of length×width=320×320, one frame is divided into 300 macroblocks as shown in FIG. 7 .

When converting 300 macroblocks to the imaging device section 61, in the case where these conversion instructions are formed into macroblocks, the front end of the header section is too large. Thus in this example, as shown in FIG. 1, a plurality (15 in FIG. 18) of macroblocks in the longitudinal direction are coupled as a unit to be fed by the conversion command.

An example of the first conversion command for one frame is shown in FIG. 9 . In FIG. 9, the coordinates X, Y are 0,0. In the next transformation instruction, the coordinates X,Y are 16,0.

Therefore, since the expanded image data is transformed into the conversion instruction type in the same manner as in the imaging instruction, the process of mixing, imaging, and image of the polygon-forming imaging instruction and the transfer instruction performed by the selection controller 45 Formation can be performed in the frame memory 63 by the imaging device part using the tag TG.

[Explanation of the process of reading image data from the frame memory]

First, the CPU 42 sends an instruction to the imaging device section 61 to send image data of a frame buffer A (becoming a display buffer) of the image storage area AD of the frame memory to the image monitor 67. At this time, the CPU 42 also sends to the imaging device section 61 a mode switching control signal instructing whether the normal mode or the high definition mode is used.

When designated as the normal mode, the imaging device section 61 switches the switches SW1 and SW2 to the terminal N side, and the expansion circuit 64 is selected. At this time, each (two bytes) of the pixel data PIX of every 15 bits is written in the display buffer memory of the image storage area AD of the frame memory 63 in the manner circled by the ellipse line in Fig. 10A middle.

As described above, the expansion circuit 64 reads out each 15-bit image data from the display buffer memory of the image storage area AD of the frame memory, and sequentially converts the read data to the A/D converter 66 to Transform analog signals. Accordingly, a reproduced image is formed on the image field of the image monitor device 67 . In this case, what is replayed in normal mode is:

i) graphic images only;

ii) superimposing the obtained structure image on the synthetic image of the imaged polygon;

iii) Composite images obtained by dilated decoders, imaged as multiple polygons in background images comprising 15 bits/pixel moving or still images;

iv) A moving picture or a still picture of 15 bits/pixel obtained only by an expansion decoder, etc.

When the high-definition mode is designated, the imaging device section 61 switches the switches SW1 and SWZ to the terminal H side, and selects the division circuit 65 . At this time, each (three bytes) of data PIX for every 24-bit pixel is written in the display buffer of the image storage area AD of the frame memory 63 in a manner encircled by an ellipse line as shown in FIG. 10B in memory.

The division circuit 65 reads out image data each of 24 bits from the display buffer memory of the image storage area AD of the frame memory, and sequentially converts the read data to the A/D converter 66 to convert an analog signal. Accordingly, a reproduced image is formed on the image field of the image monitor device. In this case, what is displayed in the high-definition mode is a moving picture or a still picture of 24 bits/pixel obtained by expansion decoding.

While the image data of the frame buffer A is being read, the CPU 42 generates data in the main memory 43 to be subsequently sent to the imaging device 61 . In the generation process of the imaging instruction line, the operation input of the control panel 71 is read out, and in response to this operation input, the coordinates of the imaging instruction line of the data packet buffer (becoming the setting data packet buffer) of the main memory 43 The values are refreshed, while at the same time the flags for each imaging command of the imaging command line are overwritten. In the case of expanded image data, the data is converted into the conversion instruction type as described above. The CPU 42 recognizes that the data is expanded image data of 15 bits/pixel or data of 24 bits/pixel.

While the CPU 42 processes the formation of imaging commands or converts expanded image data into switching commands, the selection controller 45 switches the imaging command line or the expanded image data from the main memory 43 to another frame buffer area B ( becomes an imaging buffer). At the same time, the CPU 42 recognizes that the conversion data is an imaging command line, or 15 bits/pixel expanded image data or 24 bits/pixel expanded image data.

Subsequently, when all imaging command lines or conversion command lines were converted from the main memory 43, the CPU 42 then utilized other frame buffer areas B of the frame memory 63 as a display buffer, and instructed the imaging device part 61 to read the image image data or expanded image data, and output these data to the imaging monitor 65. At this time, the CPU 42 also sends the mode switching signal to the imaging device section 61 in the same manner as previously described. As previously described, the imaging device section 61 performs switching of the switches SW1 and SW2 and performs readout processing in response to the normal mode and the high-definition mode. Also, in this case, the frame buffer A of the frame memory is simultaneously switched to the imaging buffer.

While reading image data using the other display buffer B as a display buffer, the CPU 42 generates data in the main memory 43 to be sequentially transferred to the imaging device section 61 as described above. When CPU 42 processes imaging command formation or changes the expanded image data into a conversion command type, the imaging command line or expanded image data is converted from main memory 43 to a frame buffer area A ( into the image buffer).

A moving picture can be displayed by repeating the previous operation. In addition, the expansion circuits 64 and 65 are switched in response to the normal mode and the high-definition mode, and the image data written in the frame memory 63 can be read in response to the image quality for processing.

Incidentally, in the foregoing description, examples of two kinds of bit numbers per pixel have been given. However, the present invention is equally applicable to the case where each pixel has three or more bit numbers.

Also, in the foregoing example, image data or application programs are recorded on a CD-ROM disc. However, any other kind of recording medium such as semiconductor memory type, magnetic disk, memory card can be used as the recording medium.

Also, DCT is used as a data compression method for images, but any other image data compression method can be used.

Various detailed changes may be made to the present invention without departing from the spirit and scope of the invention. Moreover, the foregoing descriptions of the embodiments according to the present invention are for the purpose of illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.

Claims (8)

1. In a device having a frame memory for sequentially reading image data written in the frame memory for image display data, an image processing device is characterized in that it comprises: Identification means for identifying whether the image data written in the frame memory is image data written in a first number of bits per pixel or a second number of bits different from the first number of bits per pixel the image data written; The first image data reading device is used to read the image data about each pixel represented by the first bit number from the frame memory; A second image data reading means for reading image data about each pixel represented by the second bit number from the frame memory; and switching means for switching the first image data reading means and the second image data reading means according to the identification information from the identification means. 2. An image processing device, characterized in that it comprises: a frame memory; imaging means for performing imaging operations according to imaging instructions on said frame memory to form graphic image data, wherein each pixel on said frame memory includes a first number of bits; Image data writing device, is used for sequentially writing the image data that has been converted to this frame memory on said frame memory; Identifying means for identifying whether each pixel of the converted image data consists of a first number of bits or a second number of bits greater than the first number of bits; The first image data reading device is used for reading the image data about each pixel represented by the first bit number from the frame memory; The second image data reading means is used for reading the image data about each pixel represented by the second bit from the frame memory; and switching means for switching the first image data reading means and the second image data reading means according to the identification information from the identification means. 3. The image processing apparatus according to claim 2, wherein the image data converted to said frame memory is image data such as moving images and still images, said image processing apparatus further comprising when these means for forming these graphic data and graphic image data when the data consists of first bit image data. 4. The image processing apparatus according to claim 3, wherein the imaging command corresponds to an operation input from the operation input unit. 5. The image processing apparatus according to claim 4, further comprising a disk reproducing section, wherein the image data is generated from a disk mounted on said disk reproducing section. 6. The image processing device according to claim 5, further comprising a D/A conversion circuit for converting a digital signal into an analog signal, wherein the digital signal is input to the D/A conversion circuit and converted into an analog signal to be output from the D/A conversion circuit by said switching means. 7. The image processing apparatus according to claim 6, further comprising a common system bus for connecting signals from said input means, said image forming means, and said disc playback section. 8. The image processing apparatus according to claim 7, further comprising a plurality of buffer memories between said common system bus, said image forming apparatus, and a playback portion of said disk.

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