CN1306731C - Device and method for realizing shared data path with transmission overhead path - Google Patents

Abstract

The present invention discloses a device for realizing a shared data path by using a transmission overhead path and a method. The device comprises a bus receiving and sending component for providing the bus drive, a programmable logic device (PLD) connected with the bus receiving and sending component for completing the main logic process, and a communication port component connected with the programmable logic device for completing the level conversion of the logic level to the outer part of data. By adopting the device and the method of the present invention, compared with the prior art, the channel application in a shared form is realized by a digital channel of point to point. The user port is saved, and the applied range of the interface is widened. The utilization ratio of the overhead channel is improved.

Description

A device and method for implementing a shared data channel by using a transmission overhead channel

Technical field

The invention relates to a point-to-point overhead channel of optical synchronous digital transmission equipment in the communication field, and in particular to a device and method for realizing a shared data channel by using the overhead channel.

Background technique

Optical Synchronous Digital Transmission Hierarchy (SDH) stipulates a series of overhead bytes to realize functions such as network management and monitoring. Among the overhead bytes, some bytes are not yet defined, and these bytes can be used to provide users with additional digital or analog channels. See the Chinese national patent CN1269645A for specific implementation, the patent title is "Analog and Data Interface Device for Optical Synchronous Digital Transmission Equipment".

Since the overhead channel of the optical transmission equipment is point-to-point transmission, overhead bytes must be terminated and regenerated at each node. Therefore, to realize full-duplex communication between every two nodes generally needs to occupy an overhead channel, and to realize full-duplex communication between a node and two nodes upstream and downstream of the node simultaneously requires the use of overhead channels in two directions. Use two communication interfaces to communicate with two upstream and downstream nodes.

In some applications, it is required to use only one communication interface and one overhead channel to communicate with upstream and downstream nodes. This form of application is the application of "shared" bus. Common forms of shared data links, such as Ethernet and RS485, are not suitable for point-to-point interface applications.

Contents of Invention

The purpose of the present invention is to overcome the shortcomings of the prior art, to provide a shared channel using point-to-point overhead channels, and to use only one communication port at each node to communicate with upstream and downstream nodes. A device that communicates with multiple nodes using a single communication port.

Another object of the present invention is to provide a method for implementing a shared data channel by using a transmission overhead channel.

In order to solve the above-mentioned task, the present invention provides a kind of device that utilizes the transmission overhead channel to realize the shared type data channel, includes the bus transceiver element that provides bus drive, the programmable logic device that completes main logic processing that is connected with the bus transceiver element and can communicate with Communication port components for programming logic device connections to complete logic level to data external level translation and port protection. The programmable logic device is composed of the demultiplexing module connected with the bus transceiver element to complete the system bus data conversion, the data sampling connected with the demultiplexing module, and the discrimination and selection of the routing through, routing receiving and routing concurrent functions. It is composed of a road module and a multiplexing module connected with the discrimination road selection module to complete the conversion from the output data of the discrimination road selection module to the system bus data.

The demultiplexing module includes a counter connected to the bus transceiver element, a comparator connected to the counter, a serial/parallel conversion and latch module connected to the comparator, a parallel/serial conversion module connected to the serial/parallel conversion module, One end is connected to the bus transceiver element, and the other end is connected to the parallel/serial conversion module and the serial/parallel conversion and latch module;

The discrimination routing module includes three AND gates connected with serial/parallel conversion elements, one of which is used to receive the data output by the demultiplexing module, and the other two AND gates are used to receive the output data from the demultiplexing module. Data and sampling data sent by the station controlled and output by frequency division components;

The multiplexing logic module includes: an AND gate for receiving the output data of the demultiplexing module and a shift register connected with the counter in the AND discrimination routing module, a latch connected with the shift register, and a gate connected with the counter It is connected with another counter, a comparator connected with another counter, a parallel/serial conversion element connected with the latch and the comparator, and a superposition module connected with the parallel/serial conversion element at one end and the communication port element at the other end.

The invention provides a transmission method for realizing a shared data channel by using a transmission overhead channel: the signal bus received from the system side is received and regenerated from the bus transceiver element, and then enters a programmable logic device for processing, and the processed multi-channel signal is completed Enter the communication port component send.

The present invention also provides a receiving method for realizing a shared data channel by using the transmission overhead channel: the multi-channel signals received from the communication port components enter the programmable logic device for processing, and the processed signals enter the bus transceiver components to be driven and then sent to the system one side.

The device and method of the present invention have the following characteristics: 1. There is no limit to the transmission data rate and the number of data bits. 2. A slight change to the discriminative routing module can meet the requirements of multi-site communication. 3. It does not process the content of the data channel, does not increase additional overhead, and realizes transparent transmission. 4. No need for external protocol processing. 5. Suitable for master-slave communication applications. 6. It can be expanded to adapt to point-to-point link and PDH line applications. Therefore, by adopting the device of the present invention, compared with the prior art, the point-to-point digital channel has realized the channel application of the shared form, saving user ports, It broadens the scope of interface adaptation and improves the utilization efficiency of overhead channels.

The present invention will be illustrated by means of embodiments with reference to the accompanying drawings.

Description of drawings

Fig. 1 is a diagram of the physical connections of the device of the present invention.

Fig. 2 is a relational diagram of the internal space structure of the programmable logic device of the device of the present invention.

Fig. 3 is a logical schematic diagram of the digital circuit of the demultiplexing module of the programmable logic device of the device of the present invention.

Fig. 4 is a logical schematic diagram of the digital circuit of the discriminating and routing module of the programmable logic device of the device of the present invention.

Fig. 5 is a logical schematic diagram of the digital circuit of the multiplexing module of the programmable logic device of the device of the present invention.

Fig. 6 is a schematic diagram of a known technical device.

Fig. 7 is a schematic diagram of an implementation of the device of the present invention.

Fig. 8 is a schematic diagram of another implementation of the device of the present invention.

Detailed ways

Referring to the accompanying drawings, specific embodiments of the present invention will be described in detail.

In order to solve the problem that the overhead byte in the optical synchronous digital transmission system is point-to-point communication and cannot realize the application of shared channels, the device of the present invention proposes the following idea: use point-to-point channels to form a source-selectable bidirectional direct channel at each site, Select one way to receive in two receiving directions at the same time. Its design is based on the communication principle of general full-duplex data channel type (such as RS232, RS422 data type), that is, the data is filled with all "1" signals in the channel when there is no data to be sent, and the data field starts with the start bit "1" when data is sent. 0" and end with a stop bit. The optical synchronous digital transmission system requires data to be transmitted transparently, without processing or distinguishing the transmitted data, but in the application of shared form, because it is necessary to determine the presence or absence of data to determine the source of the sending and receiving data, it is necessary to expand the application of the usual transmission equipment , that is, it is necessary to distinguish the type of data and dynamically determine the direction of the data.

The device of the present invention is shown in Fig. 1, and the hardware part is composed of three parts, including a bus transceiver element, a programmable logic device connected with the bus transceiver element and a communication port element connected with the programmable logic device.

The bus transceiver component mainly completes the driving of the system bus transceiver direction, provides adaptation with internal and external circuits, and can be realized by a bus driver chip. The system bus rate shown in this embodiment is 8Mbps; the programmable logic device is the core of the system. Complete all logic functions; the communication port component completes the adaptation, conversion and interface protection of the internal and external electrical properties of the port. It is composed of an interface circuit chip and a protection device. The protection device can be composed of a thermistor device and an overvoltage protection device. This embodiment Take the IEEE RS232 standard interface as an example.

Figure 2 shows the internal spatial structure relationship and signal flow diagram of the programmable logic device. The programmable logic device is composed of a demultiplexing module connected to the bus transceiver element to complete the system bus data conversion, and a data sampling connected to the demultiplexing module. It is composed of a discriminative routing module with routing direct connection, routing receiving and routing concurrent functions, and a multiplexing module connected with the discriminative routing module to complete the conversion from the output data of the discriminative routing module to the system bus data.

As shown in the figure, the 8M bit/s overhead byte bus (or different time slots in the bus) from two optical directions, after passing through the demultiplexing module, the selected time slot is taken out and converted into 64k data signal, and send the 64k data signals from two directions to the discriminative routing module for discrimination and routing; the multiplexing module multiplexes the 64k data signals from the discriminative routing module into the corresponding time slot of 8M; the discriminative routing module The route module completes the route selection and reception from the two receiving channels, selects the received data and sends it to the receiving end of the interface chip, and at the same time selects the data with signals from the data sent by the local end and the received data in the two directions and sends them to the east direction respectively. and the westward sending port are inserted into the corresponding time slots of the 8M bus of the system through the multiplexing module.

Fig. 3 shows the circuit diagram of demultiplexing module, and described demultiplexing module comprises the counter that is connected with bus transceiver element, the comparator that is connected with counter, the series/parallel conversion and latch module that are connected with comparator, and The serial/parallel conversion module is connected to the parallel/serial conversion module, one end is connected to the bus transceiver element, and the other end is connected to the parallel/serial conversion module and the serial/parallel conversion and latch module.

The demultiplexing module uses the 8M clock from the system direction to count, the 8k frame header of the system is used as the initial value of the counter, and the pulse signal of the selected time slot obtained by comparing the counting result with the selected time slot is sent to the serial/parallel conversion The module is used as the initial pulse of the serial-to-parallel conversion. At the same time, the 8M system HW line and the 8M system clock are also sent to the serial/parallel conversion module as data and clock signals for conversion and latching. At the same time, the 64k clock signal generated by the 8M clock count is also locked. The stored data is sent to the lower-level parallel/serial conversion module, and the parallel/serial conversion is performed together with the system's 8k frame header, and the output 64k data is sent to the lower-level discrimination and routing module.

The discriminative routing module shown in FIG. 4 is realized according to the technical solution, and the discriminative routing module includes three AND gates connected to serial/parallel conversion elements. Since the effective data starts with the number "0", the discrimination and route selection can be automatically realized by logic AND gate circuit. The result is that valid data is received; similarly, there may be two sources of data sent eastward: the data sent from the west and the 64k data sent from this point, and the valid data is selected and sent to the east; the data sent from the east It is compared with the 64k data sent by this point as the data sent westward. The 64k data sent by the station is obtained by sampling the data sent by the station through a 64k clock synchronized with the sending direction.

Fig. 5 shows the schematic diagram of the multiplexing module, and the multiplexing logic module includes: an AND gate for receiving the output data of the demultiplexing module and a shift register connected with a counter in the AND discrimination routing module, and a shift register A latch connected to a register, a counter connected to another counter, a comparator connected to another counter, a parallel/serial conversion element connected to a latch and a comparator, one end to a parallel/serial conversion element to the other Stacking modules connected to communication port elements.

The 64k clock and 64k data obtained by frequency division of the 8M system clock enter the shift register and are latched by the 8k system frame header to become 8-bit parallel data. The count value is compared with the selected 64k time slot, and the selected time slot frame positioning signal obtained, together with the above 8-bit parallel data and the system 8M clock, is converted into an 8M signal through parallel/serial conversion, and several 8M signals are superimposed as a system 8M HW line output.

Figure 6 is a schematic diagram of the prior art. The three points A, B, and C are three communication sites. Each site performs full-duplex communication through a port and an adjacent port. Each site needs to be configured with two ports and two sites on the left and right. Communication; Fig. 7 is according to the embodiment of this technical scheme, is connected by an overhead byte in the middle, and each node has a full-duplex communication port to communicate with two nodes on the left and right, for the "shared" form bus of master-slave mode application In general, only one node sends data at each moment, all nodes receive it, and only one node responds after receiving and discriminating. This device can be well adapted to this form of application. For the application form regardless of master-slave, for conflicting or wrong information, the node performs protocol processing such as discarding and verifying, delaying reception or sending handshake after receiving it, which can be realized in software form, does not involve this hardware device, and will not be described in detail .

Fig. 8 is the schematic diagram of embodiment two of described device, and this station receives the data that sends from station one and station two, station three, selects the one that has data to receive; Among the data received in other directions, select the one that has data to send and send it to the stations in the other three directions.

The transmission direction of the device receives the signal bus from the system side after being received and regenerated from the bus transceiver components, and enters the programmable logic device for processing, and the processed signal enters the communication port component for transmission. Receiving direction: The signal received from the communication port component enters the programmable logic device for processing, and the processed bus enters the bus transceiver component to be driven and then sent to the system side.

Claims (6)

1. device that utilizes the transport overhead passage realize to share the formula data channel; it is characterized in that: it comprises provides the bus of bus driver transmit-receive cell; programmable logic device that the completion logic that is connected with the bus transmit-receive cell is handled and the completion logic level that is connected with programmable logic device are to the PORT COM element of data external level conversion and port protection; wherein; described programmable logic device is by the demultiplexing module of finishing the system bus data transaction that is connected with the bus transmit-receive cell; what be connected with demultiplexing module finishes data sampling, and routing is straight-through; the differentiation route selection module of routing reception and routing concurrent function and with differentiate finishing that route selection module is connected from differentiating the Multiplexing module composition of route selection module dateout to the system bus data transaction.

2. a kind of device that utilizes the transport overhead passage to realize sharing the formula data channel according to claim 1, it is characterized in that: described demultiplexing module comprises the counter that is connected with the bus transmit-receive cell, the comparator that is connected with counter, the serial/parallel conversion and the latch module that are connected with comparator, the parallel/serial modular converter that is connected with serial/parallel modular converter, an end are connected the counter that the other end and parallel/serial modular converter are connected with serial/parallel conversion and latch module with the bus transmit-receive cell;

Described differentiation route selection module comprises by three that are connected with serial/parallel conversion element and door, one of them is used to receive the data that demultiplexing module is exported with door, in addition two are used to receive the sampled data that the our station by frequency division element control output sends with door, and the data exported of demultiplexing module;

Described multiplexing logic module comprise with differentiate route selection module in be used to receive the demultiplexing module dateout with door and the shift register that is connected with counter, the latch that is connected with shift register, be connected with counter with another counter, the comparator that is connected with another counter, the parallel/serial conversion element that is connected with latch and comparator, an end are connected the laminating module that the other end is connected with the communication port element with parallel/serial conversion element.

3. a kind of device that utilizes the transport overhead passage to realize sharing the formula data channel according to claim 1, it is characterized in that: described PORT COM original paper is made up of interface circuit chips and protector.

4. a kind of device that utilizes the transport overhead passage to realize sharing the formula data channel according to claim 3, it is characterized in that: described protector is made up of thermistor element and over-voltage protector.

5. a kind of sending method of utilizing the transport overhead passage realize to share the formula data channel according to claim 1, it is characterized in that: the signal bus that receives from system side from the bus transmit-receive cell receive and regeneration after, enter programmable logic device and handle, the multiple signals entry communication port element of finishing after the processing sends.

6. a kind of method of reseptance that utilizes the transport overhead passage realize to share the formula data channel according to claim 1, it is characterized in that: the multiple signals that receive from the PORT COM element enter the programmable logic device processing, and the signal after the processing enters and sends to system's one side after the bus transmit-receive cell drives.

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